Dorado Hardware ManualInstruction Fetch Unit14 September 198164Instruction Fetch Unit The instruction fetch unit, or IFU, decodes a stream of bytes from memory into a sequenceof 8-bit opcodes and operands using a writeable decoding memory, and presents theresults to the processor for efficient interpretation.  The next section contains an overviewof IFU function, supplemented by details in later sections.Read this chapter with Figure 12 in front of you.Overview of OperationThe IFU handles four independent instruction sets.  Opcodes are 8-bit bytes, which may befollowed in memory by 0, 1, or 2 operand bytes.  Hence, the total length of an operation is1, 2, or 3 bytes.  The first operand byte is called a, the second b.One method of dealing with operations longer than 3 bytes is to encode them in IFUM as 1-bytejumps to the next operation.  This gives up the possibility of referencing N, a, or b with _Id butavoids having to restart the IFU.  The processor then must compute the proper place in theinstruction stream and reference a, b, g, etc. without help from the IFU.The term PC refers to the displacement of an opcode byte from the codebase, which is BR31.  PC's are 16-bit items, where 0:14 are an unsigned word displacement relative to thecodebase, and bit 15 selects the byte.  In other words, codebase points at a 32k segmentof virtual memory; a PC selects a byte in this segment.  The PC's are named PCF, . . .,PCM, and PCX, where the final letter in the name denotes the level in the IFU pipeline.Since the IFU's PC is only 16 bits, overflowing either end of the code segment causes wraparound.This programming error is not detected by the hardware.For Alto compatibility reasons, we currently have the following kludge.  Instruction sets 0and 1 treat byte 0 in the selected word as bits 0:7, 1 as bits 8:15; instruction sets 2 and 3treat byte 0 as bits 8:15, 1 as 0:7.  Eventually, this may be changed so that all instructionsets use 0 for the byte in 0:7 and 1 for 8:15.The IFU is started by first selecting an instruction set (InsSetOrEvent_B function) and thenloading the F-level PC (PCF_B function).  The IFU then starts fetching the byte streamstarting at the word BR[31] + PCF[0:14], byte PCF[15], from the cache and preparesopcodes for interpretation by the processor.Bytes from the cache then march through the IFU pipeline beginning with the F and G full-word buffer registers on the MemD board; single bytes from F/G then move into J or H onthe IFU board.  InsSet[0:1] and the opcode byte in J address the decoding memory, IFUM,a 1024-word x 24-bit (+3 parity) RAM containing the information in the table below.Although IFUM is writeable, it will normally be loaded with the microprogram and notsubsequently changed (Diagnostics are, of course, an exception.).ÿ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"sqî5pô�îFïfñî·ïa×rp�î·ï^eô�Šð+ô�‹ð.î·ï\›ô�ßô�àð4î·ïZÐô�–ô�—ðAî·ïYô�ð;î»ïU”qô�Xð1î·ïPzsô�î·ïMpô�‰ð3ô�Šð&î·ïK>ô�ô�ŽðCî·ïIsô�ð4t�pt�p�îyïF²uô�©ðKô�ªîyïE-ô�Ÿð"ô� ð,t�ut�uîyïC©ô�Òð!ô�Óð9îyïB%ô�ð!t�ut�ut�uð!î·ï>³pô�Šqpð7qp�ô�‹î·ï<éô�§ô�¨ðTî·ï;ô�˜ð&ô�™ð2î·ï9Tô�®ðEô�¯î·ï7‰ô�·ð'ô�¸ð0îyï4Çuô�“ðaîyï3gô�ð7î·ï0pô�¨ð?ô�©î·ï.Mô�•ð[ô�–î·ï,ƒô�›ðEô�œî·ï*¸ô�ð.î·ï'Fô�	ô�ðRî·ï%|ô�Áð=ô�Âî·ï#±ô�×ô�Øð>î·ï!æô�ð,î·ïtô�‹ð+ô�Œð.î·ïªô�ŽðCô�î·ïßô�’ô�“ð8î·ïô�èô�éð?î·ïJô�Üô�ÝðDî·ïô�ðA��������
è����·8=ðRÓ%������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualInstruction Fetch Unit14 September 198165Table 18:  IFUM FieldsNameSize    ContentsLength' 2Opcode length: 1, 2 or 3 bytes (0 length is illegal).TPause' 1The opcode is of type pause.TJump' 1The opcode is of type jump.IFaddr'10TNIA[4:13] of the first instruction to be executed in interpreting this opcode(TNIA[14:15] from the IFUJump in the exit of the previous opcode).RBaseB' 1RBase initialization, discussed below.MemB 3MemBase initialization, discussed below.Sign 1Operand sign extension, discussed below.Packeda 1Packed a, discussed below.N 4Operand encoded in the opcode, discussed below.Length', TPause', TJump', Sign, Packeda, and N are used by the IFU to prepare operandsand to sequence correctly to the next opcode; IFaddr' is passed to the control section; andthe processor uses MemB and RBaseB' to initialize MemBase and RBase when themicrocode for the opcode commences.Length' determines the number of operand bytes; a for a two or three-byte instruction willbe in H, while b for a three-byte instruction will be in F/G, when the assembled instructionis ready to proceed.  The assembled instruction and a then drop into the M level.IFUJump[n] (see "Control Section") transfers control to the starting instruction for theopcode assembled in M, where TNIA[4:13]_IFaddr, TNIA[14:15]_n (n is 0 to 3) is thelocation of the entry instruction.  A 4-long entry vector, rather than a single startingaddress, can be utilized for faster execution, as discussed later.  IFaddr may be overruledby a trap address when appropriate.At t0 of the starting instruction, the processor initializes RBase to RBaseB (i.e., to 0 or to 1)and MemBase to 0..MemBX[0:1]..MemB[1:2] if MemB[0] = 0, or to 348+MemB[1:2] ifMemB[0] = 1.  MemBX is interpreted as a stack pointer to a 4-entry stack with 4 baseregisters in each entry, and MemB[1:2] in IFUM select a particular base register from thecurrent entry.  The MemBX kludge may reduce computation on procedure call/return, asdiscussed later.  Other information about the opcode and a are copied into the X level.Instructions that implement the opcode then reference operands in sequence using theA_Id, RisId, or TisId operations discussed in "Processor Section" or the IFetch_ operationdiscussed in "Memory Section," which read operands from the X level.  The operandsequence delivered by the IFU in response to _Id is as follows:����������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"sqî5pô�îFïfñî$Cïbsô�Xî­ï_£vîùPøÿúÿîžô�ùÈøÿúÿî­ï]KuùPîô�€ùPøÿúÿîžùÈøÿúÿô�ð/î­ï[¤ù�ø�ú�ùPøÿúÿ�îô�€ùPøÿúÿîžùPøÿúÿô�wu�î­ïZ ù�ø�ú�ùPøÿúÿ�îô�€ùPøÿúÿîžùPøÿúÿô�wu�î­ïXœù�ø�ú�îùPøÿúÿîžô�ìùPøÿúÿô�íð7î~ïW;ô�ðBî­ïU·ù�ø�ú�îô�€ùPøÿúÿ�ù�ø�ú��îžô�ð!î­ïT3îô�€ùPøÿúÿîžùÈøÿúÿô�ð!î­ïR¯îô�€ùPøÿúÿîžùÈøÿúÿô�ð!î­ïQùPt�îuô�€ùPøÿúÿîžùÈøÿúÿô��t�uî­ïO`�îô�€ùPøÿúÿîžùÈøÿúÿô�ð(î·ïLqô�–ù�ø�ú�ô�—t�pq�pð(î·ïJGô�ˆð.qpð&î·ïH|ô�ýqpqpô�þî·ïF²ô�ð#î·ïC@qpô�˜ð)t�pð)î·ïAuô�Œt�pô�ðHî·ï?ªô�ôð4t�p	ô�õî·ï<8ô�ÚðXî·ï:nô�Üô�Ýð?î·ï8£ô�åð2ô�æð&î·ï6Ùô�›ð#ô�œð!qpî·ï5ô�ð#î·ï1œô�…ï1u�ï1œpô�†ð$qpî·ï/Ñô�êð*ô�ëï/Du�ï/Ñpî·ï.ô�·ô�¸ðAî·ï,<ô�§ð7ô�¨ð"î·ï*rô�©ô�ªð4î·ï(§ô�´ð8ô�µ�t�pî·ï%5ô�ÉðTî·ï#jô�ðHô�Žî·ï! ô�ÖðIô�×î·ïÕô�ð?��������	T����·Ž<ðH}®��������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualInstruction Fetch Unit14 September 198166Table 19:  Operand Sequence for _IdTypeLengthPackedaSequence0IllegalJump1Length, Length, Length, . . .Packeda, sign, and N determine jump displacement.Jump2Length, Length, Length, . . .Packeda and N are unused; sign extends the sign of a for thejump displacement.Jump3IllegalRegular1N if N ne 178, Length, Length, Length, . . .Packeda and sign are unused.Regular20N if N ne 178, a, Length, Length, . . .a is sign-extended if sign = 1.Regular21N if N ne 178, a[0:3], a[4:7], Length, Length, . . .Sign is unused.Regular30N if N ne 178, a, b, Length, Length, . . .a is sign-extended if sign = 1.Regular31N if N ne 178, a[0:3], a[4:7], b, Length, Length, . . .Sign is unused.PausexxSame as regularRegular and pause opcodes have an optional 4-bit operand N that is delivered first (N isn't suppliedwhen N = 178).  This is followed by a and b, if they exist; a is sign-extended when sign = 1 orsplit into two 4-bit nibbles if Packeda = 1.  Subsequently, _Id delivers Length.  For jumps, all ofthese operands are consumed in computing the jump displacement, and _Id delivers Length.The normal opcode references all of its N, a, and b operands; however, except on three-byte opcodes, the IFU hardware does not require that these operands be referencedtheprocessor could exit to the next opcode without reading all the operands, if that wasdesirable for some reason.  However, for opcodes of length 3, the processor must consumethe a byte with _Id (both a[0:3] and a[4:7] if Packeda=1) before going to the next opcodewith an IFUJumpit does not suffice to consume the last a byte with _Id concurrent withIFUJump.  An opcode must never do more than 7 _Id's for reasons that will be discussedlater.The types of opcodes are distinguished as follows:  A pause has no successor, and the IFUmust be restarted with PCF_B before the next IFUJump.  A regular's successor is the bytefollowing its last operand; a jump's successor is determined by adding a displacement tothe current PC as follows:If Length=1, then Sign.Packeda.N forms a six-bit signed displacement.  In otherwords, the jump is to any byte in the range PC408 to PC+378.If Length=2, then Packeda and N are unused; the jump displacement is a, if signis 0, or sign-extended a, if sign is 1.A jump with Length=3 is illegal.The IFU pipeline follows the instruction stream and fills up when it is five or six bytes aheadof the current opcode.  When a pause opcode is recognized, further memory referencesare not made.  When a jump opcode is recognized in J, the IFU discards any bytes in F, G,����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"sqî5pô�îFïfñî
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������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualInstruction Fetch Unit14 September 198167and H and refills these pipe levels with bytes along the jump path.The B_PCX' function reads PC (inverted) for the current opcode.  Note that PCF_B doesnot affect the value of PCX; B_PCX' continues to read the displacement of the currentopcode, which does not change until an IFUJump is done.An opcode that conditionally jumps can be encoded in IFUM with type either jump orregular.  If encoded as type jump, when the condition is false, the program must issuePCF_B to restart the IFU at the fall-through address.  Similarly, if regular, PCF_B must beissued to restart at the jump address.The Length argument delivered by _Id after other operands have been referenced is useful inconditional jump calculations.  Note that the fall-through address for a conditional jump isLength+PCX, so:T_(Id)(PCX')1;*Id = Length for type jumpPCF_T;Noop;IFUJump[0];restarts the IFU at the fall-through address for type jump.Following PCF_B, the IFU flushes its pipeline; it is illegal for either the instructioncontaining PCF_B or the one immediately after it to do an IFUJump, but any subsequentinstruction can issue an IFUJump; however, the processor will spin uselessly at the IFU"NotReady" trap until the fifth cycle after PCF_B (earliest) or later (longer opcodes, cachemisses, Mar traffic).ÿ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"sqî5pô�îFïfñî·ïbðCî·ï^¬ô�žô�Ÿð9î·ï\áô�¾	ô�¿ðKî·ï[ô�ð7î·ïW¥ô�Ðô�Ñqpð/qpî·ïUÚqpô�¾qp�ô�¿ð4î·ïTô�”ô�•ð5qpî·ïREô�ð&îyïOuô�Ìwuô�Íð1îyïM¹ô�ýðBô�þîyïLXô�î:ïJ#îwu	wî:ïHÃuî:ïGbî:ïF
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<ð.þ�¯������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualInstruction Fetch Unit14 September 198168Table 20:  IFU FF DecodesNameActionIFUResetHalt and clear the IFU pipeline and clear errors, testing features, and BrkPending(i.e., BrkIns); Reschedule condition and instruction set are not cleared.B_IFUMLH'Read the high-order IFUM word, InsSet, and IdCnt onto B (low-true) as follows:FieldB bitsIdCnt 0:2Count of _Id's since start of opcodeInsSet 3:4Instruction set numberPackeda   5Packed aIFaddr' 6:15Starting addressIFUMLH_BLoad the high-order IFUM word from B (t1 to t3), where the Packeda and IFaddrfields are in the same form as B_IFUMLH'.  Must have at least one interveninginstruction after a preceding BrkIns_ or InsSetorEvent_.IFUMRH_BLoad the low-order IFUM word from B (t1 to t3) in the format given below; musthave at least one intervening instruction after a preceding BrkIns_ orInsSetorEvent_:FieldB bitsSign   0IPar.0   1Even parity over N, MemB[1:2], and IFAD[0:1]IPar.1   2Even parity over IFAD[2:9]IPar.2   3Even parity on Packeda, Sign, Length', MemB.0,RBaseB', TPause, and TJumpLength' 4:5Instruction length (low true)RBaseB'   61-bit RBase initializationMemB 7:93-bit MemBase initializationTPause'  10Type pause (low true)TJump'  11Type jump (low true)N12:154-bit operandB_IFUMRH'Read IFUM fields in the same format as IFUMRH_B (inverted).PCF_BLoad PCF at t3, clear and restart the pipeline.B_PCX'Read PC for the currently executing opcode (inverted).BrkIns_BLoad BrkIns from B[0:7] at t3, and set BrkPending (ill-defined unless the IFU hasbeen reset).  BrkIns replaces the next opcode loaded into J; then BrkPending iscleared.  BrkIns also addresses IFUM on IFUMLH/RH_ and B_IFUMLH'/RH'.InsSetOrEvent_BIf B[0]=1, then B[6:7] are loaded into the InsSet register at t3; if B[0]=0, thenB[4:15] control event counters as discussed in the "Other IO and Event Counters"chapter.  A following PCF_B starts the IFU interpreting using the new instructionset.  Illegal except when the IFU is paused or reset or when PCF_ will be donebefore the next IFUJump.ÿ��������������î·ïfªpô�€î"sqî5pô�îFïfñî bïbsô�Xîxï^òvîùÈøÿúÿîxï\¾uù�ø�ú�îô�œùÈøÿúÿðCô�îï[]ô�ðIîxïY“îô�³ùÈøÿúÿô�´ð6î¡ïWÈwù�ø�ú�î$îô�î¡ïUýuî$îô�€î){ô�î¡ïTî$îô�€î){
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ô�î¡ï;«î$îô�€î){ô�î¡ï:Kî$îô�€î){ô�î¡ï8êî$îô�€î){ô�î¡ï7‰î$îô�€î){ô�î¡ï6(�î$îî){îxï4^ùÈøÿúÿîùÈøÿúÿð;îxï2“îùÈøÿúÿï2�ï2“ð!îxï0ÈîùÈøÿúÿð6îxï.þîô�žùÈøÿúÿï.q�ï.þô�Ÿð+îï-Vô�¥ð-ô�¦ð"îï+öô�éô�êð<îxï*+îô�°ùÈøÿúÿð&ô�±ï)ž�ï*+îï(„ô�ð!ô�Žð/îï'#ô�Ÿð*ô� ð'îï%Âô�Ÿð<ô� îï$aô�ÿ��������ò����·$>7mCͱ��������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualInstruction Fetch Unit14 September 198169Table 20:  IFU FF Decodes (continued)NameActionRescheduleCause a reschedule trap on the second or third "successful" IFUJump."Successful" means that an IFUJump is not trapped for some other reason suchas not-ready.  The second IFUJump will be trapped if it does not occur in theinstruction immediately after the first successful IFUJump; otherwise, the thirdsuccessful IFUJump will be trapped.  The trap instruction is executed as though itwere the first instruction of the rescheduled opcode, and _Id and IFUJump willwork as though that opcode were in progress.Also set the Reschedule branch condition (emulator only) to true.RescheduleNowRescheduleNow is guaranteed to trap the next successful IFUJump, so long as thenext IFUJump appears in the second cycle after RescheduleNow, or later.  TheReschedule branch condition is not affected.NoRescheduleTurn off the Reschedule trap and branch condition.IFUTest_BLoad the test-control register from B (load with 0 or do IFUReset when not testing)as follows:FieldB bitsTestFG 0:7Substituted for cache dataTestFGParity   8Substituted for cache parity bitTestFault   9Substituted for memory fault signalTestMemAck  10Substituted for memory MemAck signalTestMakeF_D  11Substituted for memory MakeF_D signalTestFH'  12enable FHCP and t1 when IFUTick executedTestSH'  13enable SHCP and t2 when IFUTick executedTestEn  14test enableIFUTickTick the IFU's clock once according to TestFH and TestSH in the IFUTest register.The IFUJump Entry VectorAn IFUJump[n], encoded in the JCN field of the instruction, sends control to an addresspartly determined by the IFU and partly by the IFUJump clause.  The four possible targetsof an IFUJump are called an "entry vector".An opcode leaves its results in one of several convenient forms agreed to by convention,then chooses an entry instruction in its successor with IFUJump[n], where n =0 to 3.Every opcode in the instruction set must have an entry vector of the same length.  Carefulchoice of forms may reduce execution time by one cycle for some opcodes withoutincreasing execution time for successor opcodes.A true branch condition (FF-encoded) with IFUJump prevents starting the next opcode.  Forexample, IFUJump[2,condition] sends control to the next opcode's entry 2, if condition isfalse, or entry 3, if condition is true.  However, no other IFU activities associated withstarting the new opcode take place when condition is true, so entry 3 is executed in thecontext of the opcode that did the IFUJump[2,condition]; however, the processor initializesRBase and MemBase as though the next opcode were starting, so this part of the state islost.  Thus, at a cost of one entry instruction in every opcode of an instruction set, it maybe possible to shorten the execution time of some opcodes using a conditional exit.An opcode with common and uncommon exit cases, for example, can exit withIFUJump[2,condition], where entry 2, the common case, starts the next opcode, while entry3 is reached for the uncommon case.  Since IFUJump loads Link with .+1, entry 3 caneither Return, to execute more code associated with the uncommon case, or it can doÿ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"sqî5pô�îFïfñî'ïbsô�Xð%îxï^òvîùÈøÿúÿîxï\¾u	îô*ùÈøÿúÿô+�wuîï[]ô�¡ð5ô�¢îïYüô�²ð1ô�³îïXœô�áðJô�âîïW;ô�ô�ð8îïUÚô�´ðNîïTyô�ð,îïR¯ðAîxïPäîô�ŠùÈøÿúÿð(wuð#îïOƒô�³ð=ô�´îïN#ô�ð,îxïLXîùÈøÿúÿð2îxïJîô�„ùÈøÿúÿô�…ð5îïI-ô�
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3ô�ÂðLô�Ãÿ��������z����·	ì=ð^³����������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualInstruction Fetch Unit14 September 198170something more explicit, if an appropriate convention is followed by all opcodes.The following example shows how an instruction set with four opcodes (Push, Add, Store,and JNZ) is implemented using a four-long entry vector.  The opcodes in this example dealwith the stack like Mesa opcodes do, and the first three entry conventions are, in fact, oneswhich might be used by the current Mesa emulator.%Entry0:Stk[StkP] holds top-of-stack (if anygarbage if stack empty), T holds garbage1:T and Stk[StkP-1] hold previous top of stack (garbage if stack empty),Stk[StkP] garbage, Md holds top-of-stack.2:T and Stk[StkP+1] hold top-of-stack,Stk[StkP] holds previous top of stack (garbage if stack empty).3:Results in same form as entry 2, but restart IFU at NewPC = (Id)(PCX')1Note that Stack&+1 references must not check for underflow when the stack may legitimately beempty.%*Push the memory location pointed to by N.Push:Fetch_Id, T_StackNoUFL&+1, IFUJump[1];Fetch_Id, T_StackNoUFL&+1_Md, IFUJump[1];Fetch_Id, StkP+2, IFUJump[1];T_(Id)(PCX')1, StkP+1, Return;*Replace the top two stack entries by their sum.Add:T_Stack&1, Branch[.+2];Stack_Md;T_Stack&1_T+(Stack&1), IFUJump[2];T_(Id)(PCX')1, StkP+1, Return;*Store the top-of-stack into the memory location pointed to by N and pop the stack.Store:Store_Id, DBuf_Stack&1, IFUJump[0];Stack_Md, Branch[Storex];Store_Id, DBuf_T, IFUJump[0];T_(Id)(PCX')1, StkP+1, Return;Storex:Store_Id, DBuf_Stack&2, IFUJump[2];*Pop the stack and branch if the top-of-stack was zero, else fall through*This opcode is of type jump.JNZ:Pd_Stack&1, Branch[ZTest];Pd_Md, StkP1, Branch[ZTest];Pd_T, Branch[ZTest];T_(Id)(PCX')1, StkP+1, Return;ZTest:T_Stack&1, IFUJump[2,ALU#0];*Return here when the jump doesn't take.T_Stack&1, PCF_T;IFUJump[2];Push thus requires 1 execution cycle; Store and Add take either 1 or 2 cycles dependingupon the entry point; JNZ takes 2 cycles when the jump takes or 9 cycles when the opcodefalls through (because the IFU isn't ready until the fifth cycle after PCF_B).Although every opcode in an instruction set must have an entry vector following the sameconventions, it is not necessary that the vector be four-long.  In the above example, asingle-entry scheme would probably use the entry 2 convention followed above.  In thatevent, Push, Add, Store, and JNZ would require 2, 1, 2, and 3 cycles (common case),ÿ������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"sqî5pô�îFïfñî·ïbðQî·ï^¬ô�šðPô�›î·ï\áô�‰ðGô�Šî·ï[ô�‚ð$ô�ƒð9î·ïYLô�ð1îyïUýuî­ïTyî(ðMî­ïRõî(ðFî(ïQqð)î­ïOíî(ð$î(ïNið?î­ïLåî(ðIîyïKaô�«ðMô�¬îyïIÝîyïHY�îyïE-ô�ð*îyïC©îûð&îûïB%ð)îûï@¡îûï?îyï;òð0îyï:nîûîûï8êîûï7fð$îûï5âîyï2¶ðSîyï12îûð$îûï/®îûï.*îûï,¦îyï+"îûð$îyï'÷ðIîyï&sîyï$îîûîûï#jîûï!æîûï bîyïÞîûîyïZð(îûïÖîûïR
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U<ð]¶��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualInstruction Fetch Unit14 September 198171respectively, compared to 1, 1 or 2, 1 or 2, and 2 or 3 cycles for the four-entry schemeabove.Since Mesa requires about 120 IFU entries for its 256 opcodes, the cost of the secondentry in the vector is between 0 and 120 locations, and 120 locations each for the third andfourth entries.  Since Mesa is implemented by about 1044 instructions using entry vectorsof length 1, a vector of length 2 scheme would require ~1100, length 3 ~1220, and length4 ~1340 instructions.  The implementor of an instruction set should decide when theadditional locations expended for larger entry vectors are no longer worth the additionalspeed.Although we originally hoped for as much as 8% faster inner loops and 4% overall speedimprovement, Gene McDaniel measured only 2% faster execution for Mesa (excluding diskwait) using a length 3 entry vector; microstore increased about 120 locations.  Investigationrevealed that increased traffic on Mar (by overlapped Fetch_ and _Md) was causing IFUnot ready to occur more often, offsetting the fact that fewer processor cycles were needed.Forwarding saved about .2 cycles/opcode.Note:  IFU trap locations discussed below must also be entry vectors that follow the sameconvention.Timing SummaryFrom the detailed timing discussion at the end of this chapter, the following generalizationsabout IFU timing can be drawn:Assuming no misses and no delays because the processor uses Mar, IFUJump willsuccessfully dispatch to the entry instruction of the next opcode on the fifth cycleafter PCF_B if the new opcode either is one byte long or is two bytes long andstarts at an even byte; otherwise it will succeed on the sixth cycle.A jump opcode causes a 3 cycle gap in the IFU pipe.  The effect of the gap wouldbe a 3 cycle delay if each opcode were executed in exactly one cycle.  However,the gap can overlap with extra cycles taken on the jump opcode itself or either ofthe two preceding opcodes.  As usual in timing considerations, a 3-byte opcodecounts as two normal opcodes.If a long stream of regular one-byte opcodes is being executed by the processor atthe fastest possible rate (one instruction/opcode), and if the IFU neither missesnor faults nor waits for the processor's use of Mar or the cache, then it will alwayshave the next opcode ready for IFUJump.  If the IFU waits one cycle for theprocessor to use Mar, it will shortly fill its pipe again, so scattered Mar referencesby the processor will not result in IFU NotReady.If a long stream of regular two-byte opcodes, each of which has an a but no N(This is the worst case.), is being executed by the processor at the fastest possiblerate (one instruction/opcode), and if the opcodes in the stream start at the evenbytes in words, and if the IFU neither misses nor faults, and if the processor neveruses Mar, then the IFU will give 25% NotReady.  Each cycle in which the processor������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"sqî5pô�îFïfñî·ïbô�­ð)ô�®ð/î·ï`Sî·ï\áô�½ðGô�¾
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@����·K=ðXÀ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualInstruction Fetch Unit14 September 198173Each trap vector is dispatched into by IFUJump exactly as though it were an opcode.B_PCX' reads the PC of the opcode that would have been executed if the trap had notoccurred and RBase, MemBase, and _Id stuff are set according to that opcode (in everycase except NotReadyall are undefined at a NotReady trap).The relative priority of traps is as follows:  IFUM parity error is highest, then NotReady,reschedule, cache data parity error, and map fault.The NotReady trap occurs whenever the IFU does not have both an opcode and itsassociated operands (a, b) ready for the processor.  Since PCX, MemBase, and RBase areinvalid, the trap microcode must wait for the IFU to become ready.  The following codesequence will work for all instruction sets that do not use a conditional exit:NotReady:FreezeBC, IFUJump[0];FreezeBC, IFUJump[1];FreezeBC, IFUJump[2];FreezeBC, IFUJump[3];For the sample instruction set given earlier, which uses entry 3 as a conditional exit, thefollowing sequence would be appropriate:NotReady:IFUJump[0];*Can't convert to IFUJump[2] because stack may be emptyT_Stack&1_Md, IFUJump[2];*Convert case 1 to case 2IFUJump[2];T_(Id)(PCX')1, StkP_StkP+1, Return;*Resume the opcode which didn't really exitIf the IFU detects bad parity on any read of IFUM, the IFUJump to the opcode affected bythis parity error will trap to the IFUM parity error trap location.The IFU will trap at the cache data parity error location, if it detected invalid parity on anybyte sent by the memory system.  PCX will always correctly point at the opcode that wouldhave been executed next had the trap not occurred; however, the opcode and operandspointed at by PCX are not necessarily the ones that suffered the parity error.  This occursbecause the pipe has continued ahead of PCX.  The most confusing case occurs when theopcode following PCX was a jump; in this case the opcode fetched by the jump may havecaused the parity error, in which case PCX+/ jump displacement is limited to the rangePCX4008 to PCX+3778.The IFU will hold an IFUJump in the cycle prior to a cache data parity error or IFUM parityerror trap.Note that IFUReset must be given after an IFUM or cache data parity error and beforerestarting the IFU.The Reschedule function is used by io tasks to request service by the emulator.  The IFUwill honor this trap request on the second IFUJump after it is executed, as discussed in alater section.  The RescheduleNow function is like the Reschedule function, but the IFUhonors it on the first IFUJump after it is executed, rather than the second (RescheduleNowwas intended for use when continuing an opcode which previously experienced a fault).ÿ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"sqî5pô�îFïfñî·ïbô�Îô�Ïð5î·ï`Sqô�²ð?ô�³î·ï^‰ô�¦ð.ô�§ð'î·ï\¾ô�ð:p�î·ïYLô�ºð@ô�»î·ïWô�ð3î·ïTô�åð2ô�æî·ïREô�Št�p�ô�‹�t�pð=î·ïPzô�¶qpô�·ð)î·ïN°ô�ðOîyïKîuîüïJîüïI-îüïGÌîüïFkî·ïCpô�©ð8ô�ªð#î·ïARô�ð(îyï>uîüï=/
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¢����·¾=ðYMB��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualInstruction Fetch Unit14 September 198174An IFU fetch may experience a map fault.  The memory system does not report IFU mapfaults to the fault task.  Instead, it signals the IFU that a map fault has occurred, and theIFU passes this indication through its pipeline.  Eventually, the IFUJump that would havesent control to the opcode affected by the map fault will instead transfer to the map faulttrap vector.Although IFU map faults are not reported to the fault task, the fault task must be careful to passover any pipe entries that were created by IFU map faults when it is woken for some other reason.Erroneous bytes fetched after a pause or jump opcode might cause map faults, but the IFU discardsthese before they reach the end of the pipeline, so the processor is never informed.  Consequently,erroneous references interfere with processor memory activity and delay the IFU's efforts to refill itspipe on a jump, but don't have any disastrous effect.An IFU fetch may experience single or double storage failures.  Unlike map faults, these arereported to the fault task just as on processor fetches.  The memory system pipeline willfinish loading the cache munch just as though the data were ok, and the cache entries willhave valid byte parity.  The IFU will continue running just as though no error had occurred.However, the fault task will be woken soon enough that it will run before the IFU's Fregister is loaded with a byte from the bad munch.  Hence,  the fault task will run beforethe emulator can possibly execute an IFUJump to the byte that suffered the error.For a recoverable error, the fault task can simply carry out some logging action and block;no harm will occur because the IFU will actually have gotten valid data, and the cache willcontain valid data.  For an irrecoverable error, the fault task must clear the bad cachemunch and use the RescheduleNow function to trap the next IFUJump to code for dealingwith the irrecoverable error.Erroneous bytes fetched after a pause or jump opcode might suffer irrecoverable errors.  The faulttask has no reasonable way to distinguish these from bytes really in the instruction stream, so it willcause a Reschedule trap anyway.RemarkAlthough independent trap vectors for each instruction set are probably inessential, performance should bebetter when the NotReady trap, which occurs frequently, is distinct for each instruction set.  This allows thevarious IFUJump exits to be transformed into the form most likely to be convenient for the next opcode.The other traps could have been implemented to use a common trap for all locations.  This would be moreeconomical for IFUM and FG parity error traps, if these simply result in an uncontinuable crash when runningsystem microcode.  However, different trap vectors for each instruction set are probably more convenient forReschedule and Map fault traps, which have to save the state of the emulator currently running.In any case, reserving locations for these traps costs at most 5 traps * 4 instruction sets * 4 entries/trap =1008 locations, and realistically is much less than this because many instruction sets will not need 4 entriesand there will probably be fewer than 4 instruction sets concurrently active.ÿ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"sqî5pô�îFïfñî·ïbô�¦ð-ô�§ð&î·ï`Sô�Ÿð2ô� ð+î·ï^‰ô�®ðAô�¯î·ï\¾ô�žô�ŸðHî·ïZóô�îyïX2uô�¤ô�¥ðGîyïVÑô�’ô�“ðLîyïT3ô�ˆwuwuô�‰ð'îyïRÒô�ô�‘ðRîyïQqô�”ð-ô�•ð:îyïPô�	wuð'î·ïLÂpô�€ð>ô�î·ïJ÷ô�¨ô�©ð:î·ïI-ô�ŠðGô�‹î·ïGbô�†ô�‡ðDî·ïCðô�ÑðUî·ïB%ô�Ÿð2ô� ð(î·ï@[ô�ðQî·ï<éô�ŽðAô�î·ï;ô�ð[î·ï9Tô�Àô�ÁðEî·ï7‰ô�“ô�”ðDî·ï5¾ô�îyï2Úuô�šwuwuð5îyï1Uô�‹ðDô�Œð#îyï/Ñô�î·ï,Éwî·ï*+uô�¶ðTô�·î·ï(Êô� ð:ô�¡ð4î·ï'iô�¾ô�¿ðOî·ï$Ëô�Ÿð+ô� ð<î·ï#jô�“ð_ô�”î·ï"
ô�žð;ô�Ÿð1î·ï ©ô�ð_î·ïô�—ðVô�˜î·ïªï�ïªô�¡ðjî·ïô�ðMÿ��������²����·ß<ðM,+������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualInstruction Fetch Unit14 September 198175IFU ResetThe processor can reset the IFU by executing the IFUReset function.  This clears all IFUerror conditions, prevents further IFU memory references, clears the BrkIns_ featurediscussed earlier and the test features discussed later, and generally puts the IFU in aclean and operable state.  The Reschedule feature is not affected by IFUReset.IFUReset should be executed after power-on to get the IFU shut off.  A single IFUReset willmake the IFU passive with respect to operating the rest of Dorado.  However, the IFU itselfmight not be operable until a second IFUReset is executed because of a pathologicalcondition (If BrkIns is loaded and Testing is true, then the first IFUReset will clear Testingbut not BrkIns; a second IFUReset is required to clear BrkIns in this case).If the IFU has any outstanding memory references pending at the time the first IFUReset isexecuted, those references will complete and disturb the top part of the IFU pipeline.  Asecond IFUReset must be issued after these references have all finished prior to reading orwriting IFUM.  If the second IFUReset is executed 36 or more cycles after the first, then itwill for sure completely reset the IFU.The worst case is when a miss has just started the storage pipeline with an IFU reference in thecache address section.  In this case the IFU reference does not enter the storage pipeline until the8th cycle and then takes 28 cycles to complete.IFUReset should be executed prior to using BrkIns_.  It should also be executed afterreading or writing IFUM (to reset the BrkPending condition that is still lurking).ReschedulingIo tasks request service from the emulator by first indicating a request in some way(Presently an RM location is used as a 16-bit table in which 1's indicate requests.), thenexecuting the Reschedule function, and finally blocking.  The IFU and the processor storethe reschedule condition in flipflops which remain set until the NoReschedule functionturns them off.The next IFUJump after Reschedule transfers to the entry vector for the opcode as usual;the reschedule trap address will drop into the IFAddr register at t2 of this instruction, andthe first IFUJump after that will dispatch into the reschedule trap vector.  This means thatsecond IFUJump will trap unless the second IFUJump occurs on the instructionimmediately after the first IFUJump, in which case the trap will not occur until the thirdIFUJump.  IFUJump's that experience a NotReady trap are not counted. The entry vector at the reschedule trap location is entered as though it were the nextopcode.  When Reschedule is used by io tasks to request the wakeup of another process,this fact is unimportant.  However, the other use of Reschedule is in continuation from map(and other) faults.  In this application, the reschedule trap will wind up restoring the IFUstate by executing an appropriate number of _Id's and eventually branching back to theinstruction that experienced the fault.  The continuation method is discussed later.Opcodes which might execute for a long time, such as block transfer and BitBlt, mustcheck for rescheduling explicitly, and the (emulator only) Reschedule branch conditionÿ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"sqî5pô�îFïfñî·ïbrî·ï^¬pô�¨ðXî·ï\áô�þðLô�ÿî·ï[ô�ÅðOô�Æî·ïYLô�ðNî·ïUÚô�†ô�‡ð@î·ïTô�Œô�ðSî·ïREô�Õð9ô�Öî·ïPzô�šô�›ð@î·ïN°ô�ðLî·ïK>ô�ô�ðHî·ïIsô�¬ðAô�­î·ïG¨ô�‡ðPô�ˆ
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ô�ÊðTî·ï·ô�Õð*ô�Öð,ÿ�������¤����·p<ð\›7������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualInstruction Fetch Unit14 September 198176makes this check easier.  If such opcodes did not check for rescheduling, then service tothe io device might be postponed for too long.The reschedule flipflops are not cleared by IFUReset, so the NoReschedule function mustbe executed as part of system reset.When the reschedule trap vector is entered, the IFU is in an undefined state except forPCX', and PCF_ is needed to restart the IFU at the continuation address.BreakpointsBrkIns_B implements debugging breakpoints straightforwardly.  The idea is that a one-byteopcode, BrkP, is used to transfer control to a debugger while saving emulator state neededto continue later, and another opcode, Continue, is used to continue from breakpoints (ForMesa, BrkP and Continue are special cases of Xfer.).BrkP may be substituted for any opcode in a program.  The debugger gets control whenBrkP is executed, saves state, and eventually can execute Continue to restore state fromvalues saved by BrkP.Continue first restores registers, then loads BrkIns with the opcode for which BrkP wassubstitued; then it uses PCF_B to restart the IFU at the breakpoint.  The IFU will then startrunning; the first opcode fetched will again be the BrkP opcode, but the contents of BrkInswill be substituted for the one fetched from memory, and the program will continuecorrectly.Without BrkIns_B the debugger would have to simulate the broken opcode beforecontinuing at the following opcode, which would be harder.  The example below shows acode sequence for the final part of Continue.Continue:. . .IFUReset;*Stop future IFU fetches and clear pipeT_41C;Cnt_T;IFUReset, Goto[.,Cnt#0&-1];*Reset after previous IFU fetches completeBrkIns_Opcode;*Load opcode which BrkP replacedPCF_BreakAddress;*Restart IFU at address of BrkPNoop;*No-op required after PCF_ before IFUJumpIFUJump[0];*Resume programNote: IFUReset is required before BrkIns_, even when an opcode of type Pause is inprogress.Reading and Writing IFUMIn addition to its function related to breakpoints, BrkIns_B is used to address IFUM whenreading or writing that memory.When IFUM is loaded, it is addressed by the instruction set InsSet[0:1] and BrkIns.  Thedata must remain on B for two cycles, so tasking must be disabled and the instruction����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"sqî5pô�îFïfñî·ïbô�šðYî·ï`Sô�ð.î·ï\áô� ð5ô�¡ð"î·ï[ô�ð$î·ïW¥ô�·ð6ô�¸ð!î·ïUÚô�ðHî·ïPÁr
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������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualInstruction Fetch Unit14 September 198177following the one with IFUMLH/RH_ must put the same data on B.  If this data comes fromRM or T, the register must not have been loaded in the cycle preceding the IFUMLH/RH_(because the bypass logic will change the B select from Pd or Md to RM or T, possiblyglitching data on B).  The following subroutines illustrate loading and reading back IFUM.WriteIFUM:IFUReset;*Stop future IFU fetches and clear the pipeT_41C;Cnt_T;IFUReset, GoTo[.,Cnt#0&1];*Reset after previously issued fetches completeInsSetOrEvent_RMaddr0;*Load 2 instruction set bits forming IFUM addressBrkIns_RMAddr1;*Load 8 opcode bits forming IFUM addressTaskingOff;*Ensure no B glitch below and let BrkIns_ settle for 1 cycleIFUMLH_RMdataHi;*Write high part of IFUMB_RMdataHi;*Keep data good a little longer (mustn't glitch)IFUMRH_RMdataLo;*Write low part of IFUMB_RMdataLo, TaskingOn;*Keep data good a little longerIFUReset, Return;*Clear BrkInsReadIFUM:IFUReset;*Stop future IFU fetches and clear the pipeT_41C;Cnt_T;IFUReset, GoTo[.,Cnt#0&1];*Reset after previously issued fetches completeBrkIns_RMaddr1;*Load 8 opcode bits forming IFUM addressInsSetOrEvent_RMaddr0;*Load 2 instruction set bits forming IFUM addressNoop;*Two instructions must elapse after loading BrkIns*one after loading InsSet (?Two noops after loading InsSet*might be better since this is a tight path?)RMdataHi_IFUMLH;*Read IFUM into RM.RMdataLo_IFUMRH;IFUReset, Return;*Clear BrkInsContinuing from Processor FaultsSaving and restoring the state of an interrupted program requires some cleverness not onlyfor the IFU, but also for the Control, Processor, and Memory sections.  The emulator mightfault for a data error, map fault, or stack overflow/underflow; for io tasks, stackoverflow/underflow is impossible and map faults will probably be illegal, so only data errorfaults are legitimate.  The discussion here will concentrate on map faults, though the sameapproach could be used for other fault conditions as well.The fault task must use as few instructions as possible so that io tasks won't be preemptedfor too long.  The minimum is to copy all pipe entries that contain memory faults into RM orStk buffers, preserve DBuf, and save the emulator's TPC; the fault task must itself deal withdata error faults by io tasks; it then restarts the emulator at a trap address.  The emulatormicroprogram then saves the rest of the emulator state and deduces the nature of thefault(s) using methods discussed in "Memory Section".The emulator fault microcode first saves ALU branch conditions and task-specific registers,then other information of interest.  The saved information is stored where the Mesa (orwhatever) program can get at it; then the trap microcode restarts Mesa at a trap procedurethat will service the map fault (probably swap in a page from the disk); eventually, state willbe restored and the opcode that faulted will be resumed at the instruction that faulted.ÿ������������������������������������������������������������������������������������������î·ïfªpô�€î"sqî5pô�îFïfñî·ïbô�…ð?ô�†î·ï`Sô�”ðFô�•î·ï^‰ô�±ð@ô�²î·ï\¾ô�¡ô�¢ð@îyïYüs	îüïXœî&•ô�ð+îüïW;îüïUÚîüïTyô�€î&•ô�ð)îüïSî&•ð1îüïQ¸î&•ð(îüïPW
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¤<ðZg\����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualInstruction Fetch Unit14 September 198178The IFU state may be saved via B_IFUMLH' and B_PCX'.  B_IFUMLH' reads the currentinstruction set and IdCnt from B[0:4]; B[5:15] are IFUM bits which are not of interest whensaving the state of the program, so the tricky code sequence given earlier for reading IFUMis not required.  B_PCX' reads the current PC.The 3-bit counter, IdCnt, keeps track of how many _Id's have been done; to avoidoverflowing this counter, no more than 7 _Id's should be done when executing anyopcode.  This is one (harmless) restriction on coding emulators.  The other is thatemulators never map fault on the instruction after a dispatch (BDispatch_B,BigBDispatch_B, or Multiply); this can be assured by doing _Md prior to or concurrent withany dispatch.Sample microcode for saving emulator state is as follows:%Must first save the volatile branch conditions; Overflow and Carry won't change unless an arithmeticALU operation is executed, so saving them can be deferred.  T, the first item saved, is written into theRM region reserved for Save using the change-RBase-for-write FF decode.%Save:FreezeBC, DblGoTo[ALUls,ALUge,ALU<0];ALUls:SavedT_T;T_0C, GoTo[SaveBC];ALUge:SavedT_T, DblGoTo[ALUgr,ALUeq,ALU#0];ALUgr:T_1C, GoTo[SaveBC];ALUeq:T_2C;*Have a code, 0, 1, or 2, in T indicating the state of the ALU<0 and ALU=0 branch conditions.SaveBC:SavedALULEZ_T;*Save the branch condition codeT_Pointers;*T_MemBase, MemBX, and RBaseT_T Or (100000C);*Make negativeRBase_RBase[SaveRMRegion];*Now choose two numbers such that their sum produces the correct ALUcry and Overflow branch*conditions.SavedPointers_T, MemBase_SaveBaseReg, DblGoto[Cry,NoCry,Carry];Cry:DblGoTo[CryOvf,CryNoOvf,Overflow];NoCry:DblGoTo[NoCryOvf,NoCryNoOvf,Overflow];CryOvf:SaveA1_100000C;SaveA2_100000C, GoTo[SaveRest];*Numbers such that SaveA1+SaveA2 produces*Overflow and Carry resultNoCryNoOvf:SaveA2_0C, GoTo[.+2];CryNoOvf:SaveA2_1C;SaveA1_177777C, GoTo[SaveRest];NoCryOvf:SaveA1_77777C;SaveA2_77777C, GoTo[SaveRest];SaveRest:SavedPCX_Not(PCX');T_Not(IFUMLH');*Read IdCnt and InsSet in IFUMLH[0:4]SavedIdCnt_LdF[T,0,2];T_T and (14000C);T_RSh[T,2];SavedInsSet_T+(100000C);*Set up word for InsSetOrEvent_ below. . .*Code to save rest of state (all easy)Sample microcode for continuing is given below:Resume:. . .*Restore all processor registers except T, Cnt, RBase,*and MemBase.InsSetOrEvent_SavedInsSet;*Restore the IFU instruction set number.PCF_SavedPCX;*Restart IFU at address of the opcode that faultedWakeUp[ContTask];*Wakeup the special task used for continuation.Noop;*No-op required so that the instruction after the IFUJumpÿ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"sqî5pô�îFïfñî·ïbô�¨ô�©ðJî·ï`Sô�“ð<ô�”î·ï^‰ô�„ô�…ðDî·ï\¾ô�ð.î·ïYLô�óð(ô�ôð(î·ïWô�íðPî·ïU·ô�õô�öðKî·ïSìqôŠô‹ð$p
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;<ðZÐs������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualInstruction Fetch Unit14 September 198182If Length < 3, then the H/J level is now free to work on the next opcode.  If Length = 1and the next opcode happens to be in H, then H will drop into J at the same time (t2);otherwise, J will be loaded from the next opcode in F/G when it is ready.When the processor does an IFUJump[n], level M presents information needed by the nextopcode as follows:IFaddr is TNIA[4:13] for the IFUJump;MemBase is set to 0.MemBX.MemB[1:2] or 348+MemB[1:2];RBase is set to 0 or 1;N, Sign, Length, Packeda, and a are loaded into the X level;b is loaded into the M level if Length = 3.Referencing IFU operands with A_Id, TisId, or RisId affects the IFU in two ways: it causesthe IFU to advance to the next item of Id, and for a 3 byte instruction when a is taken(a[4:7] when Packeda = 1) it causes b to drop from M to X, freeing M for the nextinstruction.IFetch_ also uses Id, as discussed in memory section, but does not advance the IFU to thenext item of Id.For a one or two-byte opcode, it is permissible for the processor to do an IFUJump beforereferencing any operands with _Id; this will advance normally to the next opcode.However, for a three-byte opcode the processor must reference all of a, so that b dropsinto X, before doing an IFUJump.When a pause or jump is recognized, the IFU may already have filled the F and G levelserroneously (i.e., 4 bytes ahead).  These levels are flushed and refilled along the jump path.Timing DetailsThis section discusses timing details of the IFU pipeline assuming that all IFU references hitin the cache and are never deferred for processor references.First case:  Restart IFU at even bytet0:An instruction with PCF_FOO is started, where FOO is even.t2:F, G, H, J, and M levels are made invalid.t3:Reference the word containing FOO.t5:Reference word containing FOO+2.t7:Load F with data from the FOO reference; reference the word containing FOO+4.t8:Load the first byte from F into J; load G from F; F becomes invalid; start reading the IFUMentry for J.t9:Load the putative operand byte from G into H; G becomes invalid; load F from the FOO+2reference.t10:Distinguish 5 cases below.FOO is a one-byte regular opcodeÿ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"sqî5pô�îFïfñî·ïbô�žqpð@ô�Ÿî·ï`Sô�´ð.ô�µð%ï_Æs�ï`Spî·ï^‰ô�ðIî·ï[ô�‘ð&ô�’ð0î·ïYLô�î:ïUÚð%î:ïTð)ïS‚s�ïTp
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ô�–ðMî›ïô�îxïî›ô�—ðVî›ïµ	îxïÇî›ô�îxïxq�������ž����·1=ðYÚ ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualInstruction Fetch Unit14 September 198183t10:Load M from IFUM; IFUJump will now succeed; load J from H (FOO+1); load G from F(FOO+2 and FOO+3); F and H become invalid; start reading the IFUM entry for J.t11:Load H from G (FOO+2); load F from FOO+4 reference.t12: (The FOO+1 opcode would pop into M if IFUJump were done at t10.)IFU is quiescent; F has two useful bytes, G one byte, J/H has two bytes; M level is readyand waiting for IFUJump.FOO is a two-byte regular opcodet10:Load M from IFUM and M[a] from H; IFUJump will now succeed; load J from F (FOO+2);load G from F (garbage and FOO+3); F and H become invalid; start reading the IFUM entryfor J.t11:Load H from G (FOO+3); G becomes invalid; load F from FOO+4 reference; reference theword containing FOO+6.t12:Load G from F; F becomes invalid.t15:Load F from the FOO+6 reference; now quiescent.FOO is a three-byte regular opcodet10:Load M from IFUM and M[a] from H; IFUJump will now succeed; load G from F (FOO+2and FOO+3); H and F become invalid; J goes to special state (b in H).t11:Load H from G (FOO+2 = b); load F from the FOO+4 reference; now quiescent.t12: (The FOO+2 byte would pop from H into M[b] if IFUJump were done at t10.)FOO is a one-byte jump opcodet10:Load M from IFUM; IFUJump will now succeed; J, H, G, and F become invalid.t11:Discard the FOO+4 reference; reference the first word along the jump path.t13:Reference the second word along the jump path.t15:Load F from the first word along the jump path.t16:Load J from F, etc.FOO is a two-byte jump opcodet10:Load M from IFUM and M[a] from H; IFUJump will now succeed; G and F become invalid; Jand H are in a special jump state, computing the jump address.t11:Discard the FOO+4 reference; reference the first word along the jump path.t12:J and H become invalid.t13:Reference the second word along the jump path.t15:Load F from the first word along the jump path, etc.Second case:  Restart IFU at odd bytet0:An instruction with PCF_FOO is started, where FOO is odd.t2:F, G, H, J, and M levels are invalid; IFUJump will trap at NotReady.t3:Reference the word containing FOO.t5:Reference word containing FOO+1.t7:Load F with data from the FOO reference; reference the word containing FOO+3.t8:Load the second byte from F into J; F becomes invalid; start reading the IFUM entry for J.t9:Load F from the FOO+1 reference.t10:Distinguish 3 cases below (and the one and two-byte jump cases which are not repeatedbelow).ÿ����������������������������������������������������������������������������������������������������î·ïfªpô�€î"sqî5pô�îFïfñîxïbAsî›ô�¶ðIô�·î›ï`àô�éð0ô�êîxï^òî›ô�ð3îxï]î›ðBî›ï[¤ô�ŸðSô� î›ïZCô�îxïVôqîxïTysî›ô�žu�sð*ô�Ÿî›ïRõô�Žð:ô�î›ïQ”ô�îxïO§î›ô�›ðPô�œî›ïNFô�îxïLXî›ð!îxïJjî›ð/îxïGqð"îxïD sî›ô�¤ô�¥u�sð8î›ïBùô�ð=u�sîxï@Åî›ô�íô�î	u�sð2îxï>î›ô�öð*u�s�ô�÷îxï;qô�îxï8Æsî›ðJîxï6Ùî›ðJîxï4ëî›ð.îxï2ýî›ð/îxï1î›îxï-Àqîxï+Esî›ô�‰u�sð2ô�Š
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ÿ�������	œ����·ô7m[A����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualInstruction Fetch Unit14 September 198184FOO is a one-byte opcodet10:Load M from IFUM; IFUJump will now succeed; load J from F (FOO+1); load G from F(garbage and FOO+2); F becomes invalid; start reading the IFUM entry for J.t11:Load H from G (FOO+2); G becomes invalid; load F with the FOO+3 reference; referencethe word containing FOO+5.t12:Load G from F; F becomes invalid.t15:Load F from the FOO+5 reference; now quiescent.FOO is a two-byte opcodet10:Load G from F (FOO+1 and FOO+2); F becomes invalid.t11:Load H from G (FOO+1); load F with the FOO+3 reference.t12:Load M from IFUM and M[a] from H; IFUJump will now succeed; load J from G (FOO+2);load G from F; F and H become invalid; start reading the IFUM entry for J.t13:Reference the word containing FOO+5; load H from G (FOO+3).t17:Load F with data from the FOO+5 reference; now quiescent.FOO is a three-byte opcodet10:Load G from F (FOO+1 and FOO+2); F becomes invalid.t11:Load H from G (FOO+1); load F from the FOO+3 reference.t12:Load M from IFUM and M[a] from H; IFUJump will now succeed; H becomes invalid; J is ina special state (b in H).t13:Load H from G (FOO+2); load G from F (FOO+3 and FOO+4); F becomes invalid; referencethe word containing FOO+5.t17:Load F from the FOO+5 reference; now quiescent.������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"sqî5pô�îFïfñîxïbqîxï_Æsî›ô�¸ð9ô�¹î›ï^eô�ðKîxï\wî›ô�Ÿð)ô� ð+î›ï[ô�îxïY)î›ð!îxïW;î›ð/îxïSìqîxïQ”sî›ð3îxïO§î›ð7îxïM•î›ô�š
ô�›u�sð:î›ïLô�ðJîxïJ#î›ð;îxïH6î›ð9îxïDçqîxïBsî›ð3îxï@¡î›ð7îxï>î›ô�Žu�sð%ô�î›ï<éô�u�sîxï:Øî›ô�ð7ô�‚î›ï9wô�îxï7‰î›ð/ÿ�������
����·7f7m0¥�°����������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualSlow IO14 September 198185Slow IOThe slow io facility allows data transfers between the processor and any of up to 256independently addressed io registers.  It is intended that the slow io facility will be used toload and read control information associated with high speed io devices (> 20 x 106bits/sec), which will then use the fast io system for their data transfers.  Low speed devices(< 20  x 106 bits/sec) will use the slow io bus for all phases of their operation.  Very slowor polled devices may be driven directly from an emulator.Device controllers for Dorado interact with the processor by exchanging data over a 16-bitbidirectional bus IOB ("Input/Output Bus").  There may be a total of up to 256 io registersin all controllers connected to a single system.  The unique 8-bit device numbers assignedto particular devices or uses that appear in every system are discussed in subsequentchapters and summarized in the table below.Table 21:  IO Register AddressesNumberNameComment10DiskControlDisk control register11DiskMuffDisk muffler control12DiskDataDisk FIFO data13DiskRamDisk format RAM14DiskTagDisk tag register15EDataEthernet input or output data16EControlEthernet control and status360PixelClockDDC pixel clock361MixerDDC mixer362CMapDDC CMap363DWTFlag* (DispM analog of DWTFlag)364DHTFlag* (DispM analog of DHTFlag)365BMapDDC BMap366NLCB* (DispM analog of NLCB)367Statics* (DispM analog of Statics)370StatusDDC muffler and OIS data372MiniMixerDDC MiniMixer373DWTFlagDDC word task control374DHTFlagDDC horizontal task control375HRamDDC horizontal waveform control376NLCBDDC next line control block377StaticsDDC debugging controlÿ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î&•qî4]pô�îGïfñî·ïa×rî·ï^epô�Ë
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îÚï;ˆîî"sîÚï9½îî"sîÚï7óîî"sîÚï6(îî"sîÚï4^î	î"sîÚï2“îî"sîÚï0Èîî"sîÚï.þî�î"sð"îÚï-3î�î"sð"îÚï+iîî"sîÚï)žî�î"sîÚï'Óî�î"sð"îÚï&	îî"sîÚï$>îî"sîÚï"sîî"sîÚï ©îî"sîÚïÞîî"sîÚïîî"sîÚïIîî"s�����������·<ðM	F������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualSlow IO14 September 198186Input/Output FunctionsIn most cases, a task will need to do many sequential io operations to the same io register.The 8-bit task-specific register TIOA holds the device address being referenced by eachtask.TIOA is loaded at t2 from B[0:7] by the TIOA_B function, or TIOA[5:7] can be loaded fromFF[5:7] while preserving TIOA[0:4] by the TIOA_small constant function.  Pd_Input,Pd_InputNoPE, or Output_B functions can be issued in the instruction immediatelyfollowing the one that loads TIOA.Most input registers include odd byte parity with IOB data.  The Pd_Input function readsIOB data and checks parity.  The Pd_InputNoPE function reads IOB data without a paritycheck; this is useful when determining whether a device exists (IOB has bad parity if anonexistent register is selected).  The enabling and timing of parity error halts is discussedin the "Errors" chapter.The Output_B function sends 16 bits of data with parity to the io register selected by TIOA.Many controllers check the parity and report parity errors as part of their status.The tasks reserved for standard peripherals are given in the table below.Table 22:  Task AssignmentsNumberNameComment0EMUThe emulator1CONSpecial task for restarting emulator after faults2JNKJunk task (awakened every 32 ms)3DHTDisplay horizontal task4AHTDispM terminal interface horizontal task6EOTEthernet output task7EITEthernet input task118AWTDispM terminal interface word task128SIMTask simulator138DWTDisplay word task148DSKDisk io178FLTThe fault taskIO OpcodesThe Mesa instruction set has two opcodes for dealing with the slow io system:INPUT:TIOA_a;Stkp_Stkp+1;Stack_Input, IFUJump[0];OUTPUT:��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î&•qî4]pô�îGïfñî·ïbtî·ï^¬pô�‡
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ë=ðZ (������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualSlow IO14 September 198187TIOA_a;Output_Stack&1, IFUJump[0];These opcodes allow a Mesa program to have full access to the io system.  The intent isthat these instructions will be used to set up registers in firmware-driven devices, and do allthe service required by polled slow devices.    In many cases, the use of an INPUT orOUTPUT instruction is not sensible (doing io to a device normally driven by firmware, forexample), but the capability should prove useful for testing and diagnostics.Wakeup, Block, and NextThe "Control Section" chapter discussed task switching, and the material which follows is anelaboration of that discussion.Note that a task for which a wakeup request is issued at t0 cannot commence its nextinstruction until t4; i.e., at least two cycles elapse after a wakeup before the next instructionis executed.  The task then runs until it does a Block; in order to avoid an erroneous extrawakeup, the task must lower its wakeup request at least one cycle before issuing Block.Consequently, an io device may turn off its wakeup request according to one of threestrategies:The first is to turn off the request when Next becomes equal to its task number; inthis case the wakeup request is lowered at t0 of the first instruction executed for thetask, and it must not block until the second instruction to prevent an erroneoussecond wakeup.  The special situation in which Next is invalid ("Next Lies") must bedealt with by device controllers that do this.  This situation occurs as follows:Suppose that a task blocks with the following instruction:Branch[Loop], Fetch_Address, Block;*Fetch next wordThis generates Switch and the task in Bnt is broadcast over the Next bus.If the Fetch_ causes hold and Bnt < Ctask, then no task switch will occur.However, the Next bus is incorrectly broadcasting Bnt.  Since hold occursafter t1, there is insufficient time to change the Next bus back to Ctask inthis case.Consequently, controllers using Next detect "Next Lies" and disable anyactions that would otherwise be performed when it occurs.A pathological lockout problem should be noted:  Since task T's wakeuprequest was lowered at t2 when Next=T was noted at t0, the Next Liescondition will (correctly) result in repeating the held instruction at t2;however, some task of lower priority than T may erroneously execute at t4.This might be a problem if some high demand task of higher priority iscoded so that it always creates Next Lies (say, by doing Block andimmediate _Md in the instruction after a Fetch_).Another consequence of "Next Lies" is that IOAtten may be incorrect when����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î&•qî4]pô�îGïfñî¬ïbsu�p�î¬ï`Ssî·ï\ápô�Ÿô� ðBî·ï[ô�ô�‚ðCî·ïYLô�»ðUî·ïWô�¦ð,ô�§ð-î·ïU·ô�ðMî·ïQqtî·ïMÿpô�ð\î·ïL5ô�î·ïHÃô�Îð5ô�ÏïH6s�ïHÃpî·ïFøô�“ïFks�ïFøpô�”ð2î·ïE-ô�šð7ô�›ð%î·ïCcô�ÀqðNp�î·ï?ñô�ÝðKô�Þî·ï>&
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ã=ç](H��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualSlow IO14 September 198188"Next Lies" is occurring.  Consequently, branch on IOAtten is illegal duringan instruction that blocks and might cause hold.The second strategy monitors TIOA becoming equal to a particular device value.  Inthis case the wakeup request is lowered at t0 of the second instruction following awakeup, and the task must not block until the third instruction.  The disk controllerhas used this strategy, which has the draw back that if TIOA inadvertently assumesthe particular device value for any other task, the hardware will malfunction.  Aconsequence of any device using this strategy is that all tasks must be careful toinitialize TIOA properly when first awakened.The third strategy waits for some Output_B or Pd_Input operation to reset thewakeup condition.  This would reset the condition at t3 or t5 of the Output_Binstruction, and the wakeup would be lowered at t4 or t6; in this case the task mustnot block until the third or fourth instruction after the Output_B or Pd_Input toavoid an erroneous wakeup.  The exact requirement depends upon the iocontrollerthe disk controller, for example, lowers its wakeup request at t4 and canblock in the third instruction after Output_B, while the display controller horizontaltask lowers its wakeup request at t5 and can block in the fourth instruction.If loops naturally run for at least three instructions, use of TIOA is more economical than useof Next because TIOA decoding is mandatory in any case, while Next is needed only forshort loop devices, devices that use the fast io system, and devices that drive the SubTasklines.SubTasksWhen an io device sees Next becoming equal to its task, it can (optionally) present a two-bitSubTask number as well.The processor, control, and memory sections clock SubTask into flipflops at t0.  Theprocessor OR's SubTask [0:1] into RBase[2:3] and into MemBase[2:3].  This allows the samefirmware to control several identical io devices concurrentlyeach device, represented by aSubTask, gets its own RM region with 16 RM locations and its own pair of MemBaseregisters; if only SubTask[0] is driven, then two RM regions and four MemBase registers areavailable to each subtask.  Note that the 16 change-RBase-for-write functions do not ORSubTask into the changed address, so they cannot be used; also, if RBase is read by theprocessor the value read out has SubTask OR'ed in.  However, the 16 change-RSTK-for-write functions do work.Note also that when the debugging processor (Baseboard microcomputer or Alto runningMidas) asserts the Freeze signal, the affect of the subtask on RBase[2:3] is disabled, butsubtask continues to affect MemBase[2:3].In the memory section, the task and SubTask that issued an IOFetch_ is bussed to fastoutput devices with data from storage.  The device receiving the data identifies itself bymeans of this information.  IOStore_'s are handled similarly.A task presenting SubTask signals generally must Block at the same location each iteration������������������������������������������������������������������î·ïfªpô�€î&•qî4]pô�îGïfñî;ïbô�Ž
ô�ð>î;ï`Sô�ð0îyï\áô�ð5ô�Žîyï[ô�Ÿð,ïZŠs�ï[pô� îyïYLô�—qô�˜ð"pîyïWô�–ô�—ð5îyïU·ô�ÌðQîyïSìô�¯qpð$qpô�°îyïR"ô�ð-îyïN°ô�Ùð6ô�ÚîyïLåô�Ýô�Þð$ïLXs�ïLåpïLXs�ïLåpîyïKô�‘ô�’ð!ïJs�ïKpïJs�ïKpqîyïIPô�ÌðNpîyïG…ô,ð>ô-îyïE»ô�‘ð3ô�’ïE.s�ïE»pîyïCðô�¤ðKô�¥
îyïB%ô�úð#ïA˜s�ïB%pô�ûî·ï>×ô�ƒð#ô�„ð<î·ï=ô�»ð1ô�¼ð$î·ï;Aô�žð[î·ï9wî·ï4^tî·ï0ìpô�‹ð>ô�Œî·ï/!ô�î·ï+¯ô�óô�ôð2ï+"s�ï+¯pî·ï)äô�‰ð5ô�Šð$î·ï(ô�—ð0ô�˜ð+î·ï&Oô�âð@ô�ãî·ï$…ô�‘ô�’ð;î·ï"ºô�½ô�¾ðEqpî·ï ïô�¬ðKô�­î·ï%ô�»ð2ô�¼ð"î·ïZô�qpî·ïèô�¿ð+ô�Àð)î·ïô�»qpð"ô�¼î·ïSô�ð)î·ïáô�Ãð7ô�Äî·ïô�Æð<ô�Çî·ïLô�ð=î·ïÚô�˜ð,qô�™ð*ÿ�������¾����·“=ç\xi��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualSlow IO14 September 198189since there is only a single TPC value for all of the SubTasks.  Hence, the full generality oftasking is unavailablethe microcode for these tasks must be coded as though the wakeupmechanism were a priority interrupt.Illegal Things IO Tasks Must Not Do(1) It is illegal to Block in an instruction that does B_ExternalSource, where ExternalSourceis anything except one of the sources on the IFU board.  This restriction is needed so thatthe emulator will be able to do arithmetic on B_PCX'.(2) The IOAtten branch condition is illegal in an instruction that Blocks and might be held,because NextLies might occur, as discussed above.(3) A task may not Block on an instruction that might be held, if its wakeup request might bedropped at t0 of the instruction.  If this occurred, the instruction might inadvertently berepeated before the Block took effect.(4) It is illegal to Block with TaskingOff in force.(5) A task must not Block until one cycle after its wakeup request is turned off.(6)It is illegal to issue Wakeup[n] if task n might run in the next cycle.  Wakeup[n] must beexecuted with TaskingOff in such circumstances.ÿ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î&•qî4]pô�îGïfñî·ïbô�—ô�˜ðKî·ï`Sô�—ðWî·ï^‰ô�ð$î·ïYotð#î·ïUýpô�–ð1ô�—ð,î·ïT3ô�ð(ô�žð3î·ïRhô�ð5î·ïNöô�¤ð+ô�¥ð1î·ïM,ô�ð1î·ïIºô�†ðTô�‡î·ïGïô�ÐïGbs�ïGïpð+ô�Ñð#î·ïF$ô�ð&î·ïB²ð4î·ï?AðQî·ï;Ïî2ô�ð0ô�ð*î·ï:ô�ð/�������–����·9½=ç.N�ˆ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualFast IO14 September 198190Fast IO The fast input/output system provides high-bandwidth data transfers between storage andio devices.  Transfers occur in units of one munch (= 16 words); the addresses of the 16words must be i, i+1, ..., i+15, where i mod 16 = 0.   One word is transferred every clock,for a peak bandwidth of 533 x 106 bits/second.  A fast device is also interfaced to the slowio system, from which it receives its control information, since there is no way for thedevice to communicate directly with the processor using the fast io system.A single transaction of the fast io system transfers exactly one munch.  Successivetransactions are completely independent of each other, whether they involve the same ordifferent devices, as far as the io system is concerned.  The only relationship betweentransactions is that storage references of two transactions occur in the order that they wereissued.Each fast io transaction is initiated by an IOFetch_ or IOStore_ reference coded in ASEL.Once this instruction has been executed, the transaction proceeds without furtherinteraction with the processor (except for fault reporting).  The transaction itself involves astorage reference, and transport of the data between main storage and the device.  In thecase of a fetch, transport happens at the end of the reference, after the munch has beenerror-corrected.  For a store, transport happens at the beginning of the reference, inparallel with mapping the VA and starting the storage chips.  As a result of this difference,the transport for a fetch may overlap or even follow the transport for a following store.TransportThe device is only concerned with the transport of the data, and has no way of knowingexactly how or when the storage reference take place.  The transport happens in 16clocks, each transporting a single word using the Fin bus (IOFetch_'es) or Fout bus(IOStore_'s).  The two busses are independent, and transport can be happening on both ofthem simultaneously.The two busses have much in common.  Both have Task and Subtask lines, on which thememory presents the task and subtask involved in the transport about to begin and a Nextsignal used for synchronization.  The Fout bus has a Fault line which is high at the time thelast word of the transaction is delivered if there was a memory fault during the fetch (otherthan a corrected single error).Both data busses are 18 bits wide: 16 data bits, numbered 0..15, and two byte partiy bits,numbered 16 (bits 0..7) and 17 (bits 8..15).  The parity bits have the same timing as thedata bits.  A device is invited to check the parity of data on Fin, and is required to generateparity for data on Fout.Wakeups and MicrocodeThe normal interface between a device and its task involves one wakeup for each munchtransferred.  The device must keep track of the number of wakeups it has issued, sincedata may not arrive from storage for several microseconds, but there is no way to stop the��������������������������������������������������������������������������������������������î·ïfªpô�€î&•qî5
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ô�ðRî·ï"Pô�ŒðEô�î·ï †ô�î·ïô�ð0ô�žð*î·ïIô�®ðUô�¯î·ï~ô�‚ðCô�ƒî·ï´ô�î·ï›tî·ï)pô�¡ðOô�¢î·ï
^ô�²ô�³ðIî·ï“ô�ŽðGô��������¤����·L=ð\¿7������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualFast IO14 September 198191data from arriving once the task has started the memory reference.Typical microcode for a fast output device is given in the "Display Controller" chapter.LatencySuppose that the highest priority fast io task issues its wakeup request at t0; then it willexecute its first instruction at t4.  Some other task can cache fault with clean victim in thecycle starting at t0, and another task can cache fault with dirty victim in the cycle startingat t2.  The first reference gives rise to one storage reference and the second to two storagereferences; each of these three storage references takes 8 cycles to handle, so the fast ioreference will not begin for about 24 cycles.  From the time it begins until the last dataword is delivered to the device is 23.5 cycles, for a total of 47.5 cycles, to which 2 cyclesmust be added for the time between the wakeup and the first executed instruction.  In thissituation, the transport is not finished until 49.5 cycles after the wakeup.  Lower prioritytasks are delayed by an additional 8 cycles for each reference which might be made by ahigher priority task.The above is one possible worst case.  Another is the execution time of higher prioritytasks; a wakeup might be delayed by sum of the longest normal execution of the fault taskand of other higher priority tasks.  The fault task execution time is presently unknown.A store reference is slightly better, since its transport is finished 8 cycles after thereference starts, for a total latency of 40 cycles.All these numbers assume that a reference can be started every 8 cycles.  Ifsuccessive references are to 4k modules, however, they can happen only every 13cycles, and the calculations must be adjusted accordingly.  Also, data is returnedfrom a 4k module 3.5 cycles later.������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î&•qî5
pô�îFïfñî·ïbðBî·ï^¬ô�Ãð-ô�Äð+î·ïY“tî·ïV!pô�±ðMïU”s�ïV!pô�²î·ïTVô�”ð"ïSÉs�ïTVpô�•ð9î·ïR‹ô�™ïQþs�ïR‹pô�šðEî·ïPÁô�ïP4s�ïPÁpô�‚ðRî·ïNöô�”ô�•ðHî·ïM,ô�²ð-ô�³ð-î·ïKaô�˜ô�™ðEî·ïI–ô�ð1ô�‘ð)î·ïGÌô�¶ðDô�·î·ïFô�šðWî·ïD7ô�î·ï@Åô�½ð?ô�¾î·ï>úô�Žð6ô�ð#î·ï=/ô�Äð(ô�Åð0î·ï9½ô�÷ð/ô�øð)î·ï7óô�ð3îyï5ô�Ôô�Õð-îyï3gô�ô�Žð3îyï1¿ô�žðAô�Ÿîyï0ô�ð"�����������·/Ñ<ð8:�Ñ����������������������������������������������������������������������������������������������Dorado Hardware ManualDisk Controller  14 September 198192Disk ControllerThis chapter describes the Dorado disk controller, which uses the Slow IO system tocontrol up to four Century Data Trident disk drives.  Either the 80x106-byte T-80 or the300x106-byte T-300 drives can be used.  An extension of the controller onto a second logicboard (not designed) would allow control of up to 31 disk drives; alternatively, duplicatingthe present controller (with different TIOA, task, and muffler assignments) would allowindependent control of four additional drives.Keep Figure 13 in view while reading this chapter.The disk controller uses task 148 and the first five values of the TIOA addresses in block108 - 178 (The Ethernet controller, on the same logic board, uses two of the other three.).Either the task or TIOA block can be modified by changing a SIP component on the logicboard.  TIOA assignments are as follows:108DiskControlOutput_B to control register118DiskMuffOutput_B muffler control and Pd_Input to read muffler128DiskDataPd_Input to read FIFO or Output_B to write FIFO data138DiskRamOutput_B to format RAM148DiskTagOutput_B to tag registerNote: other tasks must not select these TIOA addresses at any time; doing so may cause the diskcontroller to malfunction.The controller is interfaced to the disk drives by a daisy chain cable bussed to all drivesand by an independent radial cable to each drive.  The radial cables contain the followingsignals:data line (bidirectional, differentially driven)data clock (from drive, differentially driven)subsector/index line (from drive)selected line (from drive)select line (from controller)sequence line (from controller, controlled by the baseboard for drive 0 and groundedfor other drives)two VCC lines and scope trigger (from controller)The daisy-chain cable contains the following signals:16 control "tags" driven by the controller and received by the selected drive9 error and status signals from the drive as follows:CylOffset'ReadOnly'NoTerminatorHeadOvfl'SeekInc'DevCheck'NotOnLineNotReadyIndex'������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�Xî"
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î îyïC©ïCs�îûïC©pî ð5îyïAßïARs�îûïAßpî ð4îyï@ï?‡s�îûï@pî îyï>Jï=½s�îûï>Jpî îxï;«tsô�Çtð$sô�Èîxï:Kô�î·ï6üpô�§ð5qpô�¨î·ï51ô�•qpð.ô�–	î·ï3gîyï0_ô�ð0îyï.”ð.îyï,Éð!îyï*ÿîyï)4îyï'iô�¤ðGô�¥î­ï%Ÿô�îyï#Ôð1î·ï Ìð5îyïÄðMîyïùð5î­ï/	î­ïdî­ïšî­ïÏî­ïî­ï:î­ïoî­ï
¥î­ïÚ�����������·“=è\x6��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisk Controller  14 September 198193The controller or's the NoTerminator error (which means that the daisy-chain cable isn'tterminated) into the NotOnLine error; the other error indications are discussed later.Disk AddressingThe disk system is accessed through a many level addressing scheme.  First a particulardisk drive is selected.  Then a data surface or head and a cylinder are selected (5 surfaces,815 cylinders on a T-80).  Each cylinder is further divided into sectors which consist ofblocks.Firmware may control the following parameters:Sector size (1378 words max., limited by 4-bit subsector counter)Number of blocks within one sector (1 to 4)Block sizes (2 to 2684 words)Note: Various limits on the sizes of blocks and sectors will be discussed.  The processor interface allowsa six-bit subsector counter of which only four bits are presently implemented, and this is the mostsignificant length limit at present (1378 words).  If the subsector counter were enlarged to six bits, thenthe block size limit imposed by the error correction algorithm (2684 data words) would apply.  We are,however, unlikely to find any of these length limits significant unless we enlarge the memory page size to4096 words.  Jumpers in the disk unit could also be set to vary the spacing between subsector pulses.Because sector formats are flexible, firmware can adjust the controller to system needs.The sector formats specifically envisioned in the design of the controller include 28 256-word sectors for Alto Diablo emulation and Pilot, 16 512-word sectors for Juniper, and 91024-word sectors for Alto Trident emulation.Sector Layout ConsiderationsEach block within a sector can be either read, written, or checked.  However, once anyblock is written, later blocks in that sector cannot be read during that disk revolution.(Later blocks should be readable on subsequent disk revolutions, though this is notguaranteed and no existing software depends on this.)  Reading or writing must start withthe first block in the sector and continue; since check bits are stored at the end of eachblock, the entire block must be read to verify its data or correct errors; however, one doesnot have to read or write subsequent blocks in the sector.  After a check-block operation isstarted, the controller inhibits writing later blocks within a sector without a specific "OK"from the firmware.Our general plan is to use the first block in a sector as a header identifying the diskaddress; all headers will be written when a disk pack is initialized; subsequently, the disktask compares the header with the disk address it thinks it is accessing.  The header notonly provides a useful safeguard against positioning errors but also allows faster sectordetermination when switching to a new drive, as discussed later.The second block might identify information stored in the sector (e.g., the Label block inAlto format).  The third block might be the data block.  The fourth block could holdreference, backup, or archiving information.  All of these choices are a matter ofprogramming convention.������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�Xî"
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=èZŠ9��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisk Controller  14 September 198194Feasible sector layouts are determined by several considerations.  First, each disk drive isconfigured to generate 117 subsector pulses/revolution.  The disk controller has asubsector counter for each drive that is initialized to N when an index pulse is receivedfrom the drive; it then counts down to -1, generates a sector pulse, and reinitializes itself.The firmware can specify N (0 to 178) independently for each disk drive and thus create117/(N+1) sectors/revolution.  If this division leaves any remainder, then there will be oneor more unused subsectors at the end of the cylinder.Note that the quantization of cylinders into subsectors allows a sector size to be specifiedin units of 10,080/117 = 86.15 words/subsector.Various delays must be provided at the beginning and end of each block to allow forelectrical and mechanical tolerances within the disk drive.  To define a sector format, onesimply needs a summary of "words lost" for each block:Total words/track =10,080Words lost for the 1st block in a sector =38Words lost for successive blocks =14Required gap at end of sector =(microcode-dependent)A track is the path swept through one revolution by a single head at a single cylinder."Words lost" for each block include 2 words of error detection and correction (32 bits ofECC code) which are always added at the end of the data written, plus preamble,postamble, and various other delays required by the controller and drive electronics.These are detailed later under "Format RAM and Sequence PROMs".  Additionally, toenable the microcode to process consecutive sectors, there must be some gap betweenthe end of the last block and the end of the sector; the number of words required dependson the amount of time the microcode requires to complete processing the last block andissue a command for the next sector.For the Alto Trident format there is a 2-word Header block, 10-word Label block, and 1024-word data block; total words lost for disk formatting is 38 for the first block, 14 for thesecond, and 14 for the third; altogether, this requires 1100 words/sector.  The next largermultiple of the subsector size is 86.15*13 = 1119 words, leaving 19*1.65 = 31.35 ms ofgap at the end of the sector.  Thus 13 subsectors/sector are required, yielding 117/13 = 9sectors/revolution.Using this kind of analysis, reasonable sector layouts on the T-80 are as follows:29 sectors of 256 data words each (4 subsectors/sector),16 sectors of 512 data words each (7 subsectors/sector), or9 sectors of 1024 data words each (13 subsectors/sector).Note: The 29-sector and 16-sector formats do not divide the disk evenly but rather yield an unusableleftover fraction of a sector; the 9-sector format does divide the disk evenly.  The 9-sector format iscompatible with the Alto Trident 9-sector format (used by BCPL Trident software such as IFS).  The 16-sector format is not compatible with the Alto Trident 16-sector format (used by Juniper), though it isusable if interchangeability of disk packs with Altos is not required.  The 29-sector format has no Altoanalogue.����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�Xî"
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qpôî·ï^‰qô�²pð&ô�³ð"î·ï\¾ô�ðHô�žî·ïZóô�¬ð#ïZfs�ïZópô�­î·ïY)ô�ð6ô�Žð&î·ïW^ô�ð5î·ïSìô�—ô�˜ðOî·ïR"ô�ð/î·ïN°ô�ÏðSî·ïLåô�™ð<ô�šî·ïKô�ð6îxïG¨ô�Xî)€îxïEÞð*î)€îxïDð"î)€îxïBIî)€î·ï>×ô�½qpô�¾ðPî·ï=ô� ðVô�¡î·ï;Aô�üð+ô�ýð$î·ï9wô�òð>ô�óî·ï7¬ô�Ôô�ÕðHî·ï5âô�´ô�µð?î·ï4ô�‰ð4ô�Šð%î·ï2Lô�¦ô�§ðFî·ï0‚ô�ð$î·ï-ô�‡ðPô�ˆ	î·ï+Eô�¹ðIô�ºî·ï){ô�˜ô�™ðEî·ï'°ô�ªô�«ðBv�pî·ï%åô�‚
ô�ƒðLî·ï$î·ï ©ô�ðRîxï¡ð9îxïÖð<îxïð:îxïJtsô�³ðMô�´îxïéô�¸ð]ô�¹	îxïˆô�˜ðOô�™îxï(ô�·tsð2ô�¸îxïÇô�¦ð5ô�§ð3îxïf�������:����·C=èWÈ;����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisk Controller  14 September 198195Table 23:  T-80 Specifications and CharacteristicsCapacity82.1 million 8-bit bytes unformattedTransfer rate9.67 x 106 bits/sec (= one 16-bit word/1.65 ms)Cylinder positioning time6 ms cylinder to cylinder maximum (3 ms typical)30 ms average55 ms maximumRotational speed3600 rpm (16.66 ms/revolution)Sector length selection12-bit increments through jumpers on sector boardDensities370 cylinders/inch6060 bits/inch max. recording densityDisk pack characteristicsIBM 3336-type components5 recording surfaces plus 1 servo surface815 cylinders/surfaceOperating methodsModified frequency modulation recordingLinear positioning motor with cylinder following servoMechanical specificationsSize - 17.8" wide x 10.5" high x 32" deepWeight - 230 lbs.Error rateRecoverable: 1 error/1010 bitsIrrecoverable:  1 error/1013 bitsPositioning:  1 error/106 seeksPack start/stop time20 sec start time20 sec stop time (with dynamic braking)Controls and indicatorsReady IndicatorOff = disk not spinningFlashing = spinning up/downOn = ReadyFault IndicatorStart/Stop switchRead-only switchDegate switch (inside the drive; takes disk off-line for testing)General Firmware OrganizationThis section gives a general overview of how the disk controller firmware is organized;more detailed descriptions follow later.The disk drive generates subsector and index pulses on one line in the radial cable; thecontroller distinguishes these according to pulse width.  In the normal Idle loop, thecontroller looks only at these pulses from the connected drives.  A four-bit counter for eachdrive counts down subsector pulses and generates sector pulses.  Upon either a sector oran index pulse from the selected drive, the controller generates a disk task wakeup.  Thedisk task then either increments (sector wakeup) or zeroes (index wakeup) its firmwaresector counter, clears the wakeup condition, checks for a new command, and blocks.Because there are no hardware sector counters, the disk task must maintain a sectorcounter itself; this implies that the rotational position is generally unknown on alldeselected drives.����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�Xî"
qî0ìpîGïfñîLïbAwô�Fð2î·ï_9sîQô�ð$î·ï]ô�€îQô�ï]’�ï]ð"v�sî·ïZ­ô�€îQ�ô�ð/îQïYLîQïWëî·ïU·ô�€îQô�î·ïS‚ô�€îQô�ð+î·ïQNîQîQïOíð%î·ïM¹ô�€îQô�îQïLXð)îQïJ÷î·ïHÃô�€îQô�îQïGbð6î·ïE-ô�€îQô�ð%îQïCÍî·ïA˜ô�€	îQô�
ïB%ïA˜îQï?ñï@~ï?ñîQï>Jï>×�ï>Jî·ï<ô�€îQô�îQï:´ð'î·ï8€ô�€îQô�	îï7îï5¾îï4^	îQï2ýîQï1œîQï0;îQï.ÚðAî·ï*¸uô�Xî·ï'Fpô�Æð@ô�Çî·ï%|ô�ð(î·ï"
ô�¬qpqpô�­ð%î·ï ?ô�èðRô�éî·ïtô�€ð.ô�ð/î·ïªô�“ð1qpô�”	î·ïßô�žqpô�Ÿð9î·ïô�Æð:ô�Çî·ïJô�Õô�Öð<î·ïØô�Ôð$ô�Õð/î·ï
ôðFôî·ïCô�ÿ�������^����·ü<èX>����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisk Controller  14 September 198196When first selecting a drive, there are two strategies for determining the sector position:  (1) Wait foran index wakeup, at which time the sector position becomes known; (2) Wait for a sector wakeupand then read the sector number stored in the header block (This can only be done if the disk isnot moving to a new cyclinder.).  The most efficient strategy appears to be a combination:  Selectthe drive and start a seek to the correct cylinder; if an index wakeup arrives before the seek isfinished, then the sector position is synchronized with no loss of time.  If the seek finishes first, thenread the next header to determine the sector number. When a new disk operation is noted, firmware will perform the following steps:Execute a drive-select command, if the drive differs.Load the sector size only if different, and block until index.Load the format RAM only if word count or commands differ.Execute a Control Tag (seek) command only if the cylinder differs, and wait (continuingto count sectors) until the drive becomes ready again.Execute a Head Tag command.Block until, at a sector wakeup, the next sector is the one wanted.Load the appropriate transfer command into the control registerBlock until the next sector wakeup.At the start of the next sector, the controller will become active and sequence throughcommands under control of the format RAM and two sequence proms (one for reading,one for writing).The sequence proms define what operations the controller must go through, and the formatRAM contains all parameters that might change from one implementation to another.Actual commands for the Trident disk are stored in the format RAM along with countvalues such as words/block, words of ECC, and words of delay before some operation; thecommands are loaded into the tag register and executed by the controller during thetransfer.Once a transfer has started, the disk task will be woken according to the number of wordsin the FIFO, and it will send or receive the appropriate number of words.  Read andcompare operations are performed by firmware, as well as detecting checksum errors atthe end of reading.  During writing, firmware must provide one word of sync bits (2018standard, 0018 for Alto Trident emulation) followed by the specified number of words forthat block (the controller will append 2 words of checksum).  During read, the controllerwill look for, and discard, the first word of sync bits, then firmware must accept thespecified number of words for that block, followed by two words of checksum to bediscarded, followed by the ECC remainder to be used for error detection/correction.Task WakeupsThe controller may wakeup the disk task for many conditions; the disk task must deteminethe cause and take appropriate action, which must in some way cause the wakeup to goaway.In general, there are two ways to determine the wakeup condition:  read the wakeupcondition, or assume the condition knowing the state of the disk task (which implies thestate of the controller).  When expecting a sector or index wakeup, the disk task must testcarefully to count sectors reliably, but in the middle of word transfer operations, it willÿ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�Xî"
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qpð?î·ï?ªô�¸ô�¹ð4î·ï=àô�î·ï:nô�ô�‚ð:î·ï8£ô�íð6ô�îî·ï6Ùô�Óð(ô�Ôð*î·ï5ô�‡ð6ô�ˆð!î·ï3Cô�Úô�Ûð3î·ï1yî·ï.ô�Žð/ô�ð*î·ï,<ô�ÖðSî·ï*rô�³ô�´ðCî·ï(§ô�»ðFô�¼ï(�î·ï&¹ô�¬ï&,�ï&¹ô�­ðFî·ï$Ëô�®ðYî·ï#ô�àð%ô�áð1î·ï!6ô�ãð?ô�äî·ïkô�òð3ô�óî·ï&uô�Xî·ï´pô�“
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ô�ô�‘ð<î·ïMô�Éð9ô�Êð"ÿ�������’����·=è];����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisk Controller  14 September 198197assume the wakeup reason to minimize overhead.  The various conditions are as follows:IndexTW, SectorTW, TagTW, RdFifoTW, and WrFifoTW; these wakeup conditions aredetailed in the "Muffler Input" section.Control RegisterThe DiskControl register is a collection of flip-flops defining the state of the controller; onOutput to DiskControl, IOB is interpreted as follows:B[5]Clear EnableRunB[6]Set DebugModeB[7]Set BlockTilIndexB[8:9]Operation for first block of sector, where the operations are:0 = Done (finished with all blocks in this sector)1 = Write2 = Read and check3 = ReadB[10:11]Operation for second block of sector, as above.B[12:13]Operation for third block of sector, as above.B[14:15]Operation for fourth block of sector, as above.EnableRun determines whether the controller is active at all.   It is initially cleared byIOReset, and can only be set by completing the loading of the format RAM (see below).DebugMode allows the controller to be exercised by diagnostics when no disk is present; inthis case, diagnostic firmware provides fake disk bit-clocks and data.  The flip-flop iscleared by DisableRun.BlockTilIndex can be set to disable sector and index task wakeups until (a) the selecteddrive is ready, and (b) an index pulse is received from the drive.  It is cleared by an indexwakeup.  This is useful after switching drives or executing a ReZero operation, either ofwhich causes the controller to lose sector synchronization with the drive.  BlockTillIndexprevents the wakeup conditions from being set until these conditions are met, but does notclear any such wakeups that have already occurred.  To prevent races, it is necessary toclear SectorTW and IndexTW, then set BlockTillIndex, then clear SectorTW again.A request for a sector transfer is initiated by loading bits 8 and 9 of the control registerwith a non-zero value.  Then the controller will wait until the next sector pulse to set the"Active" flip-flop and execute the transfer.  Once a transfer has been started, it may beaborted by loading a new value into the control register twice.  The first will clear theActive flip-flop, and the second will load the control register.  (When Active, the controlregister is enabled for shifting commands rather than loading of io data.)Format RAM and Sequence PROMsThe format RAM is a 16-word by 12-bit register that holds commands and delay countsused by the controller during a transfer.  Words within the RAM are used according to thefollowing table; the example values are appropriate for Alto Diablo disk emulation (2-wordheader, 8-word label, and 256-word data record).ÿ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�Xî"
qî0ìpîGïfñî·ïbô�£ð.ô�¤ð(î·ï`Sôð7ôî·ï^‰ô�ð(î·ïZCuô�Xî·ïVÑpô�žðPô�Ÿî·ïUô�ð5îxïR"sîô�FîxïPžîîxïOîîxïM•îð>î'ïLXô�ð2î'ïKî'ïIÝî'ïHŸîxïGîô�Fð/îxïE—îð.îxïDîð/î·ï@¡pô�Íð8ô�Îð"î·ï>×ô�°ðDô�±î·ï;eô�ô�‚ðJî·ï9šô�Ý	ô�ÞðNî·ï7Ðô�î·ï4^ô�¯ð*ô�°ð.î·ï2“ô�“ô�”ðNî·ï0Èô�°ð=ô�±î·ï.þô�°ð?ô�±î·ï-3ô�ˆô�‰ðKqî·ï+ipô� ô�¡ðBî·ï)žô�ðOî·ï&,ô�¬ô�­ðSî·ï$aô�£ð@qpô�¤î·ï"—ô�±ðYî·ï Ìô�Äô�ÅðEî·ïô�·ðAô�¸î·ï7ô�ðJî·ïñuô�Xî·ïpô�ºð.ô�»ð%î·ïµô�ð*ô�‘ð/î·ïêô�¡ð#ô�¢ð7î·ï ô�ð0�������
b����·Ù=èX2%������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisk Controller  14 September 198198ExampleAddrDescription Value00Word count of the first block000101Word count of the second block000702Word count of the third block037703Word count of the fourth block000004Control tag command for a read operation010405Control tag command for a write operation020406Control tag command to set Head Select000407Control tag command to zero the tag bus000008Word count to write zeroes before writing the 1st block of a sector003309Word count to write zeroes before writing the sucessive blocks000610Word count to wait before reading the 1st block of a sector001111Word count to wait before reading the sucessive blocks000212Word count of ECC words plus one000213Word count of 2000114Word count of 1 (minimum count)000015Not used0000Notice that the format RAM contains both word counts and tag commands.  Word countsare 1 less that the desired count.  Tag commands will be loaded into the tag register (seebelow) and then used as a "control tag function" by the Trident disk.  The values in theright column are those used for the Alto Diablo emulation format.  Notice that all but thefirst 4 values are determined by characteristics of the drive being used as opposed to thespecific sector format.  The meaning of the tag command values can be found in the "TagRegister" section.The format RAM is addressed in two ways.  During a transfer, sequence PROMs move datafrom the RAM into either a tag register or a count register.  At other times, the Dorado mayaddress the RAM with the RAM Address register, which is zeroed when the control registeris written; executing an Output to the DiskRam register writes IOB into the RAM at thecurrent address and then increments the address.  Loading the last word in the formatRAM turns on the EnableRun flip-flop allowing normal disk control activity.  The formatRAM may be read via the muffler scheme discussed later.There are two sequence PROMs, one for reading (or checking) and one for writing.  ThePROMs are addressed by a program counter that is initialized to zero at the beginning of asector and is incremented upon completion of each PROM program action.  Either the readPROM or the write PROM is selected according to the operation being performed on thecurrent block.The sequence PROMs are clocked by WordClock, which is derived from the disk bit clock,which in turn is derived from timing information pre-recorded on the disk pack.  Thesubsector pulses generated by the drive are also derived from this timing information.  Thisenables very precise placement of the data on the disk, in a manner that is independent ofthe disk's rotational velocity or the Dorado's clock rate.��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�Xî"
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x����·d<èO§N��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisk Controller  14 September 198199The read and write sequence PROMs are described in the following tables.Write Sequence PROMDurationAddrDescription(WordClocks)00Issue tag command in RAM[6] (head select)101Delay (wait for head select to settle)RAM[13]+102Issue tag command in RAM[5] (write command)103Write long preamble for first blockRAM[8]+104Write sync word105Write data for first blockRAM[0]+106Write first ECC wordRAM[14]+107Write second ECC word and 2 postamble wordsRAM[12]+108Advance control register to the operation for the next blockRAM[14]+109Issue tag command in RAM[5] (write command)110Write short preamble for second blockRAM[9]+111Write sync word112Write data for second blockRAM[1]+113Write first ECC wordRAM[14]+114Write second ECC word and 2 postamble wordsRAM[12]+115Advance control register to the operation for the next blockRAM[14]+116-22Same as 09-15, except step 19 uses RAM[2]+123-29Same as 09-15, except step 26 uses RAM[3]+130Zero the tag bus131Not usedRead Sequence PROMDurationAddrDescription(WordClocks)00Issue tag command in RAM[6] (head select)101Delay (wait for head select to settle)RAM[13]+102Delay (skip over early part of preamble)RAM[10]+103Issue tag command in RAM[4] (read command)1Note: WordClocks cease until controller has read sync word from disk04Read data for first blockRAM[0]+105Read ECC wordsRAM[13]+106Compute first word of ECC remainder, issue tag command in RAM[6]107Compute second word of ECC remainderRAM[14]+108Advance control register to the operation for the next blockRAM[14]+109Delay (skip over early part of preamble)RAM[11]+110Issue tag command in RAM[4] (read command)1Note: WordClocks cease until controller has read sync word from disk11Read data for second blockRAM[1]+112Read ECC wordsRAM[13]+113Compute first word of ECC remainder, issue tag command in RAM[6]114Compute second word of ECC remainderRAM[14]+115Advance control register to the operation for the next blockRAM[14]+116-22Same as 09-15, except step 18 uses RAM[2]+123-29Same as 09-15, except step 25 uses RAM[3]+130Zero the tag bus131Not usedTag RegisterThe 16-bit tag register drives the tag bus on the daisy-chain cable; all disk drive commandsare initiated through the tag register.  The tag register is sometimes loaded from IOB via anOutput command to DiskTag, sometimes from the format RAM.  Loading a Head Tag,Cylinder Tag, or Control Tag into the tag register (from either source) activates a timingcircuit that handles all timing requirements of the Trident drive as follows:  Only the tag busbits are enabled for the first 200 ns; then the Tag[0:3] bits are also enabled for 1.2 ms;finally, the Tag[0:3] bits are disabled again and the TagTW flip-flop is set to wakeup thedisk task (indicating completion of the Tag instruction).  The Drive Select Tag (Tag[0]) doesnot activate the timing circuit, since the timer counts disk clock cycles, but disk clocks areinvalid during drive select changes.����������������������������������������������������������������������������������������������������������������î·ïfªpô�Xî"
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î9 î]ï[]sî ð)î:_�î]ïZ î ð&î:_î]ïXâî ð+î:_�î]ïW¥î ð#î:_î]ïVgî î:_�î]ïU*î î:_î]ïSìî î:_î]ïR¯î ð+î:_î]ïQqî ð<î:_î]ïP4î ð+î:_�î]ïNöî ð%î:_î]ïM¹î î:_�î]ïL{î î:_î]ïK>î î:_î]ïJ�î ð+î:_î]ïHÃî ð<î:_î]ïG…î ð+î]ïFHî ð+î]ïE
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î9 î]ï=/sî ð)î:_�î]ï;òî ð&î:_î]ï:´î ð(î:_î]ï9wî ð*î:_�î ï89tðDî]ï6üsî î:_î]ï5¾î 
î:_î]ï4î ð@î:_�î]ï3Cî ð$î:_î]ï2î ð<î:_î]ï0Èî ð(î:_î]ï/‹î ð*î:_�î ï.MtðDî]ï-sî î:_î]ï+Òî 
î:_î]ï*•î ð@î:_�î]ï)Wî ð$î:_î]ï(î ð<î:_î]ï&Üî ð+î]ï%Ÿî ð+î]ï$aî î:_�î]ï#$î î·ïuô�Xî·ïpô�„	ô�…ðRî·ïÅô�ƒð0ô�„ð-î·ïúô�Õð4ô�Öî·ï0ô�±ô�²ðBî·ïeô�ðAô�‚î·ï›ô�·ðRô�¸v�pî·ïÐô�®ô�¯ð<î·ïô�ô�‚ðHî·ï
;ô�ô�Žð>î·ïpô�ð$ÿ�����������·)<è\âÆ��������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisk Controller  14 September 1981100Bits 4 through 15 of the tag register are interpreted according to the following table:Tag[0]Drive select and subsector countTag[4:15] are interpreted by the controller to effect drive select orsubsector counter changes.  The tag timing and wakeup circuit is notactivated; firmware must take care of the timing by first loading Tag[4:15]as desired but with Tag[0:3] equal 0, then or-ing in the Tag[0] bit andoutputting again. 4:9Subsector countDivide the 117 subsector pulses from disk by subsector count+1 to form Sectorpulses (Tag[4:5] are presently unimplemented).Tag[4:9] = 3 yields 29 sectors large enough for 256-word data blocksTag[4:9] = 6 yields 16 sectors large enough for 512-word data blocksTag[4:9] = 148 yields 9 sectors large enough for 1024-word data blocks  10Load subsector from Tag[4:9] for the drive selected prior to the execution of thistag instruction.11:15Drive selectThe basic controller handles up to 4 disk drives; additional units may beaccommodated by adding drive dependent logic on an additional board andconnecting it in in place of drive 3.  To allow this, the 5 bit drive select field isinterpreted as follows. 0 - 3select drive 0 to 3, respectively 4 - 368select drive 3378don't select any driveTag[1]Head TagLoads a register in the drive that selects the head to be used duringsubsequent read/write commands.  A Tag wakeup occurs at completion(1.6 ms). 4:7Unused   8Off Cylindermay be activated during a read to attempt recovery of unreadabledata.  It causes cylinder positioning to be offset 80 micro-inches.   9Determines direction of offset if bit 8 is set.10:15Head numbervalues from 0 to 4 are valid for a T-80, 0 to 19 for a T-300.  Thedrive will turn on "EndOfCylinder" (alias HeadOverflow) error if an invalid headaddress is issued.Tag[2]Cylinder TagCauses the drive to seek to the specified cylinder.  A Tag wakeup occursafter the tag timing sequence has completed (1.6 ms), and the NotReadystatus bit is raised until the seek has completed (3 to 55 ms depending onthe seek distance). 4:15Cylinder number (0 to 814 for Trident disks presently in use).  An illegal cylindernumber will cause DeviceCheck to be raised.Tag[3]Control TagA Tag wakeup occurs at command completion (1.6 ms) and uponcompletion of the last read/write operation in a sector.  Generally, ControlTag commands are issued only by the controller itself (using tagcommands from the format RAM) rather than by the microcode; DeviceCheck Reset and ReZero are an exception.ÿ����������������î·ïfªpô�Xî"
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î~ï'�ô�›ðKô�œî~ï%Ÿô�îxï"Ppîûîûï †ô�•ô�–ð)îûï»ô�©ð+ô�ªv�pîûïðô�‰ð7ô�Šîûï&ô�îûïdsô�€î~ô�ƒô�„ð>î~ïô�ð+îxïµpîû
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y;è]’x��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisk Controller  14 September 1981101   4AltoLeaderspecial flag to the controller that allows disks written by an AltoTricon Controller to be read.  This bit should only be used for the Alto Tridentsimulation.   5Unused   6Strobe Latecauses data recovery circuits within the drive to sample data earlywithin the data bit time (for recovery when the drive is experiencing excessiveread errors).   7Strobe Earlylike StrobeLate except in the obvious way.   8Writeturns on the write circuits.   9Readturns on the read circuits.  10Unused  11Reset Head registerzeroes the head address register in the drive.  12Device Check Resetresets all latched error conditions in the drive.  13Head Selectturns on the head selection circuits, in conjunction with a Read orWrite.  14ReZerorepositions the heads to cylinder 0 (if the heads are loaded) and resetsthe head address register; resets SeekIncomplete and DeviceCheck errorconditions.  15Head Advanceincrements the head address register in the drive.FIFO RegisterData to/from the disk is buffered through a 16-word FIFO (25 ms of buffer), which isread/written with Pd_Input/Output_B when TIOA selects DiskData.  Each FIFO word holds16 data bits, 2 parity bits, and a 2-bit field indicating that the next word to be read is eitherwrite, read, or read-and-check type data.  During output to the disk, the controller checksparity both when receiving data on the io bus and again when reading the FIFO.  During adisk read, parity is computed before writing into the FIFO, is passed through the FIFO, andis then written on the io bus for the processor to test.Muffler InputDorado uses a multiplexor scheme called the muffler system for reading miscellaneouslogic signals during debugging from the Alto or baseboard.  The disk controller also allowsa muffler address to be specified on an Output to the DiskMuff register; in this way, anyDskEth board signal available through the multiplexors (mufflers) is also available forfirmware sampling.  Other bits of the DiskMuff register output specify other operations asfollows:B[0]Simulate read data of 1 for 1 cycle  (for use by diagnostic programs)B[1]Simulate read clock of 1 for 1 cycle  (for use by diagnostic programs)B[2]Clear CompareErrdone by disk task if a read&compare is found to be OKB[3]Set ReadDataErrdone by disk task to inhibit future writesB[4]Clear the index wakeup flip-flopB[5]Clear the sector wakeup flip-flopB[6]Clear the tag wakeup flip-flopÿ��������������������������������������������������������������������������������î·ïfªpô�Xî"
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ô�îûïQ¸ô�€î~	ô�îûïOƒô�€î~îûïMOî~ô�ðBîûïKô�€î~ô�ð>îûïHæô�€î~ô�†ðKî~ïG…îûïEQô�€î~ô�…	ô�†ð3î~ïCðôôð,î~ïB
îûï@[ô�€î~ô�ð;î·ï<8uô�Xî·ï8Æpô�×ð)ô�Øv�pî·ï6üô�ˆðEô�‰î·ï51ô�ˆðLô�‰î·ï3gô�›ð[î·ï1œô�Žð-ô�ð+î·ï/Ñô�ŒðEô�î·ï.ô�ð8î·ï)Áuô�Xî·ï&Opô�Ïð3ô�Ðð!î·ï$…ô�‹ð?ô�Œî·ï"ºô�«ð5ô�¬ð$î·ï ïô�îðAô�ïî·ï%ô�¥ðFô�¦î·ïZîxï¼sî ô�FðEîxï~î ðFîxïAî ðFîxïî ð:îxïÆî îxïˆî ð!îxïKî �������	°����·(<èTãC������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisk Controller  14 September 1981102B[7]Clear all error flip-flops within the controller (not the disk drive)B[8:15]Muffler addresssignals are enumerated belowFollowing an output to the DiskMuff register, the firmware must wait one cycle beforeinputting the selected muffler signal with Pd_Input.  The state of the signal selected will bedriven on IOB[15], and the remaining bits will be zero.  For the purpose of examinationfrom Midas, the signals are grouped into 16-bit words, as shown in the following table.  Thebits within each word and an appropriate explanation follow:KSTATEvarious bits indicating the state of the controller  000TempSensesee "Dorado Debugging Interface" document  001IndexTWdisk task wakeup is due to an index pulse; index pulses occur once/diskrevolution (16.7 ms) and are used to synchronize the hardware subsectorcounter and the firmware sector counter.  An index pulse also causes aSectorTW.  002SectorTWdisk task wakeup is due to a sector pulse.  To maintain a reliable sectorcount in a race-free manner, the microcode must (a) check for SectorTW,and upon finding it set increment the sector number and clear SectorTW;(b) check for IndexTW, and upon finding it set zero the sector number andclear both IndexTW and SectorTW.  003TagTWdisk task wakeup is due to completion of a Head Tag, Cylinder Tag, orControl Tag command.  This occurs 1.6 ms after issuing an Output to theDiskTag register, and also upon completion of the last read/write transferin a sector.  004RdFifoTWdisk task wakeup is due to presence of at least 3 words in the FIFO duringa normal read or 1 word during a read-and-check.  During a normal read,an Input that reduces the FIFO below 3 words will drop RdFifoTW in timefor a Block to take effect on the 5th cycle following the Input; this permitsa 2-cycle loop (Input, Block).  During a read-and-check, an Input thatempties the FIFO will drop RdFifoTW in time for a Block to take effect onthe 3rd cycle following the Input; this permits a 4-cycle loop (Input, no-op,no-op, Block).  005WrFifoTWdisk task wakeup is due to space for at least 4 words in the FIFO.  AnOutput that reduces the free space below 4 words will drop WrFifoTW intime for a Block to take effect on the 5th cycle following the Output; thispermits a 2-cycle loop (Output, Block).  WrFifoTW is enabled to occur byselecting TIOA[DiskData] when a write command is in progress; it isdisabled by TIOA[DiskControl], which the microcode executes afteroutputting the last data word of a block.  One more WrFifoTW will occurafter all data has actually been sent to the disk.  006ReadDataData bit from the disk (available for diagnostics)  007WriteDataData bit to the disk (available for diagnostics)  010EnableRunFormat RAM has been written, and wakeups are enabled  011DebugModeController has been placed in debug mode  012RdOnlyBlock'The controller is processing a block in normal read mode  013WriteBlock'The controller is processing a block in write mode  014CheckBlock'The controller is processing a block in read and check mode  015ActiveThe controller is processing a command for the current sector016:017Select.0..1The address of the currently selected drive unitKSTATvarious bits indicating the status of the drive/controller.  The controller willturn on WriteInhibit for the remainder of the sector after any of the followingerrors are detected, but will still go through all the motions of wordtransfers.ÿ��������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�Xî"
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z����·Ù<èX2Ë����������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisk Controller  14 September 1981103  020SeekIncThe disk drive has not correctly positioned the heads within the last 700ms.  A ReZero command must be issued to clear this error.  021HeadOvflThe head address given to the disk drive is invalid (i.e., greater than 4 fora T-80 drive).  022DevCheckOne of the following errors occurred:Head select, Cylinder select, or Write command and disk not readyIllegal cylinder address.Offset active and cylinder select command.Read-Only and Write.Certain errors during writing, such as more than one head selected, notransitions of encoded data or heads more than 80 micro-inches offcylinder.A ReZero command may be necessary to clear this error.  023NotSelectedThe selected drive is in "off-line" test mode or the selected drive is notpowered up  024NotOnLineThe drive is in test mode or the heads are not loaded  025NotReadyThere is a cylinder seek in progress or the heads are not loaded  026SectorOvflThe controller detected that a command was active when the next sectorpulse occurred.  This error implies either a hardware malfunction or adiscrepancy between the sector format of the drive and the word count theprogram thinks is appropriate.  027FifoUnderflowEither the FIFO became empty while writing (task got behind) or the FIFOhad too many words taken out of it while readng (microcode word count orwakeup error).  030FifoOverflowEither the FIFO became full while reading (task got behind) or the FIFOhad too many words put into it during writing (microcode word count orwakeup error).  031ReadDataErrA flip-flop in the controller for latching one of three errors:CompareErra read-and-check operation was executed on a block,and the microcode did not issue ClearCompareErr beforethe beginning of the next block.ECCErrorthe microcode can set the ReadDataErr flag if itdetermines that the ECC words after reading one blockare non-zero in order to inhibit future writes.ECCComputeErrThe ECC hardware within the disk controller failed togenerate a single "1" bit (i.e., a hardware malfunction).  032ReadOnlyThe "Read-Only" switch on the drive is on.  033CylinderOffsetThe cylinder position is currently offset.  This is a mode used for recoveryof bad data.  034IOBParityErrThe controller detected bad parity on the IOB bus.  035FifoParityErrThe controller detected bad parity on the data out of the FIFO.  036WriteErrOR of errors on muffler addresses 020-035  037ReadErrOR of errors on muffler addresses 020-031 and 034-035KRAMcontents of the format RAM040:043Address of format RAM word044:057contents of format RAM wordKTAGcontents of the tag register060:07720 bit value last loaded into the tag registerKFIFOstate of the io control logic������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�Xî"
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’����·Æ8ÆVE«��������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisk Controller  14 September 1981104  100ShiftInThe controller is currently shifting data into the FIFO  101ShiftOutThe controller is currently shifting data out of the FIFO  102ComputeECCThe controller is currently shifting data and computing the ECC checksum  103NextBlockOccurs between blocks within a sector  104LoadTagIndicates that the next word read from the format RAM should be loadedinto the tag register as opposed to the count register  105CntDone'Indicates that the count register is again zero, and a new value from theformat RAM will be loaded next  106OutRegFullThe holding register on the input to the FIFO has been loaded, but nottransferred into the FIFO.  107InRegFullThe holding register out of the FIFO has been loaded, but not read viaPd_Input or loaded into the output shift register.110:113FifoWaddrThe 4-bit address indicating where the next word will be written into theFIFO114:117FifoRaddrThe 4-bit address indicating where the next word will be read from theFIFO.  if FifoWaddr equals FifoRaddr then the FIFO is defined as empty.Error Detection and CorrectionTo allow high data density and a few surface imperfections during manufacture, Tridentdisk packs are not required to be perfect.  A disk pack is defined as suitable when no morethan three bad areas occur on any data surface; a bad area is defined as one which couldpotentially cause read errors of no more than 11 bits in length.  To correct errors arisingfrom these imperfections as well as other (infrequent) read errors, the controller implementsan error detection and correction scheme which will detect (with very high probability)errors of any length, and will allow correction of any burst error of 11 bits or less.Warning:  If an error burst longer than 11 bits occurs, there is a significant possibility that the errorcorrection algorithm detailed below will fail and double the number of bad bits!  Consequently, diskhandling programs should try other methods of error recovery before invoking the error-correctionalgorithm.To avoid problems, it is good practice to run diagnostic programs on new disk packs; note badsectors and don't use these during normal operation.When an error does occur, the first step is to try rereading the offending sector several times.  Oneof these reads may succeed.  If not, try rereading with the cylinder position offset or with the datastrobe early or late as discussed in the "Tag Register" section.  If these attempts all fail, then tryerror correction.Error correction is accomplished through a mixture of disk controller hardware (for ECCgeneration and checking) and system software/firmware (for error recovery).  This is acompromise between capability, speed, and cost.  The basic capabilities and restrictions ofthe 32-check-bit scheme are summarized below.1) A single error burst of length less than 12 data bits (i.e., a scattering of errorbits within the bit stream, all of which fit within an 11-bit span) can be corrected inblocks shorter than 2685 data words. (Example: for the data "0001100101", thedata "0000101101" contains a single burst error of length 4.).  The codeimplemented will detect errors in arbitrarily long blocks, but not enoughinformation exists to correct longer blocks.��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�Xî"
qî0ìpîFMïfñîÙïbsô�€î\îsô�ð4îÙï`0ô�€î\îsô�ð6îÙï^Bô�€î\	îsô�˜ð*ô�™îÙï\Tô�€î\îsô�îÙïZfô�€î\îsô�Ÿô� ð4îïXâô�ð6îÙïWô�€î\îsô� ð!ô�¡îïU”ô�îÙïSÉô�€î\	îsô�°ô�±ð+îïREô�îÙïPzô�€î\îsô�²ô�³ð.îïNöô�ð2îÙïM,î\îsô�©ð"ô�ªð'îïK¨îÙïIÝî\îsô�¹ô�ºð*îïHYô�ªð@ô�«î·ïD7uô�Xî·ï@Åpô�»ð:ô�¼î·ï>úô�ô�‚ð=î·ï=/ô�‹ð=ô�Œî·ï;eô�¡ðSô�¢î·ï9šô�€ð#ô�ð:î·ï7Ðô�Îð.ô�Ïð)î·ï6ô�éô�êðMîxï3Cwsô�…ô�†ðZîxï1ãô�•ð8ô�–ð,îxï0‚ô�«ð*ô�¬ð7îxï/!	îxï,ƒô�³ð)ô�´ð4îxï+"ô�ð4îxï(„ô�‹ðYô�Œîxï'#ô�–ðDô�—ð!îxï%Âô�žðWô�Ÿîxï$aô�î·ï!pô�´ô�µðGî·ïHô�ÉðVî·ï}ô�‹ð/ô�Œð,î·ï³ô�ð-îxïAô�©qpðAô�ªîxïvô�‡ð3ô�ˆð$îxï¬ô�¼ð@î;‰ïUþ�Æ�ï¬�î=ÛïUþ�Æ�ï¬�ô�½îxïáôîpïŠþ�Æ�ïá�îÂïŠþ�Æ�ïá�ôð,îxïôFôGð+îxïLô�ð,ÿ�������º����·<èY§����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisk Controller  14 September 19811052) Simple error detectiontwo words are returned by the hardware which are bothzero if the read is successful.3) Software/firmware error correction can be completed in less than one diskrevolution.  The correction procedure is well suited to a mixture of software andfirmware.  If done entirely in firmware, error correction would take less than 1 ms.4) Not all uncorrectable errors will be detected as such.  An uncorrectable errorrequires two bad spots on the disk surface within one sector (the pack isbadthrow it out!), an electronic error in a sector with a bad spot, or twoelectronic errors within one sector.  If such an error has occurred, it can, with aprobability of say 20 percent, result in an error pattern and displacement thatseems valid.  This will result in leaving the error bits uncorrected and changingsome bits which were in fact correct.  This means that for high data security, acheck code should be generated and imbedded as part of the data file beforewriting on the disk.The error-correcting code (ECC) generated is referred to as a Fire Code (see Error-Correcting Codes by Peterson).  The following is a detailed description of this code andrecovery procedure.The code calls for dividing the outgoing data stream by a polynomial of the form:P(X) = P1(X)(Xm + 1)Where P1(X) is an irreducible polynomial of degree n (n = burst length) and m is > 2*n.For this particular application the polynomials chosen are:P(X) = (X11 + X2 + 1)(X21 + 1)During a write, the two polynomials are multiplied together and implemented by hardware inthe form:P(X) = X32 + X23 + x21 + X11 + X2 + 1The data stream is premultiplied by X32 to make room for the 2 word ECC and thenreduced modulo P(X).  This is accomplished by the normal feedback shift registertechnique with the difference that to perform premultiplication, the output of the register isexclusive-or'd with the incoming data and then fed back.  After all data bits have beenshifted out, the contents of the ECC shift registers are appended to the disk block.During a read, the feedback shift register is reconfigured such that the two originalpolynomials are implemented separately.  The incoming data stream, including the 2appended words of ECC, is independently reduced modulo P0(X) and P1(X), whereP0(X) = X21 + 1������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�Xî"
qî0ìpîFMïfñîxïbô�ˆð'ô�‰ð(îxï`Sô�îxï\áô�ÙðLîxï[ô�«ô�¬ðAîxïYLô�“ô�”ð9îxïUÚô�ªô�«ðKîxïTôôð,îxïREô�ôð8ô�õîxïPzô�¤ðDô�¥îxïN°ô�×ð+ô�Øð$îxïLåô�¶ô�·ð?îxïKô�°ô�±ð9îxïIPô�Èð+ô�ÉîxïG…ô�î·ïDô�êð,ô�ëð!qî·ïBIô�°pð:ô�±
î·ï@~ô�î·ï=ðQî£ï9šï9
�ï9šï:'�ï9šî·ï6(ô�£ï5›�ï6(ô�¤ðIî·ï4:ô�ð;î£ï0Èï1Uï0Èï1U�ï0Èï1Uï0Èî·ï-Vô�€ô�ðKî·ï+Œô�î£ï(ï(§ï(ï(§ï(ï(§ï(ï(§ï(ï(§�ï(î·ï$¨ô�Óð%ï%5ï$¨ô�Ôî·ï"Ýôôð6î·ï!ô�‘ô�’ðAî·ïHô�¼ð%ô�½ð2î·ï}ô�îðAô�ïî·ïô�ñð:ô�òî·ïAô�õðBô�öî·ïvô�ð8ïé�ïvïé�ïv	î£ï�ïw�ïï‘ïÿ�������	(����·0=èUÛ:������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisk Controller  14 September 1981106P1(X) = X11 + X2 + 1After reading in all words off the disk, the contents of the two polynomial shift registers areread out of the FIFO.  If the data is recovered without error, then reducing it modulo P0(X)and P1(X) results in the registers containing all zeroes.If the data contains an error, then the two registers will be non-zero.  If one but not bothregisters is non-zero, then the error is irrecoverable.To recover from an error, a procedure is undertaken which determines the pattern of bitswhich are in error, and the displacement of this pattern from the end of the record.  I amsimply going to present the magic equation to be solved, and some magic constants to beused for solving this equation.  Much of the polynomial implementation and the equations,which use the "Chinese Remainder Theorem" are discussed in technical reports fromCALCOMP  (Calcomp Technical Report TR-1035-04, by Wesley Gee and David George) andXEROX (Xerox XDS preliminary report  "Error Correction Code for the R.M. Subsystem," byGreg Tsilikas, 28 March 1972.).The basic equation is:D = Q*LCM  (A0*M0*S0 + A1*M1*S1)where:Ei = modulus of the polynomialLCM = least common multiple of E0 and E1Mi = LCM/EiAi = a constant such that Ai*Mi modulo Ei = 1Q = smallest integer to make D positiveSi = number of shift operations to the appropriate polynomial remainders asdescribed below.D = displacement of right-most incorrect bit from the end of the record.The values of E0 and E1 were found by programming the procedure outlined in theCALCOMP report, and yielded the following result:E0 = 21        E1 = 2047The least common multiple (LCM) of E0 and E1 is simply the product of E0 and E1 sincethe two numbers have no factors in common.  Thus the LCM, which is also the recordlength which can be corrected, is 42,987 bits, or 26862 words.Knowing LCM and E0 and E1, the values of M0 and M1 are easily found to beM0 = 2047        M1 = 21The values of A0 and A1 are next determined using a trial and error approach that I put ina small program.  The results can easily be confirmed, and are given below:��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïgpô�Xî"
qî0ìpîFMïfñî£ïa‘�ïa�ïa‘ô�ïbïa‘ïb�ïa‘î·ï^ô�‡ð"ô�ˆð=î·ï\Tô�Œô�ð;ï[Ç�ï\Tî·ïZfô�ïYÙ�ïZfð3î·ïVôô�ðKô�žî·ïU*ô�ð7î·ïQ¸ô�ž	ô�ŸðNî·ïOíô�šðTô�›î·ïN#ô�’ô�“ðHî·ïLXô�–ô�—ðIî·ïJô�Üð:ô�Ýî·ïHÃô�‚ð8ô�ƒî·ïFøô�‚ð$ô�ƒð3î·ïE-ô�î·ïA¼î:ï>J
ï=½�ï>Jï=½�ï>Jï=½�ï>Jï=½�ï>Jï=½�ï>Jï=½�ï>J�îxï:Øî:ï9
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î:ï7ï6’�ï7ï6’�î:ï51�ï4¤�ï51ï4¤�î:ï3C�ï2¶�ï3Cï2¶�ï3Cï2¶�ï3Cï2¶�ï3Cî:ï1Uð'î:ï/‹�ï.þ�ï/‹ô�çðIî:ï-ô�î:ï+ÒðHî·ï(`ô�åï'Ó�ï(`ï'Ó�ï(`ô�æð8î·ï&sô�ð1î£ï#�ï"t�ï#
ï"t�ï#î·ïô�žð$ï�ïï�ïï�ïï�ïô�Ÿî·ï¡ô�¹ô�ºð>î·ïÖô�ð?î·ïdï×�ïdï×�ïdï×�ïdï×�ïdî£ïò�ïe�ïòïe�ïòî·ï€ô�Œïó�ï€ô�ïó�ï€ðCî·ï’ô�ðK�������Z����·K<èXãn����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisk Controller  14 September 1981107A0 = 19        A1 = 195All of the above values derived so far are constants determined for the particularpolynomials chosen.  The values of S0 and S1 are determined in the software from theerror patterns returned at the end of a disk transfer.S0 is first determined by a software procedure using the following steps:1) The remainder from dividing the input data by X21 + 1 is found in ECC[11:31];if this remainder is zero, then the error is uncorrectable.2) Test the low order 10 bits for all zeroes, and if not then perform a left circularshift on the 21 bits.  When the low order 10 bits are all zeroes, the error pattern isin the upper 11 bits of the word, and S0 is the number of times the circular shiftwas performed.3) If the low order 10 bits don't become all zeroes within 20 shifts (1 full cycle), theerror is uncorrectable.S1 is then determined in microcode as follows:1) The remainder from dividing the input data by X11 + X2 + 1 is found inECC[0:10]; if this remainder is zero, then the error is uncorrectable.2) Test this number to see if it is equal to the error pattern determined in step 3 ofS0, and if not reduce this number modulo X11 + X2 + 1 (left shift and XORfeedback).  When the contents of this word equals the error pattern (it isguaranteed to happen before 2047 reductions), S1 is determined as the number ofreductions performed (In the hardware implementation of switching from the writepolynomial to the read polynomials, it was easier to implement a polynomial thatpremultiplied by X11.  This means that the remainder returned by the hardwarealready has had 11 shifts performed.  To compensate, when S1 has beendetermined by the above procedure, you must add 11 to the value, and subtract2047 if the result is greater than or equal to 2047.).The basic equation for the displacement now looks likeD = Q*42,987  19*2047*S0  195*21*S1where:0 < S0 < 200 < S1 < 2046Notice that the straightforward solution to this equation cannot be done with single-precision arithmetic on the Dorado; to avoid double precision, the following manipulation ofthe equations is useful:������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïgpô�Xî"
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ïa‘�ïbî·ï^¬ôðCôî·ï\áô�¹ð$ï\T�ï\áï\T�ï\áð(î·ïZóô�ð6î·ïW�ïVô�ïWðGîxïTô�’ð"ô�“ïTœïTîxïREô�ð;îxïNÓô�›ô�œðNîxïMô�Šô�‹ð@îxïK>ô�Ÿð'ïJ±�ïK>ô� îxïIPô�
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ð-îxï2Lô�ð/ï1¿�ï2Lô�Ž	îxï0_ô�ðAô�žîxï.”ô�¯ðKô�°îxï,¦ô�½ï-3ï,¦ô�¾ð7îxï*Ûô
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ï²�îxïÍî:ïî�ï«þ�°�ï�ïu�ï�î]ï«þ�°�ï�î:ïî�ï¾þ�°�ï�ïˆ�ï�î]ï¾þ�°�ï�î·ï£ô�ñð@ô�òî·ïØô�†ðYô�‡î·ï
ô�ÿ�������h����·Æ<èVhY����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisk Controller  14 September 1981108D = Q*2047*21  19*2047*S0  4095*S1D = Q*2047*21  19*2047*S0  2*2047*S1  S1D'= Q*21  19*S0  2*S1where:0 < D' < 20D = 2047*D'  S1    (add 42,987 if D' = 0)For some reason that we don't understand, the actual required calculation must be D =2047*(D'+1)  S1 in the last step.  Also D' is conveniently calculated as (215*21  19*S0 2*S1) rem 21.ÿ������������������������������������������������������������������������������������������������������î·ïgpô�Xî"
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ï_£�ï`0ï_£�î:ï^Bï]µ�ï^Bï]µ�îxïZÐî:ïYî�ïX®þ�°�ïY�îïX®þ�°�ïY�î:ïW;ïV®�ïW;î·ïSÉqô�«ô�¬ð8î·ïQþô�‰ïQqt�ïQþqðHïQqt�î·ïP4qô�ïO§t�ïP4q�������š����·O„<èª�z����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisplay Controller14 September 1981109Display ControllerThe Dorado Display Controller (DDC) uses the fast io system to obtain representations ofvideo images from storage; it then transforms these representations into control signals formonitors.  Its three design objectives are:(1) To handle a variety of color, grey-level, and binary (black-and-white) monitors;(2) To utilize the full power of the fast io system in producing high-bandwidthcomputer graphics;(3) To allow various compromises in color and spatio-temporal resolution forexperimental purposes.  Clock rates, video signals, and other monitor waveformsshould be controllable by firmware.There are two independent video channels capable of running in a variety of modes.  Twochannels allow text to be displayed on one channel, graphics on another, or the mainpicture on one, cursor on the other.The DDC must readily handle Alto-style and LF (large format) monitors which we expect tobe standard for most systems.  Bit maps, display control blocks, and monitor controlblocks, similar to those used on the Alto, provide the software interface to the DDC.  The"seven-wire" video interface makes provision for one or more low bandwidth input devices(keyboard, pointing device, etc.); our current provisions for keyboard and mouse input arealso discussed in this chapter.Keep Figure 14 in view while reading this chapter.Operational OverviewVideo scan lines are encoded in bitmaps, which are contiguous blocks of virtual memory;the two channels, A and B, have independent bitmaps and data paths in the DDC.  Thehigh-priority DWT (Display Word Task) runs on behalf of either A or B using the subtaskmechanism; it transmits each bitmap to a FIFO consisting of 15 munches/channel.  Thebitmap stream emerging from the FIFO is then sorted into items (1, 2, 4, or 8 bits wide) foreach channel which are combined, mapped, and transformed into pixels (picture cells) onthe screen.In addition to the two channels, the DDC supports a programmable cursor that is 16 pixelsx 1 bit/pixel wide.A lower priority DHT (Display Horizontal Task) handles horizontal and vertical retrace andsets up starting addresses and munch counts, cursor data, and formatting information inthe NLCB (Next Line Control Block) for the DDC.  The NLCB is then copied into the CLCB(Current Line Control Block) during horizontal retrace prior to the next scan line.The rate-of-flow of items is governed by the resolution and pixel clock period.  Resolutionmay be independently programmed for each channel so that items flow at 1/4, 1/2, or 1times the pixel clock period.  If the DispM board is present, then the pixel clock period isalso progammable; otherwise, it is determined by a crystal oscillator on the DispY board,which must have a frequency appropriate for the monitor being driven.ÿ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"
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^ô�ªô�«ðHî·ï“ô�ðEÿ�����������·L<ð\¿5����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisplay Controller14 September 1981110Items can be treated in one of three ways:  First, an Alto monitor can be driven.  Second,items can be mapped through the 256-word x 4-bit MiniMixer into video data for a black-and-white or grey-level monitor.Three separate interfaces are provided on the DispY board.  An Alto monitor interface ORs one-bititems from the A and B channels with the cursor, and then XORs by polarity to produce one-bitpixels for an Alto display.  A seven-wire interface outputs 1 bit/pixel for a binary monitor.  And an 8-bit digital-to-analog converter (DAC) produces grey-level video.Third, items may be mapped by the Mixer (or A color map), a 1024-word x 24-bit RAM, intosignals for a color or grey-level monitor.  A variety of modes determine which bits from theA and B items address the mixer.  Mixer output consisting of 8 bits for each of the red,green, and blue guns is then digital-to-analog converted for color monitors.  Additionally,there is a 24-bit/pixel mode in which the Dorado supplies 8 bits for each of the threecolors; the colors are independently mapped through the Mixer and two additional 256-word x 8-bit RAMs called the BMap and the CMap.The DDC is implemented on two Dorado main logic boards, called DispY and DispM.DispY contains all the logic necessary for vertical and horizontal sweep control, channeldata paths, and video data for binary and grey-level monitors running at a fixed pixel clockrate.  DispM contains the color maps, the programmable pixel clock, and the three DACsfor driving a color monitor.  Additionally, DispM contains an independent terminal controllerthat is structurally similar to a one-channel, one bit/pixel DispY but is specialized to drivinga 7-wire terminal.Thus there are two principal DDC configurations.  On a Dorado with only a 7-wire terminaland no color monitor, only the DispY board is present; it is programmed for Alto terminalemulation, and only a small subset of its capabilities are used.  However, on a Dorado withboth a 7-wire terminal and a color monitor, the DispM board is also present; all of DispYand the color hardware on DispM are used to drive the color monitor, and the independentcontroller on DispM is used to drive the 7-wire terminal.Video Data PathFast IO Interface and FIFOThe fast io system delivers data to the DDC at a rate of 16 bits/clock; words are receivedalternately in the REven (t1) and ROdd (t2) registers shown in Figure 14, then written intothe FIFO, a 256-word x 32-bit RAM, during the first half of the next Dorado cycle (t2 to t3),leaving the second half of the cycle free for read access by the video channels.  In otherwords, the REven and ROdd registers widen the data path from 16 to 32 bits to allowsufficient time to both write and read the FIFO in one cycle.The 256 double-words in the FIFO are divided evenly among the two channels, so each hasbuffer storage for 16 munches.  Each channel has write and read pointers that address theFIFO when appropriate.Write pointers are initialized once during vertical retrace and then sequence throughaddresses for the entire display field; a write pointer is incremented after each double-wordwrite for its channel, so that the next word to be written is addressed at all times.  Sinceÿ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"
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=ð]üQ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisplay Controller14 September 1981111the fast io system delivers only one munch at a time, there is never any problem indeciding which of the two write pointers should address the FIFO.Read pointers, however, are initialized during each horizontal retrace, so that the correctfirst double-word is read at the start of every scan line.  This is required because the fast iosystem always delivers complete munches, but unused double words may appear at theend of the last munch for the previous scan line, or at the beginning of the first munch forthe current scan line; the read pointer has to be reinitialized to skip over these.  FIFO readsalternate between channels A and B, so the data rate for one channel is limited to 32bits/2 cycles (=16 bits/cycle).Note that bitmaps are required to start at even addresses because the FIFO is 32 bits wide.Item FormationAt the output end of the FIFO there is a multiplexor shared by both channels and, for eachchannel, two intermediate buffers (FIB and SIB), and a shift register SR.  The multiplexorpermutes the 32-bit quantity emerging from the FIFO so that when the double-word hasmarched through FIB and SIB and is finally loaded into SR, successive shifts will producesuccessive items of the selected size (8, 4, 2, or 1 bits).The SR is tapped as follows:SR.0Item[0] for item sizes 1, 2, 4, or 8;SR.16Item[1] for sizes 2, 4, or 8, gated to 0 for size 1;SR.8, SR.24Item[2:3] for sizes 4 or 8, gated to 0 for sizes 1 or 2;SR.4, SR.12, SR.20, SR.28Item[4:7] for size 8, gated to 0 for sizes 1, 2, or 4.All eight Item bits are gated to 0 if the channel is off.  It is useful to think at this point that,regardless of a channel's item size, an 8-bit wide item is produced, whose bits contain non-zero data only in those positions dictated by the item size; i.e., for size 1 only the mostsignificant bit may be non-zero; size 2 allows data in the topmost two bits, etc.The SR loads on the item clock after its last item has been used; the item clock rate is thepixel clock rate divided by the resolution (1, 2, or 4 for full, half, or quarter, respectively).Hence, for 8, 4, 2, or 1-bit items, SR will be shifted 3, 7, 15, or 31 times, repectively, and bereloaded from SIB on the following item clock.Synchronization of SR, which uses the item clock, with FIB and SIB, which use the Dorado systemclock, is a little tricky.  SIB_FIB will occur no later than (4.6 ns)+C+(1.1 ns)+C+C = 3*C+5.7 nsafter SR_SIB, where C is the period of the Dorado system clock and 4.6 ns and 1.1 ns are the worstcase propagation delay and setup time of the components in the synchronizer; FIB_FIFO will occurat this time or on one of the next three Dorado clocks, depending upon which of these four clockscorresponds to t2 of the cycle in which this channel can read the FIFO.  Allowing for propagationdelay through SIB (5.0 ns) and setup time for SR (1.7 ns), the worst case minimum spacing betweenloads of SR is 3*C+(5.7 ns)+(6.7 ns) = 3*C+12.4 ns.  This must be less than the time foremptying SR which is I*(32/ItemSize), where I is the period of the item clock.  Hence, I >(3*C+12.4)/4 for ItemSize=8, or I > 25.6 ns for a Dorado clock period of C = 30 ns.The 8-bit items from the two channels are then presented to either the Mixer section on theDispM board or the MiniMixer or Alto video interface on the DispY board.��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"
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=ðZôS����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisplay Controller14 September 1981112MixerThe Mixer is controlled by the A8B2, BBypass, and 24Bit mode controls.  It is a 1024-wordx 24-bit RAM for which the 10 bits of address required may be obtained from two possiblesource distributions, depending upon the A8B2 mode.  When A8B2 is true, the addressconsists of AItem[0:7] and BItem[0:1]; when false (called A6B4), the address is AItem[0:5]and BItem[0:3].Another mode, the BBypass mode, can be enabled independently for the B channel.  If B isbypassed, none of its bits contribute to the Mixer address.  Instead, they bypass the mixerand address a 256 x 8 RAM, the BMap, whose outputs are ORed with the mixer outputs forthe blue DAC.  For example, with ASize=8, BSize=4, BBypass true, and A8B2 true, andwith appropriate values in the Mixer RAM, the controller may be thought of as three 4/bitspixel channels driving three color guns.  One channel is bypassed data from B, while theother two are mapped through the Mixer.24Bit mode, used in conjunction with BBypass mode,  is used to run a three-channel colordisplay directly from memory.  In this mode, items from the A channel alternately addressthe Mixer (called the AMap in this mode) and another 256 x 8 RAM called the CMap.Meanwhile, the B channel runs at half the A channel rate and addresses the BMap asdescribed above.  (That is, the B channel must be set to one-half the resolution of the Achannel.)  With suitable values in the color maps, the AMap, BMap, and CMapindependently generate outputs for the red, blue, and green DACs respectively.Note: when the A channel is turned on, the first AItem addresses the AMap and the second AItemaddresses the CMap.  For the A and B pixels to align properly on the display in 24Bit mode, the leftmargin counts must be set to start the B channel one pixel clock earlier than the A channel.  Theblue and green portions of the AMap must be entirely zeroed, since the blue and green outputs areORed with the BMap and CMap.After routing as dictated by the mixer modes, chosen items are loaded into the mapaddress registers, causing the color maps to produce a new video value every pixel clock(every two pixel clocks in 24Bit mode), and these values are latched in the three 8-bit mixeroutput registers.  Three very fast DAC modules then produce a Red-Green-Blue triple ofanalog signals for a color monitor, or up to three grey-level video signals.  In conjunctionwith the sync, blank, and composite waveforms produced by the monitor control circuitry,these signals can drive a wide variety of monitors attached to the Dorado.Alto Video InterfaceA small circuit on the DispY board produces video for an Alto monitor.  This circuit ORsCursorData, AItem[0], and BItem[0], then XORs by the polarity, and finally ORs with thevertical and horizontal blanking signals.  This interface is obsolete and is no longer inactive use.MiniMixerA small video mixer on the DispY board, not to be confused with the large Mixer on theDispM board, can drive either a DAC or the seven-wire interface discussed later.  TheMiniMixer is a 256 word x 4-bit RAM addressed by a combination of AItem, BItem, and statebits, as shown in Figure 14.  On every pixel clock, dDAC[0:3] are loaded from MiniMixerÿ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"
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U=ð]¶D����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisplay Controller14 September 1981113output, while dDAC[4:7] are loaded directly from AItem[4:7].  The MiniMixer aims atexperiments with mixing channels and driving grey level monitors.Horizontal and Vertical ControlEvery monitor requires horizontal synchronizing and blanking waveforms.  Interlacedmonitors must be able to distinguish fractions of a scan line to implement interlacing.  Ingeneral, the duration and phasing of sync/blank waveforms is unique to a given monitor.The DDC uses the 1024-word x 3-bit HRam (Horizontal RAM) to control horizontalsync/blank.The DDC has a set of registers called the CLCB (Current Line Control Block) whichcontrols video generation for the current scan line.  The DHT sets up parameters for thenext scan line in NLCB (Next Line Control Block), a 16-word x 12-bit RAM.  The first 32pixel clocks of horizontal blanking are called the HWindow; during HWindow parameters forthe next line are copied from NLCB into CLCB.  Vertical control is also handled through theNLCB.The interpretation of fields in NLCB and HRam are shown in Figure 15 and loading will bediscussed in the "Slow IO Interface" section; the use of the different information isdiscussed here.  The top part of Figure 14 shows how horizontal timing is controlled.Line Control BlocksThe fields in NLCB/CLCB are interpreted as follows, where a denotes that the item ischannel-specific (i.e., copies exist for both A and B channels):aPolarity.  A single bit, used only for binary monitors, that inverts black and white(APolarity and BPolarity are or'ed by the hardware).aResolution.  A 2-bit field that controls item clock generation; values of 0, 2, and 3cause quarter, half, and full resolution, respectively.aItemSize.  A 4-bit field unary encoded as aSize1, aSize2, aSize4, or aSize8,denoting bits/pixel for the channel; setting multiple bits is illegal.aLeftMargin.  A 12-bit field in units of pixel clocks specifying 31 less than thenumber of pixel clocks to wait after HWindow completes before turning thechannel on.  This value is not a straightforward constant, but depends uponmonitor-specific horizontal blanking time.  If the horizontal blanking time is B pixelclocks and the desired beginning of data is L pixel clocks after the end ofhorizontal blanking, then aLeftMargin should be loaded with B+L3231 =B+L63, independent of resolution.  Since L may be 0, this implies that thehorizontal blanking time for the monitor must be greater than 63 pixel clocks.Since high-speed monitors typically have greater than 4 ms horizontal blankingtimes, and are this fast only with high speed pixel clocks, this restriction is notexpected to be significant.������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"
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z����·T=ðY·\����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisplay Controller14 September 1981114Note: For a monitor connected via the 7-wire interface, aLeftMargin must be B+L68,rather than B+L63, because video signals are delayed from horizontal control waveformsby 5 pixel clocks.Note: The value loaded into aLeftMargin must actually be the negative of the left margincount computed above.aWidth.  A 12-bit counter that counts at the pixel clock rate as soon as thechannel turns on; when the counter runs out (or when horizontal retrace starts,whichever is earliest), the channel is turned off.  Precisely, if the channel is to runfor W pixel clocks, the width counter must be loaded with (W+255).aFifoAddr.  An 8-bit quantity pointing to the munch and word within the munch forthe first FIFO read for the next scan line; this must be an even number becausedoublewords are fetched from the FIFO.  Firmware must keep track of the numberof used munches for any given line and advance aFifoAddr by exactly the rightamount, adjusting for munch boundaries, interlacing, and data breakage.  TheCLCB register for aFifoAddr is the channel read pointer itself.MixerModes.  A set of bits that control the mixer; these are not channel-specific.These will normally be changed infrequently, maybe at the field rate or duringdisplay initialization.  However, they are in the NLCB to allow modes to change onthe fly.Vertical Control Word (VCW).  A word controlling the vertical retrace operation ofthe monitor; it contains the vertical blank bit, vertical sync bit, and interlace fieldbit discussed in the "Vertical Waveform Generator" section below.Cursor and CursorX.  The 12-bit CursorX value is loaded into a counter whichstarts counting at the end of HWindow.  When the counter runs out, the 16-bitCursor value is shifted out onto the CursorVideo line.  This is used by the Altovideo interface and in the MiniMixer address.  Precisely, if horizontal blanking is Bpixels in duration, and the leftmost bit of the cursor is to appear X pixels beyondthe end of horizontal blanking, then the CursorX register must be loaded with(B+X+226), or (B+X+221) when using the 7-wire interface.Horizontal Waveform GeneratorThe 1024-word x 3-bit HRam contains control information for these waveforms.  Undernormal operation, HRam is addressed by a 12-bit counter (HRamAddr[0:11]) which is resetat the leading edge of horizontal sync and then increments every pixel clock until the nextleading edge of horizontal sync; HRamAddr[1:10] address the RAM, and the output isloaded into the HRamOut register every other pixel clock.  The three bits in HRamOutcontrol horizontal sync, horizontal blank, and half-line; these three bits are combined andlevel shifted by a logic network appropriate for the monitor being driven.The 1024-word HRam imposes the uninteresting restriction that there be fewer than 2048 pixels/scanline.As shown in the diagram at the top of Figure 14, horizontal blanking (HBlank) is true fromthe end of one scan line to the beginning of the next.  During horizontal blanking, HSync isturned on to initiate the horizontal retrace and turned off again when horizontal retrace is��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"
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u�tu�tî·ïTyqî·ïQpô�ºðOô�»î·ïO=ô�‹ô�ŒðJî·ïMOô�§ô�¨ð7ïMÜ�ïMOî·ïK„î·ïHô�£ð3ô�¤ð"î·ïFHô�ƒð<ô�„î·ïD}ô�™ðFô�šî·ïB²î·ï?Aô�˜qpqpô�™�qpî·ï=vô�ð/ô�‘ð*î·ï;«ô�’ð?ô�“î·ï9áô�®ô�¯ð;î·ï8ô�ðHî·ï2ýsî·ï/‹pô�”ð#ô�•ð4î·ï-Àô�£ðRô�¤î·ï+öô�Éô�Êð@î·ï*+ô�™ð8ô�šð$î·ï(`ô�ðGî·ï$îô�¬ð(ô�­ð-î·ï#$ô�ðBô�Žî·ï!Yô�ðPô�î·ïô�«ô�¬ðLî·ïÄô�ªð$ô�«ð5î·ïùô�ð2ÿ�������	¶����·²<ðLY������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisplay Controller14 September 1981116Seven-Wire Video InterfaceSo that a number of different controller and terminal types may be freely interconnected inDolphin and Dorado-based systems, a common interface between terminals and controllershas been defined.  This interface assumes that a terminal contains a raster-scanned bitmapdisplay and one or more low bandwidth input devices (keyboard, pointing device, etc.)  TheDDC transmits digital video and sync to the terminal over six pairs of a seven-pair cable.The input data is encoded by a microcomputer in the terminal and sent back serially overthe seventh pair (the "back channel").  Video and control (sync) are time-multiplexed, andfour bits are transmitted in parallel to reduce the cable bandwidth required.While the description in the following sections assumes a display having one bit/pixel, thebasic signalling mechanism may be extended to support gray-level or color displays.Video OutputThe four output lines are interpreted as either a 4-bit nibble of video or four control signalsaccording to the phases of the two clock signals; the DDC places data on the data lines atthe falling edge of ClkA, and the terminal samples this data on the rising edge of ClkA.  IfClkB is 1 at this time, the nibble is interpreted as four bits of video, else as sync andcontrol information.  ClkA and ClkB are transmitted in quadrature so that the terminal canreconstitute a clock at the video bit rate.When a nibble is interpreted as control information, bit 2 is reserved for horizontal syncand bit 3 for vertical sync, while 0:1 are undefined; different types of terminals may use 0:1for any purpose.A circuit on the DispY board drives the seven-wire interface from the MiniMixer.MinMixer[0] is serial-to-parallel converted into four-bit nibbles, which are held in a registerfor transmission.  Sync, blank, and clock phases are generated in accordance with theseven-wire interface specification.Back ChannelData from low bandwidth input devices at the terminal are transmitted serially over the backchannel.  Data are clocked by the terminal on the rising edge of the horizontal blank pulseand are sampled by DHT during the subsequent scan line after HWindow.By convention the terminal microcomputer encodes 32-bit messages (delivered in 32 scanlines); each message begins with a 1, and after the 32nd bit of the message the DHTignores the backchannel until the start of another message is indicated by another 1.  Themessage consists of a start bit, 3 unused bits, a 4-bit message type, a 16-bit message body,and finally an 8-bit trailer which must be 2008.The terminal microcomputer perpetually cycles through all possible keys on the keyboard(as well as mouse buttons and keyset paddles), detecting changes in state of the keys; thestate of the keyboard then exists in seven 16-bit words, and a back channel message isdefined for each.  Whenever one of these words changes value, it is sent to the Dorado ina message.  Additionally, changes in mouse x,y coordinates are reported once per field(i.e., twice/frame or typically 60 times/sec).  If the mouse has not changed position duringÿ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"
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3ô�ô�ð=�������Z����·	ì=ð^0��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisplay Controller14 September 1981117a field, then one keyboard word is reported instead of the mouse position change; thus, thecorrect state of the keyboard is eventually reported even if transitions are missed.Table 24: Terminal Microcomputer MessagesMessageTypeComments00BIllegalignored01BKeyboard word 0 (corresponds to Alto memory location 1077034B)02BKeyboard word 1 (Alto 177035B)03BKeyboard word 2 (Alto 177036B)04BKeyboard word 3 (Alto 177037B)05BMouse buttons and keyset (Alto 177033B)06B8-bit changes in X-coordinate (0:7 of the message body) and Y-coordinate (8:15 of themessage body), represented in excess-200B notation07BIllegalignored10BKeyboard word 4 (Star keyboards only; no Alto analogue)11BKeyboard word 5 (Star)12B16BIllegalignored17BBoot message.  Actually, depressing the boot button jams the data to one continuously,rather than generating a valid terminal message.  Furthermore, when the boot button islet up, there may be as many as 8 bits of garbage following the last consecutive onebit; these must be ignored by the firmware.  The firmware should also ignore bootbutton pushes less than 10 ms in duration, as these may be caused by noise or contactbounce.Processor Task ManagementThis section outlines the implementation requirements of DHT and DWT and discusses thehardware associated with task wakeups and DWT subtask arbitration between the twochannels.Since DHT must do a lot of processing, it runs at low priority and is awakened once/scanline at the end of HWindow.  When it runs, it must calculate all parameters for the nextscan line (i.e., the one after the scan line that is just starting), load the NLCB appropriatelyfor each channel, and set up the munch address and count for each channel in the RMregisters aNextAddr and aNextCount referred to in the DWT sample code below; then itsets the aNextWCBFlag flags discussed below.  The DHT wakeup will remain active untilany NLCB output command is executed, so the DHT must execute at least one NLCBoutput command every time it wakes up, and this must occur at least three instructionsprior to blocking.DWT is a very high priority task which may run on behalf of either channel:  channel A issubtask 0; channel B, subtask 2.  Since it uses the subtask mechanism, DWT must alwaysblock at the same instruction each iteration.  DWT does not explicitly know the channel forwhich it is executing at any given time; its two parameters, a start address and munchcount, are received from DHT in RM registers specific to the subtask.  In the normal case,DWT initates an IOFetch and blocks.  The following is the main-line DWT microcodepresently in use:����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"
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<ðZô?��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisplay Controller14 September 1981118%RM registers for channel A, indicated by names beginning with "A" below, are used in the program, but thecorresponding set of registers for channel B, in a different RM region, will be referenced when SubTask is 2.Note that TIOA selects the DWTFlag register and T contains 20 at the beginning of the loop, so the secondinstruction is used both to increment the munch address and to signal the hardware that an IOFetch iscommencing.%DWTStart:ACount_(ACount)T, Branch[DWTCheck, R<0];AAddress_(IOFetch_AAddress)+(Output_T), Block, Branch[DWTStart];%AAddress will be even if we just exhausted a scan line.  AAddress will be odd if we have just been awakened tostart a new scan line.  In either case, isolate flag in AAddress[15] for use in adjusting the WCB flags.%DWTCheck:AAddress_ (AAddress) AND (1C), Branch[DWTAdjustWCBFlags, R even];%Note that the change-RSTK-for write function used below is ok, but the change-RBase-for-write functions areillegal because of subtasking.%DWTRefill:ACount_ANextCount;*from DHT, # munches to fetch -1 in 0:11BrLo_ANextAddrLo;*first munch addressBrHi_ANextAddrHi;%Now adjust WCB flags, as follows: If we just exhausted a scan line, AAddress=0 now; execute Output_0 toclear the CurWCB flag, and set AAddress to 1 for the next wakeup.  If we are starting a new scan line,AAddress=1 now; execute Output_1 to set the CurWCB flag and clear the NextWCB flag, and set AAddress to 0for the first IOFetch.%DWTAdjustWCBFlags:AAddress_ (AAddress)1, Output_AAddress, Block, Branch[DWTStart];DWT lowers its wakeup request at the onset of the DWTStart instruction, and the DDCremembers that DWT is in progress.  No further DWT wakeups will be generated while thetask is running or is preempted by a higher priority task.  Whenever DWT blocks, a counteris initialized to a constant value N and counts once per Dorado cycle; when the counterruns out, DWT wakeups are allowed again.  This counter has two purposes.  First, within amunch loop it spaces out IOFetch references to the memory system by 8 or more cycles(depending upon N, which is adjustable through a hardware SIP component), so as not toclog the memory pipeline.  Second, the decision to generate subsequent DWT wakeups isbased upon the state of flags that may be altered by output commands; these commandstake time to get from the processor to the DDC and alter the state.  Other tasks may havethe processor while these state changes take effect.After N cycles have elapsed, DWT will be woken whenever aWantsDWT is true for one ofthe channels.  Two channel-specific flags are involved in DWT wakeup control:aCurrentWCBFlag is true when a is actively moving words into the FIFO; aNextWCBFlag isset true by DHT after it has loaded the munch address and munch count into DWTnextaddrand DWTnextcount for a.  After fetching the last munch for a scan line, DWT clearsaCurrentWCBFlag and blocks unless aNextWCBFlag is true.  In other words, aWantsDWTwhen(aNextWCBFlag & not aCurrentWCBFlag) %(aCurrentWCBFlag & aFifoAvailable).If only AWantsDWT or only BWantsDWT, no conflict arises and the requesting channel getsDWT.  However, if both channels want DWT, the channel that ran least recently will runnext.ÿ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"
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:<ðZÑ7������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisplay Controller14 September 1981119Two observations must be made about the DWT microcode.  First, because the finalinstruction is normally an IOFetch_, the next instruction executed (by another task) will beheld one cycle if it initiates any memory reference.  Secondly, the two instruction loopabove requires that the hardware cope with the NextLies condition discussed in the "SlowIO" chapter; a pathological lockout problem could occur if a high demand task of higherpriority is coded so that it always creates NextLies (say, by doing Block and immediate_Md in the instruction after a fetch).  This would result in the DWT wakeup beingfrequently delayed by 2 cycles.Note:  Neither DWT nor DHT drives the IOAtten branch condition.Slow IO InterfaceDDC manages all control functions via the slow io system.  At this point you should studyFigure 15, which shows the format of the various output and input commands; there are sixoutput devices and one input device on the DispY board, and eight output devices and oneinput device on the DispM board (if present).  Output commands are handled uniformly:TIOA is clocked into a register at t1; the register output is decoded and identified as one ofthe DDC commands; if the processor is doing an Output_B, then at t3 IOB data from theprocessor is clocked into a register and one of the "TIOA command" pulses occurs from t3to t5, at which point the desired action is complete.The IOB data received at t3 of an Output_B will remain in the DDC buffer register (RIOB)until the next output command.  This is useful for debugging and for muffler readout of theNLCB (because an NLCB address can be loaded into RIOB for multiple cycles).The HRam, MiniMixer, Mixer, BMap, and CMap are RAMs that will generally be loadedduring system initialization and not often changed while pictures are being displayed.  Theprogrammable pixel clock will also be loaded during initialization, if it is being used insteadof the fixed crystal oscillator.The HRam, Mixer (AMap), BMap, and CMap addresses each have two independentsources: the Dorado slow io system and the video system.  Video system addressing isdisabled during loading from the Dorado.  The output commands to each of these RAMsare interpreted as follows:  The Keep' bit is saved in a flipflop loaded by every RAM outputcommand; as long as Keep' is true (i.e., low), video system addressing is off.  If LoadAddris true, then IOB[4:15] are loaded into the RAM address register.  If Write' is true (i.e., low),the currently-addressed word of the RAM is written from the data field; additionally, theRAM address register increments after writing, so the RAM can be loaded sequentially athigh speed.  A RAM output command with Keep' false (i.e., high) releases the RAM fromDorado control and returns it to the video system.Note: the LoadAddress and Write' bits of a RAM output command take effect only if the Keep'flipflop is already true (i.e., set to zero by a previous RAM output command).Note: in the case of the Mixer, the RAM address is loaded from IOB[4:14] and a Hi/Lo Select bit isloaded from IOB[15].  The latter bit determines which 12 bits of the 24-bit wide mixer word will beloaded by the next Write'.  The Hi/Lo Select bit behaves as a low-order extension of the Mixeraddress counter, so successive Write' commands will alternate between the halves of one mixer wordbefore advancing to the next.ÿ����������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"
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Z����·›<ðYpu��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisplay Controller14 September 1981121A single input device called Status is implemented.  It is used to return the currentlyselected muffler bit and the seven-wire interface received data bit.The MapInLo and MapInHi input devices read the current values output from the colormaps (Mixer, BMap, and CMap, whichever are active).  When the color maps are controlledby the video system, these outputs change too rapidly for reading them to be useful (unlessthe DDC is being single-stepped by means of UseFakePixelClk).  However, when the colormaps are controlled by the Dorado, this input device can be used to read out the colormap entries addressed by their respective RAM address registers.MapInHi[0] is the 7-wire terminal input bit for the independent terminal interface on DispM;its position corresponds to Status[0] on DispY (see below).  MapInHi[1] is a constant 1 if aDispM board is installed; if DispM is not installed, an Input from the nonexistent registeryields a zero value.  This enables firmware to detect the presence or absence of a DispMboard.  MapInLo[0:3] are a 4-bit color monitor type jumpered on the Dorado backpanel.Note: the MapInLo and MapInHi input devices do not generate IOB parity, so they must be read bythe Pd_InputNoPE function to disable parity checking.DispM Terminal InterfaceThe independent terminal interface on the DispM board functions much the same as asingle-channel DispY board, but is specialized to driving a binary monitor via a 7-wireinterface.  The data path is one bit/pixel; the resolution is full; there is no MiniMixer; andthe horizontal waveforms are fixed by a PRom (which must be changed when a differenttype of 7-wire terminal is installed).Aside from these limitations, the DispM terminal interface operates almost identically to theA channel of DispY.  In particular, the io addresses are grouped parallel to the ones onDispY, and the data formats are identical; so a microprogram can initialize TIOA to thecorrect group and subsequently use the function that changes only TIOA[5:7] to selectregisters within that group.  This enables practically all the microcode for driving a 7-wireterminal to be shared between DispY and DispM.In Figure 15, the DispY io operations that are also defined for DispM are marked with anasterisk.  Note that outputs to unused NLCB addresses are ignored.Due to hardware differences between DispY and DispM, the ALeftMargin and CursorXvalues must be computed slightly differently.  For DispM driving the 7-wire interface,ALeftMargin = (B+L130) and CursorX = (B+X+190).Note: DispM does not have a muffler system.  In particular, the MonitorType muffler value is alwaysread from DispY.  By convention, this refers to the type of 7-wire terminal attached to the Dorado,whether that terminal is connected to DispY or to DispM.  Also by convention, the 7-wire terminal isalways connected to DispM if DispM is installed.ÿ��������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"
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î·ï0ìô�ŒðZî·ï/!ô�àð?ô�áî·ï-Vô�ŠðDô�‹î·ï+Œô�î·ï(ô�»ðUî·ï&Oô�ð;îxï#j�î:ô�žðAô�Ÿî:ï!Ãô�¸ð=ô�¹î:ï ô�ð(îxï7�î:îxïRî:ô�ûð7ô�üî:ï«îxïÆî:ô�îxïáî:ô�Žô�ð-î:ï:ô�îxïU�î:ô�ð8ô�žî:ï®ô�ð"v�p�������	����·g<ð[¤/����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualDisplay Controller14 September 1981123MMunches/scan line that the fast io system can deliver.The time required to fill the FIFO for both channels is a little longer than 30*8+20 cycles(= 276 cycles) or about 13.8 ms at a Dorado clock period of 25 ns; this follows from thefact that there are 15 munches/channel or a total of 30 munches of FIFO storage, and thefast io system can deliver one munch per 8 cycles with the first munch arriving 20 cyclesafter the first IOFetch_.  13.8 ms is much smaller than the vertical blanking time and longerthan the horizontal blanking time, so the FIFO will start out full at the beginning of a fieldand will be actively refilling itself during HS+HB of each scan line.  If the memory systemkeeps up with the demands of the video channels, then the FIFO will tend to refill itselfafter momentary transients in which it empties out a little.Consequently, we know that HS+HB = 1/(S*F)  2*VR, and that M = (HS+HB)/T lesscorrections for refresh references, storage references by other tasks, hold, and delays fortasks of higher priority than DWT.  At F = 30 frames/sec, VR = 800 ms, and S = 1000scan lines, we get HS+HB = 31.7 ms and M = 31.7/0.4 = 79 munches less corrections.There will be an average of two refresh references/scan line, so we get an upper bound of77 munches = 19,712 bits/scan line from storage.However, the DWT will not get all storage bandwidth.  The DWT wakeup spacing iscontrolled by a SIP; the smallest reasonable spacing would result in one IOFetch every 8cyclescloser spacing would result in hold while a preceding IOFetch completed, so moreprocessor cycles would be consumed without improving data rate.  At this tightest spacing,DWT runs for 2 cycles out of every 8.  Conceivably, worst case memory activity discussedin the "Fast IO" chapter could occur during these 6 cycles (a clean miss 3 cycles beforethe IOFetch, followed by a dirty miss 2 cycles before the IOFetch, each by a different task).However, the large amount of storage in the FIFO allows us to rely upon statistics toaverage out memory competition, so it is probably reasonable to allow DWT at least 80% ofstorage bandwidth or about 16,000 bits/scan line in the above example, which wouldaccommodate 1000 line x 1000 pixels/line x 16 bits/pixel.  For HB = 5 ms this is equivalentto a pixel clock period of 26.7 ns.This is only one speed limitation.  Since the 32-bit wide FIFO is accessed once/cyclealternately by the A and B channels (i.e., 16 bits/cycle/channel), and since exactly threedoublewords are fetched before the horizontal scan begins for each channel, the maximumbits/scan line for each channel is about (3*32 bits)+[(26.7 ns/pixel)*(16 bits/50 ns)*(1000pixels/line)] = 8640 bits/scan line.  This means that unless both channels are running atthe same data rate, the data rate will be significantly below the upper bound determinedabove.  For example, in 24Bit mode, if the A channel runs at full resolution and gets 8640bits/scan line, the B channel will run at half resolution and get only 4320 bits/scan line, sothe maximum data rate would be about 1000 lines x 538 pixels/line x 24 bits/pixel.����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î"
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v�pð1î·ïE»ô�ˆðPô�‰î·ïCðô�ð0î·ï@~ô�éð5ô�êî·ï>³ô�¥ô�¦ðDî·ï<ét�pô�–ô�—ð2î·ï;ô�‰ðQô�Šî·ï9Tô�–ð3ô�—ð%î·ï7‰ô�žô�ŸðHî·ï5¾ô�ˆðLô�‰î·ï3ôô�Óô�ÔðIî·ï2)ô�†
ô�‡ðNî·ï0_ô�Þô�ßð>î·ï.”ô�€ô�ð/v�pî·ï,Éô�ð#î·ï)Wô�Ðð>ô�Ñî·ï'ô�©ðBô�ªî·ï%Âô�‰ð-ô�Šð*î·ï#øô�ðQô�Ž	î·ï"-ô�žðYî·ï bô�¬ô�­ðKî·ï˜ô�–ô�—ðFî·ïÍô�ˆðUô�‰î·ïô�ëð5ô�ì�������X����·»=ðMP2����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualEthernet Controller14 September 1981124Ethernet ControllerAn Ethernet is the principal means of communication between a Dorado and the outsideworld.  An Ethernet is a broadcast multi-access packet switched network which canconnect up to 256 stations separated by as much as 1 kilometer with a 3 mHz channel.The 'Ether' is a passive coaxial cable to which each station is connected through atransceiver that is high-impedance when receiving, low impedance when driving.Readers unfamiliar with the general concepts behind the Ethernet should refer to"Ethernet: Distributed Packet Switching for Local Computer Networks," by R. M. Metcalfeand D. R. Boggs, CACM, 19(7):395-404, July 1976; or to Design and Performance of LocalComputer Networks, by John Shoch, published by University Microfilms, August 1979.Read this chapter with Figure 16 in view.Ethernet PacketsEthernet data are encoded in packets.  Packets are preceded by a low signal (i.e., silence)on the Ether; they begin with a one-bit prefixed by the transmitter, called the start bit.  Bitsin the packet are phase encoded, where the bit cell time is nominally 340 ns; phaseencoded signals have one data transition per bit cell and its direction (low-to-high = 1) isthe value of the bit.  Midway between these there may be a setup transition, so that thenext data transition can be in the correct direction.Packets end when no transitions are detected for more than 1.5 bit times and the Ether islow.  Collisions are transmissions that overlap in time and cause malformed andundecodable bits.  Transmitters jam the Ether with a continuous high for several bit timesafter participating in a collision.  Collisions are of four types: too many transitions, in whichtwo transitions occur within .25 bit times; too few transitions, in which a transition occursbetween 1.25 and 1.5 bit times after the last one; end-of-packet (EOP), in which notransitions occur for more than 1.5 bit times and the Ether is low; and jam, which is thesame as EOP except that the Ether is high.In a well-formed packet that does not experience a collision, the start bit is immediatelyfollowed by an 8-bit destination host number, then an 8-bit source host number.  This isfollowed by an indefinite number of 16-bit data words, a 16-bit checksum, and finallysilence.Even when transmitted without a source-detected collision, a packet may fail to reach itsdestination; packets are delivered only with high probability.  Stations requiring a lowerresidual error rate must follow mutually agreed upon communication protocols.When the sender of a packet detects a collision, some method is needed to arbitrate(without communication) its use of the Ether with other stations contending for it.  Thealgorithm used on the Ethernet, called the 'binary exponential backoff collision algorithm,'is discussed in the above references.  It involves waiting a random interval and thenreattempting transmission.  The (ideal) distribution of the random intervals depends uponmany factors.������������������������������������������������î·ïfªpô�€î",qî3Špô�îFMïfñî·ïa×rî·ï^epô�­ð3ô�®ð!î·ï\›ô�òðQî·ïZÐô�°ð$ô�±ð0î·ïYô�æð<ô�çî·ïW;ô�ðNî·ïSÉô$ðPî·ïQþô�¥ðWî·ïP4ô�–î¯ïOÝþ�ïP4ð"î1uïOÝþm�ïP4�î6xïOÝþh�ïP4�î9vïOÝþ@�ïP4
�îBLïOÝþ?�ïP4ô�—�îD"ïOÝþ†�ïP4î·ïNþQ�ïNiô�é�îñïNþù�ïNið4ô�êîòïJ÷qô�Xð)î·ïEÞsô�î·ïBlpô�Žqpô�î·ï@¡ô�‹ô�Œð>qpî·ï>×ô�Üqpð4î·ï=ô�˜qpô�™ð,î·ï;Aô�¬ð;qpô�­î·ï9wô�ð5î·ï6ô�–ð0ô�—ð)î·ï4:ô(q	pð;ô)î·ï2pô�œqpð!ô�î·ï0¥ô�‰ðCqpô�Šî·ï.Úô�¡ð,qpô�¢î·ï-ô�êô�ëð'qpî·ï+Eô�«ð;ô�¬qpî·ï){ô�ð*î·ï&	ô�¶ð=ô�·î·ï$>ô�­ðUô�®î·ï"sô�ßð6ô�àî·ï ©î·ï7ô�ªðUô�«î·ïlô�Åqð1pô�Æî·ï¢ô�ðMî·ï0ô�Öð%ô�×ð.î·ïeô�¿ð"ô�Àð6î·ï›ô� ðPô�¡î·ïÐô�Ýð&ô�Þð/î·ïô�®ðYî·ï
;ô��������Ð����·ô=ð[x��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualEthernet Controller14 September 1981125RemarksFrom the method of collision detection, it follows that in a noise free Ether with ideal transmitters andreceivers, a bit cell time between 0.75*T and 1.25*T, where T is the nominal bit cell time (340 ns), can bedecoded correctly.Phase encoding has the undesirable property that only 50% of the transmission medium's theoretical bandwidthis utilized.  A number of reasonably simple encodings are known that more nearly approach the theoreticallimit, though phase encoding is simple to implement.  If at some time we were willing to abandon compatibilitywith the existing Ethernet, we should reconsider the use of phase encoding.A promising alternative to phase encoding is bit-stuffing, which averages 67%, 86%, or 93% of theoreticalbandwidth for 0th, 1st, and 2nd order codes.  This encoding outputs data bits in a cell time equal to 1/2 ofthe phase-encoded cell time; when 1 (0th order), 2 (1st order), or 3 (2nd order) data bits have been outputwithout a transition, then a non-data transition is inserted into the bit stream.  The 1st order encoding (86%)could be implemented with a few changes to the current controller.Controller OverviewThe Ethernet controller is a slow IO device packaged with the disk controller on the DskEthlogic board.  These two devices require more edge pins than are available in an MSA-IOslot, so the board must be mounted in a Fast IO slot (see Figure 2).It would be possible to package two Ethernet controllers on one logic board using different task andTIOA assignments for each.  This might be appropriate if Dorados are ever used as Ethernetgateways.A cable connects the controller to a transceiver outside the Dorado enclosure; thistransceiver is almost identical to the ones used for Altos and other computers, thedifference being that it uses +12 volts rather than +15.  Dorado transceivers are paintedbright red and have large block lettering saying "Dorado only".  Plugging in the wrong typeof transceiver will not damage anything; it just won't work.  The cable between thecontroller and the transceiver contains twisted-pair signals for receiver data, transmitterdata, collision, +5 v, and +12 v.The controller has independent transmitter and receiver sections.  Because these twosections are completely independent, the Dorado can receive its own transmissions.  Thisis an important aid in hardware and software debugging and simplifies the device driver,which need not check for sending to itself.  Furthermore, the receiver can receiveconsecutive packets separated by the minimum inter-packet spacing (510 ns).  This meansthat the Dorado can receive, without loss, streams of packets directed to it by mulitplehosts and packets that immediately follow broadcasts.  This capability is important forservers and other high-performance applications.The controller uses two tasks, one for the transmitter (EOT for Ethernet Output Task) andone for the receiver (EIT for Ethernet Input Task).  The receiver task is higher priority.  Topermit two instruction/wakeup loops, a wakeup request is removed whenever the Next bussays the task is about to run.  This simple strategy can be fooled into removing a requestwhen NextLies occurs, but this is harmless since the required service rate is low.  To avoida spurious wakeup, a wakeup is not requested again until after the task has blocked.  Adebugging control bit can be set which prevents wakeups even when all other conditionsare satisfied.ÿ������������������������������������������������������������������������������������î·ïfªpô�€î",qî3Špô�îFMïfñî·ïbAtî·ï_£uô�Ñðeô�Òî·ï^Bô�¤ð-ô�¥ð>î·ï\áô�î·ïZCô�†ð9ô�‡ð3î·ïXâô�«ðYô�¬î·ïWô�Šð&ô�‹ðHî·ïV!ô�ðKî·ïS‚ô�¾ðiî·ïR"ô�˜ð;ô�™ð1î·ïPÁô�¡ð0ô�¢ð;î·ïO`ô�šðEô�›ð*î·ïMÿô�ðBî·ïI	sî·ïE—pô�„ð[î·ïCÍô�§ðIô�¨î·ïBô�ðDîxï?Auô�ˆðKô�‰îxï=àô�Ðô�ÑðJîxï<î·ï90pô�þô�ÿq
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ô�Ãð$ô�Äð4î·ï ?ô�×ð6ô�Øð!î·ïtô�ð0î·ïô�›ð&ô�œî6ï«þ�ç�ï�î< ï«þ�ï�îAï«þ�Ü�ï�î·ï8ô�’îÝïáþ�ç�ï8�î$äïáþ�c�ï8�î(ºïáþ�Ü�ï8�ô�“î·ïmô�ðRô�î·ï£ô�™ð8ô�šð"î·ïØô�ˆðRô�‰	î·ï
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¬����·1<ðYÚ~��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualEthernet Controller14 September 1981126The transmitter and receiver each have 16-word x 20-bit Fifos.  The bits are 16 data + 2parity + 2 spare (the receiver uses one of the spare bits).  Each Fifo has read and writepointers, multiplexed into the address inputs of the storage chips, to select the nextlocation to be read or written; these pointers are zeroed by IOReset.  A Fifo is empty whenthe pointers are equal and full when (WritePtr+1) mod 16 equals ReadPtr.  There are busregisters between the Fifos and IOB.  Service requests from the Ether side of a Fifo aregiven priority.  The Fifos are synchronous to t1.The basic clock for transmitting and receiving data from the Ether, called EtherClk,originates from a 23.5 MHz crystal oscillator (i.e., the period is 42.5 ns or 1/8 of the 340 nsbit cell time).  The memory system's Pendulum clock (period 16 ms) is also used to timeretransmissions after a collision, as discussed later.The receiver runs continually; its phase decoder (PD) samples the Ether every EtherClk; afinite state machine (FSM) driven by the samples detects the presence or absence ofpackets on the Ether, zero/one transitions, and collisions.  Another FSM accumulates thestatus of the packet and controls a shift register that assembles 16-bit words from theincoming data.  Words in the shift register are written into the receiver's Fifo together withodd parity on each byte; the status is written into the Fifo after the last word of eachpacket and marked to distinguish it from data words.  This allows the receiver to handleback-to-back packets; firmware decides what to do with each packet as it is read from theFifo.  EtherClk is used for receiver stages through the shift register; data in the shiftregister is synchronized to the Dorado system clock as it is written into the Fifo.When the transmitter is turned on, it attempts to send one packet and then must berestarted by firmware.  The EOT fills the Fifo; the transmitter FSM loads the shift registerfrom the Fifo and supplies a serial bit stream to the phase encoder (PE).  Transmitter statusis read directly from the controller status registers (unlike receiver status, which travelsthrough the data path).  Data is synchronized to EtherClk between the output of the shiftregister and the input of the PE.  A collision may be detected by either the transceiver orthe PD.  The occurrence of  a collision is captured, synchronized, and used to abort theoutgoing packet after jamming the Ether briefly.The controller has a number of features to help debugging.  All of the interesting internalstate is available via the IOB and the muffler system.  The transceiver can be disconnectedand PE output internally connected to PD input under firmware control.  Task wakeups canbe disabled permitting the controller to be driven entirely from emulator-level software.  Theinternal clock can be single-stepped.  These features permit the construction of asimulation program which compares its predictions with what the controller is actuallydoing.����������������������î·ïfªpô�€î",qî3Špô�îFMïfñî·ïbô�ŸðLô� î·ï`Sô�¡ð<ô�¢î·ï^‰ô�êð0ô�ëð&î·ï\¾ô�‹ðPô�Œ
î·ïZóô�–ð?ô�—qî·ïY)pô�®ô�¯ð3î·ïW^ô�ð/ïVÑu�ïW^p�î·ïTô�ýðKqp�î·ïREô�‡ð\ô�ˆî·ïPzô�§ô�¨	qpð*î·ïN°ô�ð6î·ïK>ô�œð#qô�pð$î·ïIsô�Úð<ô�Ûî·ïG¨ô�¡ð<ô�¢î·ïEÞô�Éô�ÊðNî·ïDô�‘
ô�’ðPî·ïBIô�Ç	ô�ÈðNî·ï@~ô�¬ð:ô�­î·ï>³ô�’ð.ô�“ð+î·ï<éô�Ùô�ÚðGî·ï;ô�ðSî·ï7¬ô�ÜðRî·ï5âô�¦ð/ô�§ð-î·ï4ô�‚ð#ô�ƒqpî·ï2Lô�ÅðTô�Æî·ï0‚ô�£ð-ô�¤ð,î·ï.·ô�›ô�œðOî·ï,íô�¥ô�¦ð>î·ï+"ô�ð0î·ï'°ô�žð:ô�Ÿð!î·ï%åô�Šð"ô�‹ð9î·ï$ô�‡ðLô�ˆî·ï"Pô�ƒðYô�„î·ï †ôð@ôî·ï»ô�ÝðVî·ïðÿ�������ê����·©<ðKb+������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualEthernet Controller14 September 1981127ReceiverMost of the receiver runs continuously, tracking traffic on the Ether.  The PD reports whatit sees to the receiver FSM, which assembles packets in the shift register and buffers themin the Fifo.  As words emerge from the Fifo into the bus register, they are either discardedor generate a wakeup request under control of the wakeup logic.  Following the last dataword of each packet as it travels through the Fifo are the CRC word and a status word.IOAtten branches when a status word is present in the receiver bus register.  Data andstatus are synchronized to the Dorado clock between the output of the shift register andthe input of the Fifo.The peculiar placement of status bits  in Figure 16 eases emulation of the Alto Ethernet controller.The PD is a FSM which takes in raw phase-encoded serial data and produces phasedecoder events and carrier.  Phase decoder events are 'saw a zero bit', 'saw a one bit',and 'saw a malformed bit'.  Carrier indicates that the PD is seeing transitions on the Ether(i.e. the Ether is in use).  Since the PD is completely digital, it can be single-stepped fordebugging.  Receiver collision detection, a by-product of this decoding technique, works aswell as transceiver collision detection.The receiver control is another FSM that takes in PD output and produces control andstatus signals.  RxSRCtrl controls the shift register and the bit counter.  The bit counterdecrements when a data bit is shifted into the shift register and resets to -1 when thestatus is parallel loaded into the shift register.  RxSRFull' is low when the next shift willmake the register full.  RxEOP travels in parallel with each Fifo word and is true if the wordis an ending status word.  This bit is called EthData.18 when it is in the bus register whereit can be tested with IOAtten.Writing data or status from the shift register into the Fifo has priority over loading the busregister from the Fifo.  Byte parity is computed at the shift register output and travels withthe data through the Fifo and the bus register, down IOB and into the processor where it ischecked.The optimum point at which to synchronize received data with the Dorado clock systemwould be at the input to the PD, where there is only one signal to synchronize, except thatthis would make proper operation of the PD depend upon the Dorado clock period.  Thenext best sync point is the PD output where the number of signals has only grown to three.The problem here is that the PD can produce events faster than they can be synchronizedto the Dorado clock without buffering.  Consequently, synchronization takes place after theshift register where the number of signals exceeds 20.  This is not as unfortunate as itseems because status and data use the same paths and can share a single synchronizer,RxSRDump, which produces RxFifoWE' each time RxFSM pulses RxSync'.  This leaves onlyRxCollision and PDCarrier which must be synchronized for the transmitter.  RxCollisionshares a synchronizer with XcCollision, and PDCarrier's is a simple level synchronizer.A receiver data-late occurs when the receiver FSM requests a Fifo write and the Fifo is full.In this case the write does not happen and the data is lost.  RxDataLate is cleared after anend-of-packet status word is successfully written into the Fifo.  This status has the data lateerror bit set so that the EIT is notified that the preceding packet was bad.��������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î",qî3Špô�îFMïfñî·ïbsî·ï^¬pô�”
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¤=ðZgK��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualEthernet Controller14 September 1981128EIT wakeup requests occur when the bus register contains an interesting word (providedthat the EIT is currently blocked, as discussed earlier).  Words are interesting if theyemerge from the Fifo into the bus register while RxOn and RxBOP are true and NoWakeupsis false.  RxBOP is set after the status word for a packet is discarded, so that the next wordout of the Fifo (presumably the first word of the next packet) can generate a wakeup.  It isreset by the EIT to discard the remaining words of a rejected packet (usually because theaddress didn't match).  The receiver may be reset at any time by clearing RxOn.  No morewakeups are generated and every word is discarded as it emerges from the Fifo.  WhenRxOn is next set, the receiver will continue to discard words until it has discarded a statusword.  It will then set RxBOP, and the next word (first word of the first packet after turningon the receiver) will cause a wakeup.TransmitterWhen the transmitter is turned on, it attempts to send one packet and then must berestarted by firmware.  At the request of the wakeup logic, the EOT fills the Fifo usingOutput_B to the bus register.  The transmitter FSM loads the shift register from the Fifoand supplies a serial bit stream to the PE.  Transmitter status is read directly from thecontroller status registers (unlike receiver status, which travels through the data path).Data is synchronized to the Ether clock between shift register output and PE input.EOT wakeups occur when the bus register is empty, TxOn is true, and TxEOP, TxCntDwn,and NoWakeups are false (provided that EOT is blocked, as discussed earlier).  Afterdelivering the last word of a packet, EOT wakeups are disabled by setting TxEOP.  Whilecounting down a collision retransmission interval, firmware can disable wakeups until thenext tick of Pendulum by setting TxCntDwn.  The transmitter may be reset at any time byclearing TxOn, which stops wakeup requests and shuts down the PE within 2 bit times.The binary exponential backoff collision algorithm must be implemented in firmware.  Thecontroller merely provides a way to generate a wakeup on the next rising edge ofPendulum, making the grain size of countdown intervals 16 ms for the Dorado (compared to38 ms for Altos and Novas).  Note that setting TxCntDwn prevents a wakeup; for one toactually occur when Pendulum clears it, the bus register must be empty and TxEOP mustbe false.  Pendulum is considered to be a foreign signal so it is synchronized before beingapplied to the reset input of TxCntDwn.Loading the shift register from the Fifo has priority over writing into the Fifo from the busregister.  Byte parity is computed in the processor and travels with the data down IOB intothe bus register, and through the Fifo to the shift register where it is checked.The transmitter control is a FSM which takes in start, end, and abort signals and producescontrol signals.  TxSRCtrl controls the shift register and bit counter.  The bit counterdecrements when a data bit is shifted into the shift register and resets to -1 when the nextword is parallel loaded into the shift register.  TxSREmpty' is low when the next shift willmake the register empty.  TxData wire-or's the start bit at the beginning of each packet.TxGone clears TxEOP to cause a wakeup at the end of each packet.  The transmitter startswhen the Fifo is full or, if the packet is less than 15 words long, when TxEOP is true.  Thetransmitter ends normally when the Fifo is empty and TxEOP is true.  The transmitter abortswhen a collision, Fifo parity error or data late occurs.  TxAbort can be tested with IOAtten.ÿ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î",qî3Špô�îFMïfñî·ïbô�ªð&ô�«ð0î·ï`Sô�ÛðDô�Üî·ï^‰ô�€ð0ô�ð&î·ï\¾ô�€ð!ô�ð=î·ïZóô�ô�ŽðMî·ïY)ô�™ð=ô�šî·ïW^ô�ð$ô�ð4î·ïU”ô�®ð1ô�¯ð#î·ïSÉô�Žð7ô�ð&î·ïQþô�Œô�ð@î·ïP4ô�ð%î·ïKs
î·ïG¨pô�ÜðRî·ïEÞô�¿ô�ÀðAî·ïDô�­ô�®ðFî·ïBIô�¿ô�ÀðDî·ï@~ô�×ðZî·ï>³ô�òô�óð?î·ï;Aô�”ô�•ð:î·ï9wô�Úð9ô�Ûî·ï7¬ô�¡ð5ô�¢ð"î·ï5âô�®ðYî·ï4ô�Ÿð*ô� ð-î·ï2Lô�ºð@ô�»î·ï.Úô�¢ðFô�£î·ï-ô�ýðMô�þî·ï+Eô�ƒð:v�pî·ï){ô�³v�pð4qpô�´î·ï'°ô�žô�Ÿð9î·ï%åô�Žð;ô�î·ï$ô�ð'î·ï ©ô�žðUô�Ÿî·ïÞô�ð[î·ïô�ðQî·ï¢ô�ô�ð>î·ï×ô�Öð-ô�×ð+î·ïô�ô�ð?î·ïBô�¤ð<ô�¥î·ïwô�­ô�®ðHî·ï­ô�ƒð0ô�„ð(î·ïâô�ð7ô�Žð%î·ï
ô�ðHô�‚î·ïMô�Žð9ô�ð$�������\����·=ð]W��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualEthernet Controller14 September 1981129A transmitter data late occurs when the TxFSM requests a Fifo read and the Fifo is emptybut TxEOP is false.  The PE sends one random bit and then stops.  The resulting packethas an illegal length and probably a bad CRC.The PE inverts and latches TxData at the start of each bit cell and inverts the latched value1/2 bit time later.  TxGo, synchronized to the beginning of a bit cell, enables the PE.  ThePE assumes that a data bit is available long before it is needed and acknowledges each bitafter latching it by generating TxGotBit.A collision may be detected by either the transceiver or PD.  The occurrence of a collisionis captured, synchronized, and used to abort the outgoing packet.  The output of the firststage of the TxCollision synchronizer is wire-or'ed with PD output to jam the Ether after acollision.  The jam lasts for one or two bit times, being the delay through the TxCollisionsynchronizer, TxFSM, and TxGo synchronizer.ClocksThe controller needs a clock with a nominal frequency of eight times the Ether bit rate.The SingleStep control bit selects either the 23.53 mHz crystal oscillator or single Doradoclocks injected under program control.  The clocks for the Ether-synchronous parts of thecontroller are constructed from this basic clock.The slowest Dorado clock period at which the transmitter works is 42.5 ns.  Disabling theDorado system clocks while TxOn is true causes a transmitter data late.  If TxGo is true,the packet is chopped off, causing an incomplete transmission and probably a runt bit.When the clock is reenabled, the PE sends a few fragmentary bits and then the data lateaborts the packet.The slowest Dorado clock period at which the receiver works is 85 ns.  Disabling theDorado system clocks causes a receiver data late.  The next packet that arrives after theclock is reenabled reports the data late.Task WakeupsThe controller is designed for two completely independent tasks, with the receiver higherpriority.  Two IOAs select data and status/control registers.  IOAtten may be tested todecide whether a wakeup request is just for another word or something special (endingstatus for the receiver, or PE aborted for the transmitter).Task wakeups must, on the average, be serviced within 5.44 ms.  The transmitter andreceiver each have 17 words of buffering (bus register + 15 Fifo + shift register) so thevariance can be quite largeaccumulated delay of up to about 90 ms is tolerable, whilelonger delay will cause a data late error.ÿ������������������î·ïfªpô�€î",qî3Špô�îFMïfñî·ïbô�–ð'ô�—ð1î·ï`Sô�¡ðAô�¢î·ï^‰ô�ð-î·ï[ô�„ð!ô�…ð<î·ïYLô�ô�‘ðPî·ïWô�ˆðQô�‰î·ïU·ô�ð)î·ïREô�ð[î·ïPzô�œðMô�î·ïN°ô�šô�›ðCî·ïLåô�¥ô�¦ðBî·ïKô�ð+î·ïFsî·ïBpô�µô�¶ðDî·ï@Åô�Ÿ
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������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualEthernet Controller14 September 1981130Muffler InputAll muffled signals on the DskEth board are accessible to Dorado firmware.  The method bywhich a particular signal is selected and read out is discussed in the "Muffler Input"section of the "Disk Controller" chapter.  Signal addresses 1208 to 1778 for the Ethernetcontroller are enumerated below.  Unless it is obvious, signals which are specific to thereceiver or transmitter have Rx or Tx respectively somewhere in their names.Table 26:  Ethernet Muffler SignalsWord  BitNameMeaningERX0  120PDNew1/8 bit time sample of PD input signal  121PDOldPDNew delayed one sample time122:125PDCnt[0:3]Number of samples since last data transition  126PDCntCtrlIncrements or clears PDCnt  127ReportCollisionsControl register bit that enables PD collision reporting  130RxBOP"Beginning Of Packet" enables receiver data wakeups  131EthData.18Marks status word terminating a packet  132  133RxCRCErrorOutput of receiver CRC checker  134RxDataLateReceiver Fifo overflowed  135RxBusRegFullWord in BusReg can be read with Pd_Input  136RxFifoFullReceiver Fifo is full  137RxFifoEmptyReceiver Fifo is emptyETX140:142TxState[0:2]State of transmitter FSM  143TxEOPTransmitter data wakeups are disabled  144TxBusRegFull'Word is waiting to be written into the transmitter Fifo  145TxGoneTransmitter FSM is shut down  146TxSREmpty'Transmitter shift register is empty  147TxCntDwn'Transmitter wakeups disabled until next pendulum clock  150TxCRCEnblShift/compute control for transmitter CRC  151TxGoEnable PE  152TxDataSerial data input to PE153:154TxSRCtrl[0:1]Transmitter shift register control  155PEOutputPhase Encoder (PE) output  156TxFifoFullTransmitter Fifo is full  157TxFifoEmptyTransmitter Fifo is emptyERX1160:162RxState[0:2]State of receiver FSM  163RxCollisionReceiver-detected collision  164PDCarrierThe Ether is in use165:166PDEvent[0:1]PD output (no event, collision, 0, and 1)  167RxSRFull'Receiver shift register is full  170RxEOPMarks status word terminating a packet  171RxSync'True for one cycle triggering write of SR into Fifo  172RxIncTransReceiver incomplete transmission  173RxCRCResetResets receiver CRC chip  174RxCRCClkClocks receiver CRC ship  175RxDataSerial data output from RxFSM176:177RxSRCtrl[0:1]Receiver shift register control������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î",qî3Špô�îFMïfñî·ïbsî·ï^¬pô�‚ð+ô�ƒð.î·ï\áô�Øô�ÙðDî·ï[ô�¨ð?ïZŠu�ï[pô�©ïZŠu�ï[pî·ïYLô�µð.ô�¶ð+î·ïWô�ðLîÍïS_wô�Fð#îyïPÁtîyïO`ô�€înî"tîyïLÂuîyïKaînî"tô�ð&îyïJ�ô�€înî"tô�îyïHŸîn	î"tð,îyïG?ô�€înî"t	ô�îyïEÞô�€înî"tô�ð1îyïD}ô�€înî"t	ô�ð)îyïCô�€în	î"tô�ð!îyïA¼ô�€în�îyï@[în	î"tô�îyï>úô�€în	î"tô�îyï=™ô�€înî"tô�ð$îyï<8ô�€în	î"tô�îyï:Øô�€în
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����·<ðUø����������������Dorado Hardware ManualEthernet Controller14 September 1981131IOB RegistersTIOA equals 158 selects the IOB registers (called EthD).  The transmitter bus register isloaded by Output_B and the receiver bus register is read with Pd_Input.  At end-of-packet,after the last data word, the receiver delivers first the CRC word and then a status wordcontaining the following bits:RxCollisionReceiver-detected collision occurred (can happen only if ReportCollisions hasbeen set in the control word).RxDataLateReceiver data-late occurredone or more words of the last packet were lost.RxCRCErrorCRC was incorrect in last packet.RxIncTransLast packet did not end on a word boundary.Control RegisterTIOA equals 168 selects either the (write-only) control register (EthC), discussed here, orthe (read-only) status register (also called EthC), discussed in the next section.  The controlregister has three fields: transmitter, receiver, and test.  Bits in a field are decoded only ifthe command-enable bit for the field is true.  Control bits with a single quote as their lastcharacter are true when zero.TxCmdEnbl'enables decoding of transmitter commands.TxOnenables the transmitter.  The transmitter may be reset at any time by clearingthis bit.  Cleared by IOReset.TxEOPdisables transmitter wakeups.  EOT sets this bit after outputing the last word ofa packet.  It is cleared by the controller when the PE shuts down after an abortor normal end.  Cleared by TxOn=0.TxCntDwndisables transmitter wakeups.  Set by EOT to time a retransmission interval aftera collision; cleared by the controller when the next rising edge of Pendulumoccurs (period = 16 ms).  N.B. the binary exponential backoff is done byfirmware.  Cleared by TxOn=0.RxCmdEnbl'enables decoding of receiver commands.RxOnenables the receiver, which may be turned off at any time by clearing this bit.Cleared by IOReset.RxBOP'disables receiver wakeups.  Cleared by EIT to discard the currently arrivingpacket; set by the controller when the first word of the next packet is available.Cleared by RxOn=0.TestCmdEnbl'enables decoding of test commandsLoopBackdisconnects the transceiver, loops PE output to PD input, and enables TestColl'.Cleared by IOReset.SingleStepdisables the 23.53 mHz oscillator.  Changing this bit can produce a runt clock.Reset the transmitter first and expect an occasional bad receiver status.Cleared by IOReset.NoWakeupsdisables all controller wakeups.  Cleared by IOReset.TestClockinjects a single Dorado clock pulse (t3 of the Output instruction) into theEtherClk logic.  SingleStep must already be set.TestColl'injects a single Dorado clock pulse (t3 of the Output instruction) into thecollision synchronizer.  LoopBack must already be set.TestDatawire ORs with PD input.  LoopBack must already be set and TxOn must already��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î",qî3Špô�îFMïfñî·ïbsî·ï^¬pô�·
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y<ð]’i��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualEthernet Controller14 September 1981132be false.  Do not issue TestClock in an instruction that changes TestData.Cleared by IOReset.ReportCollisionsallows the PD to report malformed bits as collisions.  Cleared by IOReset.Status RegisterTIOA of 168 also selects the (read-only) status register.  The bits in this register are themost interesting to the microcode.  Less interesting state is available from the mufflers.Host Addrthe host address set by pullups on the backplane.RxOnthe receiver is enabled.TxOnthe transmitter is enabled.LoopBackthe interface is looped back.TxCollthe current output packet was aborted by a collision.NoWakeupsall wakeups are disabled.TxDataLatethe current output packet was aborted by a data late.SingleStepthe 23.53 mHz oscillator is disabled.TxFifoPEthe current output packet was aborted by a parity error.������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î",qî3Špô�îFMïfñî@ïbAuô�Ðð$ô�Ñð&î@ï`àô�îxï^¬î@ô�ÔðAô�Õî·ïY¶sô�î·ïVDpô�°	ïU·u�ïVDpð/ô�±ð"î·ïTyô�¿ðGô�ÀîxïQNuô�€î@ô�ð.îxïOî@îxïLåî@îxïJ±î@îxïH|î@ð5îxïFHî@îxïD	î@ð5îxïAß	î@ð%îxï?ªî@ð8ÿ�������^����·?‡<ð(„�†����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualOther IO and Event Counters14 September 1981133Other IO and Event Counters In addition to the disk, ethernet, and display controllers discussed in earlier chapters,Dorado contains a general input/output interface and a junk task wakeup located on theIFU board; the two registers used in this interface may alternatively be used as eventcounters in performance monitoring, and that use is also discussed here.Since the IFU board is not interfaced to the IOB, it cannot use the slow io system to controlthese features, so functions are used instead.Junk Task WakeupThe IFU board contains a circuit which wakes up the junk task (task 1) every 32 ms.  Thewakeup is dismissed by the AckJunkTW_B function; this function interprets B[15] as follows:a 1 enables wakeups; a 0 disables them; B[0:14] are ignored.  The junk task can dismiss thewakeup by doing IFUTest_B with any value on B (but B[15] must be 0 to reenable thewakeup at the next 32 ms tick).Junk task microcode will, among other things, maintain a Real Time clock.General IOA 16-bit register called GenIn (synonym EventCntA) is used for general input; it can be readwith the B_GenIn (synonym B_EventCntA) function but cannot be written by firmware.When used for general input, GenIn is written with information that is TTL-to-ECL convertedfrom the backpanel.A 16-bit register called GenOut (synonym EventCntB) is used for general output; it can beeither read with the B_GenOut (synonym B_EventCntB) function or written with theGenOut_B (synonym EventCntB_B) function.  GenOut is connected to the backpanelthrough ECL-to-TTL converters.The plan is that devices such as Diablo printers can be connected to the GenIn and/orGenOut signals via backpanel connectors.The choice of using one of these registers for general io or for event counting is determinedby the InsSetOrEvent_B function discussed below.Event CountersThe GenIn and GenOut registers can alternatively be used as event counters.  They cannot,of course, be used simultaneously for general io.  The registers are setup for either io orevent counting by the InsSetOrEvent_B function, where B[0:15] are interpreted as follows:ÿ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€îQqî2ýpô�îEVïfñî·ïa×rp�î·ï^eô�Ü
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�������Ö����·)=ð\â&����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualError Handling14 September 1981137muffler signals available to the control processor further define the halt condition; ESTATalso shows the halt-enables.  Midas will automatically prettyprint a message describing thereasons for an error halt.  The exact conditions that cause error halts are detailed in thesections below; the table here shows the ESTAT and muffler information which is relevant.Table 27:  Error-Related SignalsESTATESTAT   Task ErrorEnableExperiencingRelated Muffler Signals  Bit  Bit    Haltand MeaningRAMPERAMPEenTask2BkSTK, RM, or T parity failure.RmPerr and TmPerr mufflers on each processorboard indicate which byte of RM/STK or T had aparity failure.  StkSelSaved indicates that RmPerr appliesto STK rather than RM.MdPEMdPEenprocessor-detected Md parity failureTask2Bkif immediate _Md (_MDSaved false)Task3Bkif deferred _Md (_MDSaved true)MdPerr muffler on each processor boardshows which byte of Md failed.IMrhPEIMrhPEenCTDparity failure of IM[17:33]IMlhPEIMlhPEenCTDparity failure of IM[0:16]IOBPEIOBPEenTask2BkPd_Input parity failure if IOBoutSaved falseTask2BkOutput_B parity failure if IOBoutSaved trueIOPerr mufflers on each processor board showwhich byte failed.MemoryPEMemoryPEencache address section parity failure,cache data parity failure on write ofdirty victim or dirty Flush_ hit, orfast input bus parity failure.Processor ErrorsThe processor has parity ladders on each byte of the following:input to RM/STKgenerate parity for write of RM/STKinput to Tgenerate parity for write of TBgenerate parity for DBuf_B, MapBuf_B, Output_B, IM_BIOBcheck parity for Pd_Input and Output_BMdcheck parity for _MdRcheck parity for _RM/STK (unless bypassed from Pd orMd or replaced by _Id)Tcheck parity for _T (unless bypassed from Pd or Md orreplaced by _Id)Input ladders to RM/STK and T generate parity stored with data in the RAM; these laddersare not used for detecting errors.The processor computes parity on its internal B bus (alub).  The generated parity may betransmitted onto IOB when an Output_B function is executed; Store_ references write Bdata and parity in the cache; parity for IM writes and map writes is computed from B parity.None of the other B destinations either check or store B parity.  External B sources do not��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î#q
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;ô�…ðAô�†î·ïpô�‹ô�ŒðJÿ�������ê����·)=ð\âQ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualError Handling14 September 1981138generate parity.Parity on the R/T ladders is checked only when the R/T data path is sourced from theRAM, not when bypassing from Md or Pd is occurring, and not when R/T is sourced fromId.  A detected failure causes the RAMPE error halt, which indicates that some byte of RM,STK, or T had bad parity.  The muffler signals that further describe this error are in thePERR word:  StkSelSaved is true if the source for R was STK, false if the source for R wasRM; each processor board has RmPerr and TmPerr signals; RmPerr is true if the RM/STKbyte on that board had bad parity, TmPerr if the T byte had bad parity.  Note that if aninstruction beginning at t0 suffered an error, Dorado halts immediately after t4; the mufflersignals apply to the instruction starting at t0.  The Task2Bk muffler signals show the taskthat executed the instruction at t0.Md parity is checked whenever _Md is done; a failure causes the MdPE error-halt whenenabled.  The _MDSaved muffler signal in PERR is true when a deferred _Md caused theerror (T_Md, RM/STK_Md), false when an immediate _Md (A_Md, B_Md, or ShMdxx)caused the error.  On a deferred _Md error, Dorado halts after t6 and Task3Bk shows thetask that executed the instruction starting at t0; on an immediate _Md, Dorado halts aftert4, and Task2Bk shows the task.  The MDPerr muffler signals on each processor boardshow which byte of Md was in error.Io devices (optionally) compute and send odd parity with each byte of data; the processorchecks parity when the Pd_Input function is executed, but not when the Pd_InputNoPEfunction is executed.  When enabled, an IOBPE error halts the processor at t4 of theinstruction that suffered the error; Task2Bk shows the task that executed the instruction.The processor also checks IOB parity on Output_B, and an error halts at t4 as forPd_Input.  The IOBoutSaved muffler signal distinguishes Pd_Input from Output_B errors;an IOPerr muffler signal on each processor board shows which byte of IOB was in error; allof these are in the PERR muffler word.The processor generally does not pass parity at one stage through multiplexing to the next stage, soany failure in the multiplexing between one stage and the next will go undetected (exception: Bparity passed through to IOB).For example, the processor could write Md parity sent by the cache into the T RAM, when T isbeing written from Md.  Instead, however, it checks Md parity independently, but then recomputesthe parity written into T with the input ladder.  Hence, a parity failure detected on a byte of T canonly indicate a failure in either (1) the input parity ladder; (2) the output parity flipflop; (3) the outputparity ladder; (4) one of three 16x4 T RAM's; (5) one of two 4-bit latches clocked at t1 (Figure 3)through which the output of the T RAM passes; (6) one of two 4-bit latches clocked by preSHC'.Parity is handled similarly for writes of RM/STK.Parity is similarly recomputed on B.The processor does not generate or check parity on the A, Mar, or Pd data paths.  Anyfailures of the A, Mar, B, Pd, or shifter multiplexing or of the ALU go undetected; failures ofQ, Cnt, RBase, MemBase, ALUFM, or branch conditions go undetected.RemarkSince 256x4 and 16x4 RAM's are used for RM, STK, and T, and since the processor is implemented with thehigh byte (0:7) on ProcH and the low byte (8:15) on ProcL, byte parity requires an additional 4-bit storageelement on each board, of which only 1 bit is used.  We could conceivably have used all 4 bits to implement afull error-correcting code for each byte of R and T data.  However, there is insufficient time to correct thedata.  (Also, we use 256x1 RAM's instead of 256x4 RAM's for the RM and STK parity bits.)ÿ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î#q
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=ð]û®��������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualError Handling14 September 1981139Alternatively, parity could be computed over each 4-bit nibble rather than each 8-bit byte; the MC170component allows nibble parity to be computed just as economically as byte parity.  If this were done, then aparity failure would be isolated to a particular nibble.  With byte parity, a detected failure could be any of 9+components; with nibble parity, it would be isolated to one of 6+ components.  Implementing nibble parity forRM/STK and T would require about 4 more ic's per board than byte parity.It is hard to say whether the additional precision of nibble parity would be worth the additional parts.Control Section ErrorsThe control section stores parity with each 17-bit half of data in IM.  When IM is written,the two byte-parity bits on B are xor'ed with the 17th data bit to compute the odd parity bitwritten into IM.  It is possible to specify that bad (even) parity be written into IM, and thisartifice is used to create breakpoints; bad parity from both halves of IM is assumed to be adeliberately set breakpoint by Midas.IM RAM output is loaded into MIR and parity ladders on each 17-bit half give rise to errorindicators that, when enabled, will halt the processor after t2 of the instruction suffering anerror.  For testing purposes, halt-on-error can be independently enabled for each half ofMIR.  Both the unbuffered output of the MIR parity ladders and values buffered at t2 appearin ESTAT.  The buffered values show the cause of an error halt, and the unbuffered signalsallow Midas to detect parity errors in MIR before executing instructions or when displayingthe contents of IM.The special MIRDebug feature discussed in the "Dorado Debugging Interface" documentprevents MIR from being loaded at t2 when MIR parity is bad.  In other words, when theMIRDebug feature is being used, all of the t2 clocks in the machine will occur except theones to MIR.  This feature prevents the instruction that suffered an error from beingoverwritten at the expense of being unable to continue execution after the error.MIRDebug can be enabled/disabled by the control processor.IFU ErrorsThe IFU never halts the processor; any errors it detects are buffered until an IFUJumptransfers control to a trap location.  The errors it detects, discussed in "IFU Section", areparity failures on bytes from the cache, IFUM parity failures, and map parity failures on IFUfetches.Memory System ErrorsThere is no parity checking on Mar or on data in BR, so any failure in the addresscomputation for a reference goes undetected.  However, valid parity is stored with VA inthe cache, and any failure detected will cause the MemoryPE error to occur, halting thesystem (if MemoryPE is enabled).Parity is also stored in the Map (computed from B parity) and an error causes a fault taskwakeup in most situations (Exceptions:  IFU references and Map_ references do notwakeup the fault task when a map parity error occurs).ÿ����������������������������������������������������������������������������������������������������������î·ïfªpô�€î#q
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ô�±ðNî·ïA¼ô�ƒðSïA/u�ïA¼pô�„î·ï?ñô�ƒð9ô�„ð!î·ï>&ô�’ð*ô�“ð1î·ï<\ô�î·ï8êô�­ô�®ð?î·ï7ô�¨ð#ï6’u�ï7pô�©ð2î·ï5Uô� ð,ï4Èu�ï5Upð,î·ï3Šô�ßô�àðNî·ï1¿ô ðQî·ï/õô�ð:î·ï*Ûs	î·ï'ipô�ÆðVî·ï%Ÿô�šð]î·ï#Ôô�ŒðYô�î·ï"
î·ïðsô�î·ï~pô�Þð%ô�ßð-î·ï´ô�«ðFô�¬î·ïéô�±ð(ô�²ð/î·ïô�î·ï­ô�—ð9ô�˜ð!î·ïâô�èô�éðHî·ï
ô�ð6ÿ�������–����·Ð=ð[;7������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualError Handling14 September 1981140The cache data section stores valid parity with each byte of data.  When a munch is loadedfrom storage, the error corrector carries out single-error correction and double errordetection using the syndrome and recomputes parity on each 8-bit byte of data stored inthe cache.  When a word from B is Store_'d in the cache, byte parity on B is stored withthe data.A MemoryPE error occurs if, when storing a dirty victim back into storage, the memorysystem detects bad parity on data from the cache.The IFU and processor also check parity of data from the cache, as discussed previously.Sources of FailuresIn a full 4-module storage configuration, Dorado will have 1173 MOS storage, about 700Schottky-TTL, 3000 MECL-10K, and 60 MECL-3 DIPs, and about 1500 SIPs (7-resistorpackages).  This logic is connected with over 100,000 stitch-welded or multiwireconnections to sockets into which the parts plug; logic boards connect to sidepanelsthrough about 2500 edge pins.  Sockets are used for all the RAM DIPs in the machine;other parts are soldered in.  Given all these potential sources of failure, reliable operationhas been a surprising achievement.Initial debugging of new machines has been slow and difficult, requiring expertise not easilyavailable in a production environment.  In addition to mechanical assembly, board stuffing,and testing for shorts and opens both before and after stuffing, each machine hasaveraged about one man month of expert technician time to repair other malfunctionsbefore it could be released to users.Once released, the Dorados have been pretty reliable.  During a 100-day period (6 October1980 to 14 January 1981) the CSL technicians kept records of service calls made forapproximately 15 Dorados in service at that time.  The following summarizes the 43 servicecalls that were made.37 daysmean time between service calls per machine.45 days mean time between failures (some service calls were for microcode orsoftware problems).2.5 hours per machine per month average service time.13% of failures and 5% of time reseating logic boards in the chasis (connectors notmaking contact).11% of failures and 17% of time on open nets.13% of failures and 12% of time repairing 16k MOS RAM failures (standardconfiguration was 2 modules).37% of failures and 28% of time replacing other DIPs and SIPs.5% of failures and 10% of time on T80 problems.��������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î#q
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î·ï+Œô�îyï(ô�€î£ô�ð(îyï%åô�Äô�Åð;îyï$ô�îyï!æð5îyïtô�€ô�ð5îyïªô�îyïuð-îyïô�ùô�úðBîyï9ô�îyïð>îyï’ð/ÿ�������	t����·K<ðXÀ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualError Handling14 September 198114113% of failures and 11% of time on power supply failures.2% of failures and 2% of time on Terminal and display problems.4% of failures and 20% of time on repairing boards damaged during manufacturingor overheating.The power supply failures were due to problems that have since been corrected, and mostof the service calls for microcode or software problems would not happen in the moremature environment we have today.  However, the other failures are believed to berepresentative.  Note that none of the MOS RAM failures was the reason for a service call.These were found when testing a machine with diagnostics after a service call had beenmade for some other reason.Error CorrectionReliability has been improved by error-correction on storage.  The Dorado error-correctionunit of 64 data and 8 check bits (quadword), guards 1152 MOS RAMs from single failures,but almost no other parts on storage boards or in the error corrector are guarded.Our Alto experience suggests that some machines repeatedly fail under normal use due toundiagnosable failures.  For this reason, error correction should be viewed as guarding notonly against new failures but also against imperfect testing of parts that are either alreadybad or subject to noise (e.g., cosmic rays) or other kinds of intermittent failure.  The lattermay be more important in our environment.The failure summary above indicates, for a small sample, that 16k MOS RAMs, accountingfor 6% of all DIPs and SIPs (because the 15 Dorados had 2-module configurations, half themaximum) average about 4 times the failure rate of other parts and account for about 1.5failures/year/Doradothis would become 3 failures/year with a 4-module configuration.  Ifwe continue to do this well, a Dorado with error correction should run for years withoutuncorrectable MOS RAM failures.  The manufacturer's literature indicates that the dominantfailure mode appears to be single-bit failures with row and column addressing failuresaffecting many bits somewhat less frequent, but we don't know the distribution of these.If MOS failures do become significant, different strategies may be needed for single- andmulti-address failure modes.  With a multi-address failure, another failure in the samequadword causes a double error; but many single-address failures can occur in the samequadword without double errors.The failure model used below shows that with no periodic testing and replacement of badMOS RAMs, fatal failure statistics of the 1152 RAMs would approximate those of a 108RAM uncorrected store.  By thoroughly testing storage and replacing bad parts 4 timesmore often than the mean time to total failure of a part (defined below), the likelihood of anuncorrectable RAM failure crashing the system can be made insignificant compared withother sources of failure.Although system software could bypass all pages affected by a multi-address RAM failure,the entire module, 25% of storage, would be eliminated, so this is impractical except on anemergency basis.  Continuing execution despite a multi-address RAM failure will result in adouble error when any other coincident storage failure occurs in the same quadword; 1/16��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î#q
î2ýpô�îFMïfñîyïbð9îyï_éð?îyï]µô�ˆð2ô�‰îyï[êô�î·ïXxô�ô�ð>î·ïV®ô�ÅðHô�Æî·ïTãô�öðBô�÷î·ïSô�ð"ô�ð8î·ïQNô�©ô�ªð9î·ïOƒô�î·ïJjsî·ïFøpô�—ðZî·ïE-ô�”ðFô�•î·ïCcô�òðRî·ï?ñô�“ðEô�”î·ï>&ô�‰ô�ŠðDî·ï<\ô�™ðJô�šî·ï:‘ô�”ð.ô�•ð1î·ï8Æô�ð)î·ï5Uô�—ð0ô�˜ð&î·ï3Šô�‰ô�ŠðPî·ï1¿ô�›ð/ô�œð)î·ï/õô�ðYî·ï.*ô�°ô�±ðBî·ï,_ô�„ðZî·ï*•ô�Õð%ô�Öð1î·ï(Êô�²ð/ô�³ð)î·ï%Xô�ªðUô�«î·ï#Žô�ßð"ô�àð5î·ï!Ãô�¡ð#ô�¢ð3î·ïøô�î·ï‡ô�šô�›ðAî·ï¼ô�Àð)ô�Áð+î·ïñô�½ð-ô�¾ð(î·ï'ô�…ðAô�†î·ï\ô�²ðUî·ï‘ô�î·ï ô�›ô�œð@î·ïUô�Œô�ðIî·ïŠô�Žð[î·ï
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y=ð]’3��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualError Handling14 September 1981142of future failures will do this.Some interesting questions are:  How does MTBF vary with the EC arrangement?  MTBF ispertinent if we let Dorados run until they fail.  Alternatively, how likely is a failure in thenext day, week, or month, if we test the memory that often and replace bad RAMs?  Thesequestions can be asked assuming perfect testing (no failures at t=0) or imperfect testing(some likelihood of failures at t=0 because diagnostics didn't find them).To answer them, MOS RAM failures are modelled as one of two types:  those affecting asingle address in the RAM (called SF's), and those affecting all addresses (called TF's).We assume that TF's occur about 1/4 as often as SF's in 4Kx1 RAM's.  RAM failures areassumed exponentially distributed, correct if the failure rate doesn't change with time; overthe time range of interest, this is reasonable.  Finally, perfect testing is assumed, so thereare 0 failures at t=0.  These assumptions give rise to the following:let p = prob that an ic has a TF = 1  eatlet q = prob that an ic has a SF = 1  ebtlet n = number of MOS RAMs in the memoryWithout error correction, MTBF is the integral from 0 to infinity of [(1p)(1q)]n =1/n(a+b).  With b = 4a, in our 4-module system with n = 1024, this is 1/5120a =.00018/a.With error correction, failure occurs when, in a single EC unit, a TF coincides with eitheranother TF or an SF.  This ignores two coinciding SF's which is about 4000 (16k RAMs) or16000 (64k RAMs) times less likely.let n = number of RAMs in an error correction unitthen Prob[no failure] = Prob[no TF] + Prob[1 TF and 0 SF]Prob[no TF] = (1p)nSince failure modes are independent,Prob[1 TF and 0 SF] = np[(1p)(1q)]n1Prob[no failure] = Pok = (1p)n + np((1p)(1q))n1Pok = enat + n(1eat)(e(a+b)(n1)t)This is the probability for a single EC unit, so mean time to failure for all MOS storage isPok raised to a power equal to the number of EC units.  In other words, the argument ofthe integral for a 4-module x 4 quadwords/module system is Pok16 with n = 64+8; it isPok4 with n = 256+10 for a one munch EC unit.Then, expected time to failure for our 16 x n=64+8 memory system, is about:(1/n) * (1/16a + 16a/(16a+b)2 + 240a2/(16a+2b)3 + 3360a3/(16a+3b)4)= (1/an) * (1/16 + 1/25 + 5/288 + 105/17208)= (1/16an) * (1 + .64 + .28 + .006) = 1.93/16an= 1.93/16*72*a = .00168/aIn other words, mean time to failure is about 1.93 times longer than the time to the first TF= 9.5 times better than with no error correction = as often as 1024/9.5 = 108ÿ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î#q
î2ýpô�îFMïfñî·ïbî·ï^¬ô�ðUî·ï\áô�°ð_î·ï[ô�ô�Žð>î·ïYLô�¥ô�¦ðIî·ïWô�ðJî·ïTô�£ð$ô�¤ð1î·ïREô�ºðJô�»î·ïPzô�œðUî·ïN°ô�ðXô�î·ïLåô�šô�›ðCî·ïKô�ðEîyïG¨ð(ïH5uîyïEÞpð(ïFkuîyïDpð(î·ï@¡ô�êð5ô�ëïA.�ï@¡î·ï>×ô�Õð'ô�Öð(î·ï=î·ï9šô�¢ðTô�£î·ï7Ðô�Šð1ô�‹ð'î·ï6ô�ð#îyï2“ð2îyï0Èð9îyï-Vï-ãu�îyï+Œpð$îyï)Áð$ï*Nuîyï'÷pï'juï'÷pï(„u�ï'÷pï(„uîyï%Âp�ï%5uï%Âpï&Ouï%Âpï&Ouï%Âpï&Ouï%Âp�î·ï"sô� ô�¡ð?î·ï ©�ï uï ©pô�¢ô�£ð<î·ïtô�¯ô�°ð!ïçuïïtpî·ï@�ï³uïÍ�ï@pô�ð)î·ïñðKîyïïu�ïpïu�ïpïu�ïpïu�ïpïu�ïp�îyïµð,îyïêð/îyï î·ï®ô�Œð-ô�ð0î·ï
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œ=ð]oS����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualError Handling14 September 1981143uncorrected storage ic's.The results don't change much when imperfect testing is assumed.  The effect of this is toreplace densities for p and q by 1  Aeat, where A would be .999 if there was a 1/1000chance of a MOS ic being bad at t=0.RemarksOn each storage board, data from MemD is transported to a shift register consisting of 8 flipflops which arethen written into the MOS RAM's after transport has been completed.  This arrangement is unfortunateanyfailure in one of these components will cause a multiple error, and there are about 250 of these parts in a fullstorage configuration.One way to eliminate this problem while simultaneously reducing the part count on each storage board wouldbe to make modules consist of four storage boards, rather than two, so that only four flipflops receive data oneach bit path during transport; since each of these is in a different quadword, single failures would not causemultiple errors.The Dorado EC operates on quadwords, requiring 8 check-bits/64 data bits, or a 12.5% storage penalty.Alternative schemes are: 10 check bits/256 data bits (3.9%); 9 check bits/128 data bits (7.4%); 7 check bits/32data bits (22%); and no error correction at all (0%).The implementation of the EC pipeline is such that wider correction units significantly increase the time for amiss.  The current quadword error corrector requires 7 clocks (3 clocks for setup and correction, 1 clock perword of the quadword); this would become 11 clocks with a 128-bit EC scheme or 19 clocks with a 256-bit ECscheme.  Although cache hit rate seems to be above 99%, some implementation avoiding this delay would stillbe needed to make larger correction units attractive.If our quadword correction unit were replaced by a 4 x n=256+10 scheme:1/4na + 4a/n(4a+b)2 + 3a2/2n(2a+b)3, where for b = 4a this is(1/4na)*(1 + 1/4 + 1/36) = 1.28/4na = .0012/aIn other words, MTBF is about 1.28 times longer than the time to the first TF.  So error correction hasincreased MTBF by a factor of 6.2 over no error correction; alternatively, a 1064-RAM corrected memory failsas frequently as a 1064/6.7 = 159 RAM uncorrected memory.Surprisingly, the 64+8 EC scheme has only 42% longer MTBF than a 256+10 EC scheme. This improvementmay not be worth the 96 additional MOS RAM and 80 other DIPs required for address buffering; the 80additional DIPs might cause more failures than they save, being a net loss.The other method of maintaining our systems is to regularly test storage and replace bad RAMs.  Then thelikelihood of no double error before replacement is simply the value of the probability distribution (Pok4 andPok16 above) at the selected instant.  This reduces to an approximation of the form Pok = [ex + xex]mwhere x = nat, m is 4 or 16, and n = 72 for m=4 or 266 for m=16.  If this is evaluated at t = 1/mna,1/2mna, 1/4mna, etc. the following results are obtained:Table 28:  Double Error Incidence vs. Repair Rate m1/mna1/2mna1/4mna1/8mna 4.52.81.94.9816.79.84.98.99The interpretation of this table is as follows:  Measure mean time to total failure (TF) of a MOS RAM and callthis time 1/a; then assume 4 SF's per TF.  Then the rate at which TF's occur in storage will be 1/mna.  Sothe above tables show probability that the Dorado hasn't suffered a double error when tested and fixed asoften, 1/2 as often, 1/4 as often, or 1/8 as often as the mean rate of TF's.��������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î#q
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h����·!=ð[êt����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualPerformance Issues14 September 1981144Performance IssuesThis chapter discusses two issues:(1) How rapidly will Dorado be able to execute Mesa, Lisp, SmallTalk, etc. macroprograms;(2) What relationship do some of the design parameters bear to performance;Cycle TimeThe first issue is cycle time.  Dorado was designed for a 50 ns cycle time; the first threeprototypes used stitchweld technology for interconnections and operated correctly at 55 nscycle time; however, subsequent machines are being built using multiwire technology andwill not operate faster than about 60 ns cycle time.  The baseboard at present initializes theclock period to 64 ns for all machines during a boot, although there is some indication thatdesign changes made recently and repair of a few lingering slow path problems wouldpermit 5 to 10 ns faster operation.With respect to achievable cycle time, the two important differences between stitchweldand multiwire technology are that stitchweld uses point-to-point wiring and has wireimpedance of about 100 ohms (which is ideal), but multiwire uses Manhattan (square-corner) wiring with wire impedance of about 50 ohms on the inner layer and 70 ohms onthe outer layer of wiring (Most signals are in the outer layer.); longer wires and imperfectimpedance matching result in slower speed.Emulator PerformanceGene McDaniel's measurements of the Alto Mesa compiler have been adjusted to makethem compatible with Pilot Mesa and are summarized below.  It must be pointed out thatthe compiler makes heavier use of short pointers than do Pilot Mesa programs; programsbeing developed now are heavily biased toward long pointers and would be slower than theexecution rate below indicates.  Average execution rate was about 5.6 cycles/opcodeexcluding disk wait.  About 38% of all cycles are consumed by XFER opcodes (i.e.,subroutine call or return) and account for about 6% of opcodes executed.  If these areexcluded, the remaining 94% average about 3.1 cycles/opcode; if jumps and conditionaljumps are also excluded (about 14% of executions), the others average 2.5 cycles/opcode.These times include all memory and IFU delays.These excellent results indicate that there are no unusual delays due to problems with thememory or IFU and that the processor is completing most opcodes quickly.  Since XFERopcode take 34 (local) to 54 (external) cycles/opcode excluding memory delays, speeding,respecifying, or reducing executions of XFER seem to be the most promising ways ofimproving performance.In the above results, instruction forwarding has saved an average of about .25cycles/opcode or about 4% overall, in agreement with our expectations.ÿ������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î##qî5¾pô�îEVïfñî·ïa×rî·ï^epð"î·ïZóô�ô�‘ðEî·ïWô�ðKî·ïRhs	î·ïNöpô�£ðKô�¤î·ïM,ô�ŒðZî·ïKaô�£ðWî·ïI–ô�‚ð%ô�ƒð9î·ïGÌô�‡ð/ô�ˆð-î·ïFô�Çô�Èð3î·ïD7ô�ð#î·ï@Åô�ÂðWî·ï>úô�þðTî·ï=/ô�×ð-ô�Øð&î·ï;eô� ô�¡ðBî·ï9šô�¢ô�£ðJî·ï7Ðô�ð*î·ï2¶sî·ï/Dpô�¿ð(ô�Àð)î·ï-zô�¥ðVî·ï+¯ô�£ð8ô�¤î·ï)äô�ƒðHô�„î·ï(ô�ÝðAô�Þî·ï&Oô�êð=ô�ëî·ï$…ô�¹ð*ô�ºð,î·ï"ºô�¶ðIô�·î·ï ïô�Œð2ô�ð&î·ï%ô�ð.î·ï³ô�”ð/ô�•ð+î·ïèô�¨ðIô�©
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t����·=ðY����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualPerformance Issues14 September 1981145For SmallTalk and Lisp instruction sets, performance is much worse than Mesa (averagingover 30 cycles/opcode on Smalltalk 76).  Careful studies should be made to understand thereasons for this fully, but one reason is that the 16-bit word size is a serious limitation.Long storage pointers are used extensively, so execution would be substantially faster on amachine with, say, 32-bit data paths.IFU Not-Ready WaitFor the Mesa compiler, 19.5% of all cycles were in IFU not-ready wait; 16% due toincorrectly predicted jumps, 2.5% to cache miss wait, and 1% to other causes.  The 16%due to incorrectly predicted jumps might be improved.The Mesa microcode presently predicts that all conditional jumps will not jump; it isdesirable to predict not-jump unless more than 75% of executions jump due to theoverhead of restarting the IFU an extra time.  40% of the time the prediction is wrong and ajump occurs, so it seems that the microcode is doing the best it can.However, some loops ("while J ne 0 do," for example) are compiled as a normally-falseconditional jump at the beginning of the loop and an unconditional jump from the end ofthe loop back to the beginning; a faster sequence is a normally-true conditional jump at theend of the loop, eliminating the unconditional jump altogether.  The general objectives inchanging the compiler would be as follows: (1) Eliminate unnecessary jumps andconditional jumps; (2) Make the jump/not-jump execution of conditional jumps be aspredictable as possible; and (3) Make the not-jump path be the most likely, unless thisconflicts with objective (1).Microstore RequirementsSpeed is not the only issuesome reduction in microstore requirements might be possiblethrough design changes.  Space requirements for a 1981 release of the Alto/Mesaemulator system were as follows:Table 29:  Utilization of the MicrostoreMesa basic opcode set20248Cedar allocator & collector5768Floating point4578Alto opcode set11638Alto BCPL Runtime2268BitBlt subroutine4168Fault handling658Ethernet driver2558Disk driver4308Display driver5008Junk io driver768LoadRam1008Initialization1508������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î##qî5¾pô�îEVïfñî·ïbô�˜ðGô�™î·ï`Sô�€ðUô�î·ï^‰ô�¸
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t��������€����·õ=ð[:������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualPerformance Issues14 September 1981146Total76738leaving 1058 free locationsSince we do not require that more than two emulators be loaded in the microstore at onetime, there is presently a little space left for extensions.  MicroD is able to utilize well over99% of the available microstore.The third performance issue is cache efficiency and miss wait; the fourth is available iobandwidth and io task cycle consumption.  These are discussed in sections below.Cache Efficiency and Miss waitThe value of shortening the wait for a storage read is roughly proportional to misslikelihood.  Suppose that the prototypical opcode was a one-byte opcode implemented bythe following microcode:Fetch_Id, StkP+1;Stack_Md, IFUJump[0];For this example, execution time on a hit is 2 cycles; on a miss, 28 cycles.  Delay for IFUmisses must be added to this.  Since the IFU is 6 bytes ahead of the current opcode, itsmisses delay 28 cycles less execution time for preceding 6 bytes; if any of the 6 bytes itselfcauses a miss, IFU delay will be 0 because it will catch up; the IFU never gets two misses(in this example) because it crosses at most one munch boundary.  Hence, execution timewill be 2 + 26*(1H) + (28-12)*H6*(1H), with the following results:Table 30:  Execution Time vs. Cache EfficiencyHitExecution  IFU% Miss% CyclesCycles  Wait1002.00.000 992.26.1517 982.52.2829 963.04.5044 943.56.6753 924.08.7959This crude analysis shows the importance of cache efficiency in determining systemperformance.  Fortunately, measurements made by Doug Clark and Gene McDanielindicated the following surprisingly high cache hit statistics:Overall cache hit rate on three Mesa programs was 99.2% to 99.8%.  4.9% to 8.1%of all cycles were held.  10% to 19% of references were Store_'s, the rest fetches.16% to 66% of misses had dirty victims, which cause additional cycles to be heldwhile the cache address section is busy.Another measurement showed a 99.7% hit rate for IFU references.The processor obtains a word from the cache in 16% of all cycles and the IFU in32% of all cycles; the processor actually shuts out the IFU by making its own��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïgpô�€î##qî5¾pô�îEVïfñî:ïbî)Wïa‘t�î.qïbp
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¿<ð]o;����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualPerformance Issues14 September 1981147reference about 20% of the time.Provision has been made to expand the Dorado cache to 16k words, when 4k x 1 MECLRAM's are economically available, but the existing cache is so efficient that this may neverbe necessary.Performance Degradation Due to IO TasksTo first approximation, only the display controller word task (DWT) uses enough storagebandwidth to interfere significantly with emulators.  Since it uses the fast io system, DWTrequires service once/munch and will require two instructions/wakeup in the ordinarycase.  In addition, if the next instruction (by another task) issues a memory reference, it willalways be held one cycle while the DWT's IOFetch_ advances ASRN.A quick calculation shows that at an io bandwidth of 256 x 106 bits/sec (106 munches/sec)the display controller will use 48% of storage bandwidth and 12% of processor cycles at 60ns/cycle.The earlier example showed that with no io interference and a 99% hit rate, the emulatorspent 17% of cycles in miss wait, 83% in useful execution.  With a 256 x 106 bit/sec displayactive, emulator misses are slowed about 2 cycles each, so the overall effect of the displaywould be that about 78% of all cycles are emulator executions, 12% display taskexecutions, and 16% hold; the one cycle holds for IOFetch_ would make performancesomewhat worse than this.An IOFetch_ by the display task to the same cache row as an emulator miss will remain inthe address section, increasing display task latency and requiring more buffering.However, this won't degrade emulator performance.The Alto monitor only uses 14.7 x 106 bits/sec (1/17 of the above) and would not interfereappreciably with emulators.The disk controller is the fastest "slow" io device among standard peripherals.  Whenrunning, its word interrupt task reads a double word from the cache every 3.2 ms in a 3instruction/interrupt inner loop, consuming about 5.6% of all cycles at 60 ns/cycle.  Itsmemory references consume the cache at a rate of .04 munches/ms, low enough thatstorage interference with the emulator isn't significant.  However, a 256-word disk transferdisplaces about 1/16 of the cache entries, so the emulator may experience a lower hit rate.Cache and Storage GeometryThe current geometry was chosen without measurements or simulation of programs, butmeasurements made since then have indicated a surprisingly good cache performance, sonot much could be gained through changes.The following parameters are relevant:1 word as the unit of storage inside the memory pipeline;16-word munch;����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î##qî5¾pô�îEVïfñîyïbî·ï^¬ô�¥ðJô�¦î·ï\áô�ŽðHô�î·ï[ô�î·ïUýsð'î·ïR‹pô�µð(ô�¶ð/î·ïPÁô�£ð>ô�¤î·ïNöô�âð$ô�ãð0î·ïM,ô�ƒð=ô�„ð#î·ïKaô�ð@î·ïGïô�ƒð'ô�„ïH|t�ïGïpïH|t�ïGïpî·ïF$ô�ˆð<ô�‰î·ïDZî·ï@èô�¢ô�£ðEî·ï?ô�ð:ô�‚ï?ªt�ï?pî·ï=Sô�‹ð>ô�Œî·ï;ˆôð%ôð*î·ï9½ô�Ðð@ô�Ñî·ï7óô�î·ï4ô�ðUô�Žî·ï2¶ô0ô1ð3î·ï0ìô�ð1î·ï-zô�‹ð$ï.t�ï-zpô�Œð#î·ï+¯ô�î·ï(=ô�Îð,ô�Ïð)î·ï&sô�­ðMô�®�u�pî·ï$¨ô�¾ðDô�¿î·ï"Ýô�Ïð=u�pô�Ðî·ï!ô�šô�›ðHî·ïHô�ƒð>ô�„î·ï/sô�î·ï½pô�ºðSî·ïòô�—ðUî·ï(ô�ð)î·ï¶ð&îyïDð9îyï
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2=ð]Ù&����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualPerformance Issues14 September 1981148256 munches in the cache (expandable to 1024);4 columns in the cache.Munch SizeA 16-word munch size was chosen primarily because 8 cycles for transport balances 10cycles for storage access, avoiding loss of bandwidth.  The use of 256x4 RAM's toimplement the cache address section allows the original 4k-word cache (implemented with1kx1 RAM's) to be expanded to 8k words or 16k words, when 4kx1 RAM's are economicallyavailablethis is possible because only 64 of the 256 words in the address section arebeing used with the 4k-word cache.  Miss wait is about 28 cycles and storage bandwidthabout 533 x 106 bits/sec with 16-word munches.8-word munches would lower the storage bandwidth to about 262 x 106 bits/sec, probablyunacceptable.  Also 8-word munches would limit cache expansion to 8k words.  However,miss wait would be reduced to about 24 cycles because transport would require only 4cycles.  32-word munches would not allow greater storage bandwidth to fast io devicesbecause bandwidth is already limited by transport with 16-word munches.  Nor would itallow expansion to a larger cache data section because we have no way to build a datasection larger than 16k words.  Also, miss wait would be slowed to 36 cycles, so it does notseem that this munch size is attractive.For a given size of the cache data section, with smaller munches the cache will tend tostabilize with a larger amount of useful information; however, when a program is changingcontexts, larger munches might bring the new context into the cache more quickly.  Also,fast io tasks will interfere less with the emulator on larger munches because fewer wakeupsand IOFetch_'es will be required.  However, the extra buffering and longer miss wait offsetsthis advantage somewhat.Considered together, these factors suggest that the 16-word munch we are using issubstantially better than either 8 or 32-word munches.Data Path WidthHaving only 16 bit wide data paths slows misses.  Doubling the paths to 32 bits wouldreduce EC time by 1 cycle and transport time into the cache by 4 cycles (i.e., delay onmisses would be 23 cycles instead of 28).  There were not enough edge pins to do this.However, if a method of doubling the path width were found, the storage system wouldprobably be arranged as two modules of four storage boards each rather than fourmodules of two boards each, and 32-word munches might be better than 16-wordmunches.ÿ������������������������������������������������������������������������������������������������î·ïfªpô�€î##qî5¾pô�îEVïfñîyïbð.îyï`Sqp
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î·ï"ºô�³ð@ô�´î·ï ïô�¨ðEô�©î·ï%ô�»ðTî·ïZô�óô�ôð5î·ïôð/ôî·ïÅ�������	 ����·~=ðN	��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualPerformance Issues14 September 1981149Cache ColumnsThe reason for multiple columns is to approximate LRU reloading; the columns aremoderately expensive because separate hit logic has to be provided for each one; the V-NVstuff also costs a few ic's with more than two columns.  Altogether the current 64x4 cacheis about 40 ic's larger than a 128x2 cache (Because of its 50-50 LRU behavior on thefourth column, our cache is somewhere between the 64x4 and 128x2 or 128x3 cachesbelow.).  The table below shows likelihood that the Nth LRU munch is no longer in thecache for various geometries:Table 31:  Cache Geometry vs. LRU Behavior N32x464x2128x232x364x3128x364x4128x4  4.000.001.000.000.000.000.000.000  8.000.006.002.002.000.000.000.000 16.001.025.007.013.002.000.000.000 32.017.089.026.077.014.002.002.000 64.140.264.090.323.079.014.018.002128.570.596.264.767.323.080.141.019256.960.910.595.987.764.323.568.142512.763.959.567These numbers are computed from a binomial distribution using the following formulae:let R = rows in cachelet C = columns in cachethen p = (R1)/R = probability that a munch of VA is in its rowthen q = 1/R = probability that a munch of VA is not in its rowthen probability of a miss for the nth element is:CP(miss)11  pn21  pn  nqpn131  pn  nqpn1  n(n1)q2pn2/2!41  pn  nqpn-1  n(n1)q2pn2/2!  n(n1)(n2)q3pn3/3!etc.Without extensive measurements on programs, it is impossible to know how much better,say, a 32x4 cache is than a 64x2 cache, or to know whether a 128x2 cache is better orworse than a 32x4 cache, for example.  If a particular program is confining itself to a verysmall set of munches, then more closely approximating LRU reloading is most important.However, if the likelihood of reference flattens out after a small N, then it won't mattermuch that LRU reloading isn't very well approximatedthe total size of the cache will be amore important determinant of performance.��������������������������������������������������������������������������������������������î·ïfªpô�€î##qî5¾pô�îEVïfñî·ïbqî·ï^¬pô�ÿ
ô�ðBî·ï\áô�‚ð6ô�ƒð#î·ï[ô�ô�Žð?î·ïYLô�Âô�Ãð6î·ïWô�ÇðIô�Èî·ïU·ô�¸ô�¹ðLî·ïSìô�îÄïPzsô�Xð*îxïMpô�€îûî~îî$…î*î/‹î5î:‘îxïI–îûî~îî$…î*î/‹î5î:‘îxïGÌîûî~îî$…î*î/‹î5î:‘îxïFîûî~îî$…î*î/‹î5î:‘îxïD7îûî~îî$…î*î/‹î5î:‘îxïBlîûî~îî$…î*î/‹î5î:‘îxï@¡îûî~îî$…î*î/‹î5î:‘îxï>×îûî~îî$…î*î/‹î5î:‘îxï=îû�î~�î�î$…�î*�î/‹î5î:‘î·ï9šô�ÄðUî·ï6(ô�î·ï4^î·ï2“ð?î·ï0Èð?î·ï.þð2îyï+Œ�îûîyï(�îûï(§t�îyï&Op�îûï&Üt�ï&Opï&Ütîyï$…p�îûï%t�ï$…pï%tï$…p	ï%t�ï$…p�ï%tï$…pîyï"º�îûï#Gt�ï"ºpï#Gtï"ºp	ï#Gt�ï"ºp�ï#Gtï"ºpï#Gt�ï"ºp�ï#Gtï"ºpîyï ïî·ï}ô�¨ð!ô�©ð4î·ï³ô�ªðRô�«î·ïèô�”ðAô�•î·ïô�®ðCô�¯î·ïSô�Áð0ô�Âð*î·ïˆô�Œô�ðMî·ï¾ô�ð*�������¤����·w=ðU”´��������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualGlossary14 September 1981150Glossary a - the first 8-bit operand of a two-byte or longer opcode.b - the second 8-bit operand of a three-byte or longer opcode.bypassing - a number of memories and task-specific registers in Dorado (RM, STK, and T,for example) are written with data that might be needed before the write occurs.  These areimplemented so that data about-to-be-written is substituted for data read from the registeror memory when appropriate.  This substitution is called bypassing and enables Dorado torun considerably faster than would otherwise be possible.cache entry - a munch together with VA of the munch and 4 flag bits.  For a 64 row x 4column cache, VA[28:31] are the word in the munch, VA[22:27] address the row, andVA[7:21] are stored in the cache entry.column - one of 4 groups of 64 (expandable to 256) cache entries.  The cache column inwhich a word with VA resides is determined by comparing VA[7:21] with the correspondingbits stored in the four columns at row VA[22:27].  Thus a memory word may occupy one of4 locations in the cache.control processor - the microcomputer on Dorado's baseboard, or the Midas programoperating Dorado from an Alto.dirty - a cache entry is dirty if the information in it differs from information in storage,because a store has been done into the cache, and storage has not yet been updated.  Apage is dirty if a store has been done into the page since its map dirty bit was cleared.emulator - the lowest priority task, number 0, always awake.  The emulator is distinguishedby the fact that it cannot block, can use Stk, and has a private pipe entry.  Primarily theemulator task will implement instruction sets.entry vector - the exit microinstruction of an opcode sends control to the firstmicroinstruction of the next opcode by means of IFUJump[n] (n = 0 to 3), where nchooses one of 4 entry microinstructions for the next opcode; these four microinstructionsare the next opcode's entry vector.fault task - the highest priority task, number 15, woken whenever a memory fault or stackerror occurs.hit - a reference which finds the desired word in the cache.Midas - the Alto program used for loading and debugging Dorado remotely.miss - a reference which does not find the desired word in the cache.module - the unit in which storage is packaged, either 64K, 256K, or 1M words.  A machinemay have 1 to 4 modules.������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î%åqî5pô�îEVïfñî·ïa×rp�î·ï^es�pð:î·ïZós�pð=î·ïWqpô�–ô�—ðJî·ïU·ô�‚ð"ô�ƒð9î·ïSìô�žð/ô�Ÿð,î·ïR"ô�“ð9qpô�”î·ïPWô�ð9î·ïLåqô� 
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pð?ô�î·ï.þô�¥ð%ô�¦ð6î·ï-3ô�ð-q�î·ï)Áô:pðCî·ï'÷ô�áô�âð=î·ï&,ô�”ð(ô�•ð2î·ï$aô�qp�î·ï ïqô�ž	pð.ô�Ÿð!î·ï%ô�î·ï³qpð9î·ïAqpðCî·ïÏqpðAî·ï]qpô�ƒð>ô�„î·ï’ô�ÿ�������	X����·K<ðXÀ����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualGlossary14 September 1981151MTBF - mean time between failures.munch - 256 bits, or 16 machine words; the unit of data for main storage.parity - the parity of a data unit is the exclusive-or of all bits in the data unit; parity has theproperty that changing any single bit in the data unit will also change the parity, so it canbe used to detect single failures.  A data unit has odd parity when the number of 1's in theunit is odd, even parity when the number of 1's is even.  Dorado uses odd parityeverywhere, which means that the number of 1's in the data unit including its associatedparity bit should be odd when data is correct.PC - "program counter".  In this manual PC refers to the 16-bit byte displacements relativeto BR 31 (the codebase) which are maintained by the IFU for the current instruction set.This term should be distinguished from TPC, which refers to the address of the nextmicroinstruction for a task.pipe - a 16-entry memory which records the state of the last few storage references.quadrant - one of the four 4k-word regions in a 16k-word control store.RAM - "random access memory"; selected words in the memory can be both read andwritten.reference - a reference to the memory, initiated by the processor or by the IFU.  Aprocessor reference transfers a single word between the cache and the processor; an ioreference transfers a munch between storage and an io device.ROM - "read-only memory"; the contents of the memory are specified when the hardwareis constructed and cannot be modified during program execution.  ROM elements used onDorado can be reprogrammed with a special device constructed for the purpose.row - one of the 64 or 256 groups of 4 cache entries.  The cache row in which a wordresides is determined by bits 20..27 of its virtual address.storage - the main memory of the machine, organized in munches of 256 bits, or 16machine words.storage reference - a reference to the storage, initiated as a result of a memory reference.A processor reference causes a storage reference if there is a cache miss or if the FDMisscontrol is true in the memory control register; an io reference always causes a storagereference.storage reference number (SRN) - an address of a pipe entry which identifies a particularstorage reference.subtask - a two-bit number presented by an io device to the processor and memory systemwhile its task is running.  The processor OR's subtask with RBase[3]..RSTK[1] indetermining the RM address and with MemBase[2:3] in determining the base registerselection.  The memory system buffers the subtask for fast io devices, and then sends itover the Fin or Fout bus as part of device identification.������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������î·ïfªpô�€î%åqî5pô�îEVïfñî·ïbqpî·ï^¬qpðDî·ï[:qô�‰pðZî·ïYoô�—ð;ô�˜ð"î·ïW¥ô�ˆð4q	pô�‰î·ïUÚô�öqô�÷pð8î·ïTô�§ð5ô�¨ð#î·ïREô�ð.î·ïNÓqpô�‹ð2ô�Œð'î·ïMô�©ð3ô�ªð%î·ïK>ô�Üô�ÝðCî·ïIsô�î·ïFqpô�ÜðPî·ïBqpô�ð?î·ï?qô�¾pð@ô�¿î·ï=Sî·ï9áqpô�äð>ô�åî·ï8qô�«pô�¬ð5qî·ï6Kpô�ð4î·ï2Úqô�pð.ô�žî·ï1ô�’ð4ô�“ð!î·ï/Dô�ðMî·ï+Òqpô�¬ô�­ð>î·ï*ô�ð<î·ï&–qpô�Ûð:ô�Üî·ï$Ëô�
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z����·Ù=ð\2(������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Dorado Hardware ManualGlossary14 September 1981152tag - The extra bit in Md readout which complements for successive Fetch_'es andStore_'s by the same task.  Agreement of the bit in Md with the current value equalsreference finished.task - one of the 16 priority scheduled tasks.  Special tasks are the emulator (task 0, lowestpriority) and the fault task (task 15, highest priority).  Other tasks are paired with iocontrollers.VA - virtual address.Vacant - a cache entry or map entry which does not contain valid data.Victim (Vic) memory - stores 4 bits for each cache row.  Two of the bits specify the victimwhich will be chosen if a reference to that row results in a miss, and the other two are thenext victim.victim - on a processor reference that causes a cache miss, the cache entry chosen to bereplaced by the referenced data.WP - write protected.  Map entries and cache entries have bits with this name.����������������������������������������������������������������������������������������������������������������î·ïfªpô�€î%åqî5pô�îEVïfñî·ïbqô�îpô�ïð=î·ï`Sô�Éð0ô�Êð$î·ï^‰ô�î·ï[qô�„pðXî·ïYLô�ãð@ô�äî·ïWî·ïTqpô�î·ïPžqpð@î·ïM,qô�’p�qpð$ô�“qî·ïKapô�ðFô�Žî·ïI–ô�î·ïF$qpô�’ð5ô�“î·ïDZô�î·ï@èqpðLÿ�����������·@¡<ð'j�}��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������	HELVETICA�������������
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