This document is for internal Xerox use only.Dorado Hardware Manualby E.R. Fialacontributions to the manual byR. Bates, D. Boggs, B. Lampson, K. Pier, E. Taft, and C. Thackerother help byD. Clark, W. Crowther, W. Haugeland, G. McDaniel, and S. OrnsteinAugust 1, 1985The document describes the architecture and hardware design of the Dorado computer. At the dateof this printing, approximately 160 systems have been released to users.This release incorporates a major revision to the manual to lean towards hardware training. Therevision of 14 September 1981 should be used by people interested in writing microcode.Revision history:14 February 1979First complete manual exclusive of I/O controller chapters.8 October 1979Chapters on I/O controllers added; major revisions.14 September 1981Major revision to the Display Controller chapter, medium revision to Instruction Fetch Unit and Disk chapters, minor revisions elsewhere.August 1, 1985 simplified manual for technician training by Frank Vest.XEROXPalo Alto Research CenterComputer Sciences Laboratory3333 Coyote Hill Rd.Palo Alto, California 94304This document is for internal Xerox use only.+bpX,q Xxr TsX 1QNO@1K J#A C@ ?'9 >H :;$ 8Wy5t 2pF; 0 '3 /he -$ ,G,#u,p,.,cs,;pX-| n>ROTable of Contents1.Introduction 12.Overview 22.1Control 22.2Registers, Memories, and Data Paths 22.3Timing 62.4Instruction Fields 82.6Notation 93.Processor Section 103.1RM and STK Memories, RBase and StkP Registers 103.2Cnt Register 123.3Q Register 123.4T Register 123.5BSEL: B Multiplexor Select 123.6ASEL: A Source/Destination Control 143.7ALUF, ALU Operations 163.8LC: Load Control for RM and T 183.9FF: Special Function 183.10Multiply and Divide 223.11Shifter 223.12Hold and Task Simulator 244.Control Section 254.1Tasks 254.2Task Switching 264.3Next Address Generation 274.4Conditional Branches 284.5Subroutines and the Link Register 294.6Dispatches 304.7IFU Addressing 304.8IM and TPC Access 314.9Hold 324.8Program Control of the DMux 325.Memory Section 345.1Memory Addressing 345.2Processor Memory References 355.3IFU References 375.4Memory Timing and Hold 38(%^pi[q 9rxXxq 9rxV 9xT #9xR 9xP 9xN 9xKq q9rxIP -9xG 9xD 9xB 9x@~ 9x>J #9x< 9x9 9x7 9x5x 9x3C 9x1 x9x-q q9rx+ 9x) 9x' 9x% 9x# !9x"  9x  9x. 9x@ 9xR 9x'q q 9rx 9x( 9x: 9xL 9x"/Q+SDorado Hardware ManualTable Of ContentsAugust 1, 19855.5The Map 415.6The Pipe 445.7Faults and Errors 455.8Storage 485.9The Cache 495.10Initialization 505.11Testing 516.Instruction Fetch Unit 526.1Overview of Operation 526.2The IFUJump Entry Vector 566.4Use of MemBX and Duplicate Stk Regions 566.5Traps 576.6IFU Reset 596.7Rescheduling 596.8Breakpoints 596.9Reading and Writing IFUM 596.11IFU Testing 606.12Details of Pipe Operation 617.Slow IO 647.1Input/Output Functions 64 7.4SubTasks 658.Fast IO 678.1Transport 678.2Wakeups and Microcode 679.Disk Controller 689.1Disk Addressing 699.3General Microcode Organization 709.4Task Wakeups 719.5Control Register 719.6Format RAM and Sequence PROMs 729.7Tag Register 739.8FIFO Register 759.9Muffler Input 759.10Error Detection and Correction 7810.Display Controller 7910.1Operational Overview 7910.2Video Data Path 8010.3Horizontal and Vertical Control 8310.4Pixel Clock System 85 fr!Zs1Ur_ 9x]( 9x[: 9xYL 9xW^ 9xUp 9xS 9xPWq q9rxNF 9xLX 9xJj &9xH| 9xF <xE  9xC 9xA. 9x?A 9x=S 9x:'q q9rx89 9xx6K 9x3 q q9rx1 9x/! 9x+q q9rx* 9x( 9x&, 9x$> 9x"P 9x b 9xt 9x 9x 9xmq q9rx 9x 9x 9xo 9x^ (0XDorado Hardware ManualTable Of ContentsAugust 1, 198510.5Seven-Wire Video Interface 8510.6Processor Task Management 8710.7Slow IO Interface 8710.8DispM Terminal Interface 9011.Ethernet Controller 9111.1Ethernet Packets 9111.2Controller Overview 9211.3Receiver 9311.4Transmitter 9411.5Clocks 9511.6Task Wakeups 9611.7Muffler Input 9711.8IOB Registers 9811.9Control Register 9811.10Status Register 9912.Other IO and Event Counters 10012.1Junk Task Wakeup 10012.2General IO 10012.3Event Counters 10013.Error Handling 10213.1Processor Errors 10313.2Control Section Errors 10413.3IFU Errors 10413.4Memory System Errors 10413.5Sources of Failure 10513.6Error Correction 10615.Glossary 107 fr!Zs1Ur_ 9x]( 9x[: 9xY) 9xUq q9rxT 9xR" xP 9xN 9xL 9xJ 9xH 9xF 9xE  9xC 9x?q q9rx> 9x< 9x:' 9x6q q 9rx3 9x2L 9x0 9x/D 9x- 9x,< 9x'q q9rx< /HDorado Hardware ManualTable Of ContentsAugust 1, 1985List of Figures 1.Dorado: Programmer's View 2.Card Cage 3.Processor Hardware View 4.Shifter 5.Control Section 6.Next Address Formation 7.Instruction Timing 8.Overall Structure of the Memory System 9.Cache, Map, and Storage Addressing10.The Pipe and Other Memory Registers11.Error Correction12.Instruction Fetch Unit Organization13.Disk Controller14.Display Controller15.Display Controller IO Registers16.Ethernet Controller17.Programmers' Crib Sheet fr!Zs1Ur)P^pi:[rX\:YL\:W\:U\:S\:R"\:PW\:N\&:L\":J\#:I-\:Gb\#:E\:C\:B\:@7\:>m\ >&/)Front ViewTop View+5 Volt-5 Volt-2 Volt+12 VoltFanFanqqqqqqqr.625 inr4.5 in.qrq13 in.3.5 in.Fast or slow I/OFast or slow I/OFast or slow I/OFast or slow I/ODispY (Display controller)DskEth (Disk/Ethernet controller)Storage odd or Slow I/OStorage odd or Slow I/OStorage even or Slow I/OStorage evenStorage evenStorage oddStorage oddIFU (Instruction Fetch Unit)BaseB (Baseboard)Storage even or Slow I/Oqr15.5 inqr10.5 inrqPower SuppliesNot toScaleMemC (Memory addressing)MemD (Cache data and EC)The +5 V supply and one fan are controlled by a switch; -5 V, +12 V, and-2 V supplies, the other four fans, and the disk logic and spindle powerBaseB and ContB boards are equipped with temperature sensors that arerepetitively monitored by the baseboard microcomputer; most other boardsmicrocomputer will shut down the three power supplies that it controls.The microcomputer also monitors power supplies; when any voltage or currentdeviates from its allowed range, the microcomputer shuts off power tothe three supplies that it controls. 2315 246 71 24 21ic's of random logic1kx1 ECL RAM's16x4 ECL RAM's256x4 ECL RAM'sThe following shows approximate component count:11 Logic boards:8 Storage boards:10561152ic's of random logic15 in.<>PanelWiringPanelWiringFive 240 CFM (free air) fans estimated to produce375 CFM airflow in the enclosure.Estimated temperature rise of the exiting air is about8 degrees C.Power consumption on each logic board averagesabout 85 watts, on each storage board about 55watts.On each board -5 V power is distributed byfingers reaching across the board on the topside from the back, -2 V power by fingersreaching across the board on the bottom fromthe back. +5 V and +12 V reach across the boardfrom the front on top and bottom. The powerfingers on the bottom feed through to thecomponent side on the top.1600SIP'sThe +5 V supply is used for TTL/ECL conversions andD1CardCage.silFigure 2Card CageSideSideNormal MECL-10000 DIP's are connected to the groundplane and -5V supply. Logic nets are terminatedthrough 100-ohm resistors at one or both ends to the-2V supply. The resistors are in low-profile SIPs thatmount between the DIPs (144 8-pin SIPs per board).ContB (microstore)ContA (branching and tasking)+12 V x 10 A64k x 1 MOS Ram's64k x 1 MOS Ram's(100 ohm terminator resistors)7/11/85is halted. In the event some temperature exceeds 44 degreees C thehave temperature sensors that can be monitored when the Doradoare controlled by the baseboard microcomputer (Located on the BaseBoard)ProcH (Processor bits 0-7)ProcL (processor bits 8-15)DispM (Display color controller)MemX (Map and control)for TTL components. The +12 volts is used for the Ethernet box which is red the Dorado computer.-2 V x 150 A-5 V 300 A+5 V300 A+ 3)#t.%:1$&W0$%:0z@$%:0z$@%:P&$&WO-$%:O @$%:O $@FP&$GO-$FO @$FO $@F1$G0$F0z@$F0z$@#PJEtPJD.-O$3N$-M@$-M$8O$>N$8M$8M$/:O:WO-|I/:I0I9;I:I;I{$?WI{$@tI{$AI{$BI{$CI{$DI{$FI{$Et5{$DX5{$C;5{$B5{$A5{$?5{$>5{$=5{$<5{$;t5{$:W5{$9;5{$85{$75{$55{$45{$35{$25{$1s5{$0W5{$/:5{$.5{$-5{$+5{$*5{$)5{$(5{$'s5{$&W5{$(KJ1(J-!.Lf$/Lf$1sLf$9Lf$;tLf$=Lf$(G6(F (E-.(D.(B(AI*(@-,(?)(=,(<0(;,(:)(993?Wu$r#r !tAICAI30d4H7+2 : <:3e .8 +g5d$ +gd,-d!9 V@tu#t^C#_>#cuH @t > ] FI 8 :1 3e 2I32 4+G1,G 0rG 0G+0G+0rGH1,G4+Gd4Gs1,Gd0VGd0G+ PmeDorado Hardware ManualIntroductionAugust 1, 19851IntroductionDorado is a high performance, medium cost microprogrammed computer designed primarily toimplement a virtual machine for the Mesa language, and to provide high storage bandwidth forpicture-processing applications. Dorado aims more at word processing than at numericalapplications.The microprocessor has a nominal cycle time of 64 ns, and most Mesa opcodes will execute in oneor two cycles; the overall average opcode execution time will be subject to a number ofconsiderations discussed later. Dorado will also achieve respectable performance whenimplementing virtual machines for the Alto, Interlisp, and Smalltalk programming systems,although simple instructions for these run three to five times slower than Mesa.Dorado is implemented primarily of MECL-10K integrated circuits; storage boards use MOS andSchottky-TTL components primarily. Backplanes and storage boards are printed circuits; otherlogic boards are stitchweld in prototypes and multiwire or PC in production machines. Themainframe is divided into sections called Control, Processor, Instruction Fetch Unit (IFU), andMemory, and peripheral control is accomplished by the Disk, Ethernet, and Display Controllersections, as discussed in chapters of this manual. The main data paths, shown in Figure 1, are 16-bits wide (the word size). The control section is shown in Figure 5. The Baseboard section, isused to boot the Dorado, run the clocks, and support the debugging interface from the Alto.The processor is organized around an Arithmetic and Logic Unit (ALU) whose two inputs are theA and B data paths (Figure 1), and whose output is normally routed to the Pd data path. Inputsto A, B, and Pd include all registers accessible to the programmer. In addition, 16-bit literalconstants can be generated on B. B appears on the backplane for communication with the IFU,Control, and Memory sections.The processor also includes a 32-bit in/16-bit out shifter-masker optimized for field insertion andextraction and with specialized paths for the bit-boundary block transfer (BitBlt) instruction.An instruction fetch unit (the IFU) operating in parallel with the processor can handle up to fourinstruction sets with 256 opcodes each; opcodes may independently be specified as one, two, orthree bytes long.Emulator and IFU references to main memory are made through a 4k-word high-speed cache.Main storage can be configured in various sizes up to a maximum of 16 mega words using 256k x1 RAMs.The processor initiates data transfers between main memory and fast input/output devices. 16 16-bit words (Munch) are then transmitted without disturbing the processor data paths in about 1.68ms (28 cycles). New references can be initiated every 8 cycles, so total bandwidth of the memory,533 mHz, is available for devices with enough buffering. fp%5q 5pGf ar ^epX \6& ZM Y U? S8 Q@EA P4+. NiP JH I-M Gb-- E)6 C\ B30 @7J >mC :$9 9000 7f[ 5B 3 0_Q .I +"B )W^ ' $#4 "PB  P I[ ~spU m8 6 &=PR oddJCNFFBLOCKASELLCBSELALUFRSTKALU carryALU[15]{BSEL, FF}Md *Md *Md *QTFF[4:7]FF[4:7]>>TRSHIFTER161616>>{LC}16ALUFM>>{xxx} Source of ControlTask-Specific**{LC}{BSEL}ControlBAALUAddress LogicFF[4:7]0,,FFFF,,0FF,-1-1,,FF{ASEL}{ALUF}Q16R'T'Programmer's View>>>>ALU=0ALU<0SubTaskALU rsh 1ALU lsh 1To devices16R < 0>IOBALUFMShCTIOA, StkPAMuxAMuxBMuxFFRF_WF_ShC_SubTaskShiftControlsRMSTKRSTK[0:3]{FF}RSTK[1:3]StkpSaved StkpRQFF[4:7]Md*T{FF}>>>>>>>>>>>>>>>>>>>ShC16168B+RBaseCnt>>>>>>>>B>Stkp>>>>>>>>>>T*MemBase*TIOA*CntOverflowCnt=0&-1oPipe0Pipe1Pipe2'Pipe3'Pipe4'ConfigDBufooFaultInfo'gh>hgLinkRWCPRegoMemCMemDIFUControlBMuxghoPointers16IOBIOAB>>>>>>>>>>ALUBrLo_BrHi_CFlags_ghMarMuxLoadMcrAB>Mar+>>>>>>>>>>>>>>>>>>>>>>>MapBuf_>>DBuf_MemX>>Store_Map_LoadMcrLoadTestSyndromeFetch_Store_Map_PreFetch_IOFetch_IOStore_MemoryIFU>>To ProcessorTo ControlMd*Fout>>>>>Fin>IFUFetch>10161681681616F/GF/G>16{FF}{FF,ASEL}{ASEL}MultiplyDivideCDivideQ lsh 1Q rsh 1{BSEL}DoradoFigure 1From devices{JCN,FF}>>>>>RdTPC_LdTPC_IM_Link_{FF}MOS_GenOut_BrkIns_>{ASEL}MemX{FF}{shift mask}Md*/0Carry'IOAtten'>>>>{FF}o>IFUTest_{FF}{FF}MemBX>FF[6:7]BR{ASEL}IdPdPipe5'PdA_IdRisIdA_IdTisIdPdId{ASEL}{FF}ProcSRN_B[12:15]IFaddr>B[3:7]MemBIFUMRH_IFUMLH_Id0 or 1by IFU256 x 16256 x 16PCX'Junk'IFUMLH'IFUMRH'BMux>D1ProgView.sil87/28/85012345677654321021001221001233210tKDX 3 (%:  V    $UG d$Et d$C; d$A d$> d$< d$:W d$8 d$5 d$3 d$1s d$/: d$- d$* d$( d$&W d$$ d$! d$ d$s d$: d$ d$ d$V d$ d$ d$ d$ d$ r d$ d$9 d$T dZJ GVf #H6tG)e4<$#H3#H4d\$%:`;t\$7\_$7\_$]Xd_U$\$d\y$]5$]$ |[/ Y#tBf#H823$9$=f=f =f; ;u&W 87$9t8eJ|J= $U $U: $U! $U( $U* $< $UI d$L d$ K$NX $U$K$=ft?<@9$=f@=fE=fD r3Br$r3er1r$r1r/r$r01$/$0 1G$1 $u3e107$+W_$-b5$*:te 2@r$u2I1,rpIKV$sH$UH_y$H_$yGBV$sD$UCy$C$yrEt VJ $ VE$r VE$ G$R$VO-$tS A$sJ$E$sE$B$?$U?{$?{$yA$"sBB$-]$r(+W$ V(E$'sJ-> @-@ 9$V@9$ =$V=]$V=$ ?{$ V>$ VA&$B 7=f$U5+zr$#7$H_$E$#Gf#D#E#I)A G$(H$*HIK$|FYA rD rCK'sE='sC'sA's@='s>'s4K's2's0's/J's-'s+'s*J's(%'<(AI$1 $.$ 3U$ /$r /^y$ /^$ p0r1,$t1=fC$.$>^9$^.@ GX +>dpP]%:`$*:|[/*:\+\L=vrB$9B@=BABC=ft8e 7G6tS|U$7Q7PJ7LD7I$9:W$+:4G$>^H$+W;P9$5&$3$$3$$+|Lv+Lv0WpO7tN:&$-p;t-5's|:(=f$7tS>;^Q$A[$U>;Z$>;Z$y?W\<5W|K2$2]$2$2$dd$utt,,X,,,,,,X1s??7X777XHHtV|sd$"stdr$sd$,ur%| J/: JuV::V::@tY$GfM$ 9@tM$@tM$ ]ASARAQAP AOtANXApW7_'$\d$T$T$2 WW$^ $.|T*RL2_9$9_J$/uZJ /W H;tUH;Qf=|W=ZLQ/LOM;M;-tV?W|S!AuU.|W+WtXX*:ZJ$*W$JR$*BBd$,sA*-d$,,-I?W($d@-(?W#$@-$eKSXKJP$KQfJTt$KJUGfTdGGfSGH;SXGfQGXG:X!\G9!^ G$Z GG$X GG$U GG r,9GGrG:Gr:9G0GG-dGC;GH*GF+GFrG)rGs|U=V$d=tV%: :G%:#G0W :G/:#G#6,G$T$ rMG ,G,s, &9$GuZJGY.GXGVGU9t-#r#9;ub DXtVI|JIIIJDE-$EtE-$EEsEE-$E-O$E-$AVG23,32]$37I|:( +G&t<uBt5@4 =f:8e5<+W6tN{$6tLd$6tP&d$6tQd$<|N!<Lv%? Is0 F[ D7d Bl! >] =/$; ;e; 6Ks 2pY 1O /D\ -z4 *#@ (=$> &s,5 $L " kI = :(  ! s# p? J 6) % ` =]Dorado Hardware ManualOverviewAugust 1, 19853Table 1: MemoriesMemoryCommentsIM(ContB board) IM is a 4096-word x 34-bit (+2 parity) RAM used to store instructions. When written, theaddress is taken from Link and data from B 16 bits at-a-time (1 extra bit and parity from RSTK field).When read, the address is taken from Link, and data is delivered to Link 9 bits at-a-time. The read orwrite is controlled by the JCN field and two or three low bits of RSTK.ALUFM(ProcL board page 11) ALUFM is a 16-word x 6-bit ALU control RAM addressed by the 4-bit ALUFfield. Five ALUFM bits specify 16 boolean or 5 arithmetic operations on A and B. One bit is the inputcarry for arithmetic operations (modifiable by several functions). ALUFM[ALUF] is read onto Pd by theALUFMEM function or both read onto Pd and loaded from B by the ALUFMRW_ function.RM(ProcL and ProcH pages 2-9) RM is a 256-word x 16-bit (+2 parity) RAM used for general storage by alltasks. The normal address is RBase[0:3],,RSTK[0:3]. Data can be read onto A or B and loaded from Pdor Md without using FF. Together with T, RM forms the input to the Shifter.STK(ProcL and ProcH pages 2-9) STK is a 256-word x 16-bit (+2 parity) stack accessible only to the emulator(Task#0), used instead of RM when the BLOCK bit in the microinstruction is = 1. Its address comesfrom StkP, modified by -4 to +3 under control of RSTK.IFUM(IFU pages 6 and 12) IFUM is a 1024-word x 24-bit (+3 parity) decoding memory containing 256 wordsfor each of four instruction sets. The instruction set can be set by the InsSetOrEvent_ function. The low8 address bits are normally an opcode fetched from the cache, but can be loaded from B by the BrkIns_function to read or write IFUM itself. The IFUMLH_ and IFUMRH_ functions load, and theB_IFUMLH' and B_IFUMRH' functions read different bits of IFUM. During normal operation IFUMcontrols decoding of the stream of opcodes and operands fetched from memory relative to BR 31, the codebase.MAIN(MemD and MSA boards) Main storage consists of a 64-row x 4-column x 16-word virtual cache coupledwith one to four 4096k x 16-bit memory modules (using 256k-bit storage chips). Each memory moduleconsists of 2 MSA boards. The IFU and processor independently access the cache, with IFU referencesdeferring to the processor. The processor has two dissimilar methods of reference, one primarily to theCacheD (with "misses" initiating main memory action) and one directly to main memory (invalidatingcache hits on writes, using dirty cache hits on reads). Virtual addresses are transformed to absolute usingthe Map memory. All references leave information in the Pipe (History) memory.BR(MemC board pages 1, and 7-10) A 32-word x 28-bit base register memory addressed by the MemBaseregister. The virtual address for any memory reference is BR[MemBase]+Mar. BR is loaded from Marby the BrLo_A and BrHi_A functions and can be read indirectly onto B via the virtual address left in thePipe after a memory reference (Pipe0 and Pipe1 functions).Pipe(MemC and MemX boards) The 16-entry x 6-word pipe (History) contains trace information left bymemory references. Each entry into the pipe conatins the virtual address, map information, single-errorand double-error information, cache control information, task and subtask that made the access. It isautomatically loaded during any memory reference and can be read onto Bmux by the B_Pipe0, B_Pipe1,B_Pipe2, B_Pipe3, B_Pipe4, B_Pipe5' functions.Map(MemX board pages 12-17) The Map is a 64k-word x 19-bit (+parity) memory used to transform virtualaddesses to absolute. Addressed by VA[8:23], map entries into the pipe contain 16 bits of real pageinformation, 1 bit each of write protect, dirty, and referenced bits. The 16 bits of map can be writtenfrom Bmux with Map_RM/STK and read from Pipe3 after main storage references. fp%5q5pGf$#bsX `vtx ]uxc\ \ZJYG V!x@TgS.8Q> Nx.7M,SKL HxSG?20E6 BxIAR#H?=(>J L<F;AS9 6x7+5UN3c2La0B/DZ-O *x U)W&<'b&O: #jx,2!#E bf@#Z. uxc-7m44L CJ A x:-?;(> ;x?'9'6 6xD51T 2Lx0x2/DI-],<1 )WxB'4 $xQ#jU!` b }x=$ \u26T  x+=b  xRU< =[^Dorado Hardware ManualOverviewAugust 1, 19855Table 3: Data PathsPathCommentsA(ProcL and ProcH pages 2-9) The 16-bit high-true A bus (called "alua" in hardware drawings) may bedriven from T, RM, STK, Q, Id, Md, a small constant between 0 and 178, or the shifter. It is alsopossible to 'or' the low-true shifter output with one of the other A sources. The A bus is totally insidethe processor section, not connected to any other sections of Dorado, and it is one of the two Alu inputs.The RF_A and WF_A functions, which load ShC for subsequent shift operations, receive data from A.Mar(ProcL and ProcH pages 2-9, and IFU pages 8 and 9) The 16-bit Memory Address register transmits thedisplacement for a memory reference from the processor or IFU section to the memory section. Thecontents of Mar and the selected Base register (BR) are added together to get the Virtual address. Alsothe CFlags register, some bits of the Mcr register, and the BR memory in the memory section are alsoloaded from Mar. The processor drives Mar only when it is starting a reference or executing one of theFF functions between 1208 and 1278.B(ProcL and ProcH pages 2-9) The 16-bit B bus consists of one data path inside the processor section (called"alub" in hardware drawings) and another on the backplane (called "Bmux" in hardware drawings); theIOB bus is driven from Alub on Output operations, when it also is an extension of B. Alub and Bmuxmay be directly driven high-true from registers inside the processor; alternatively, Bmux may be drivenlow-true from other sections, in which case the processor receives the data onto alub through inverters (sothe data appears high-true on alub). The BSEL field in an instruction can specify that either T, RM/STK,Q, or Md sources B; other sources and destinations loaded from B are specified in the FF field; BSELand FF are used in combination to specify that a literal 8-bit constant (in either the left or right byte ofthe word with 0's or 1's in the other byte) sources B. The processor computes odd byte parity on alub;Bmux and IOB destinations may store or check the parity computed by the processor. Pd(ProcL and ProcH pages 2-9) The Pd path ("Processor data") is 16 bits wide that receives data from an 8-input multiplexor whose inputs are the Alu output, possibly shifted left or right one bit on Alu shiftfunctions or masked on a shifter operation, io device input data, and the infrequently read registers in theprocessor section. Pd may be written into the T register or the RM or STK memories.Id(IFU page 5) The Id path ("IFU data") is 8 bits+sign extended and used to send arguments from theIFU to the processor for interpretation. It can be routed onto A using ASEL (A_Id, Fetch_Id, Store_Id,or IFetch_RM/STK); alternatively, the TIsId or RIsId functions can be used to replace data from T orfrom RM/STK by IFU datathese functions provide a roundabout method of getting Id onto B.Md(MemD pages 7-15) The Md path ("Memory data") is a 16 bit + 2 bits of parity path and moves datafrom the cache in the memory section into the processor. The processor latches Md and can route it ontoA or B, load it into T and RM/STK, or use it in a shift-and-mask operation.TIOA(ProcH page 23) The TIOA bus ("Input-output address") is driven from the 8 bit TIOA register; itspecifies the io device affected by a Pd_Input or Output_B function.IOB(ProcL and ProcH pages 2-9) The IOB bus ("Input-output bus") is driven from the 16 bit alub on anOutput_B function or received on Pd by a Pd_Input function; it transmits data to or from an io device.Fout(MemD pages 7-15) "Fast output bus" is a 16 bit wide path with no parity and transmits data from theCacheD to a fast output device. The DispY and DispM are the only boards that use the Fast output. 16words (Munch) of data are transferred on each output.Fin(MemD pages 7-15) "Fast input bus" is a 16 bit wide path with no parity and transmits data from a fastinput device to the CacheD. Presently, there are no fast input devices except for the FIO test board thatis used only for debugging.Sout(MemD pages 7-15) "Storage output bus" is a 16 bit wide bus that transmits data from the CacheD toMSA storage modules.Sin(MSA pages 4-11) "Storage input bus" is a 16 bit wide bus that transmits data from the MSA storage modules tothe CacheD. fp%5q5pGf#bsX `vtx ]uxxC\ 9[\ZfMXPW^/2 Tyx2x,R]QqcO;)Ni`LLXLLXL Jxx?H|HFU EtE"CKBl.;@N?d]=N<\S 9wxx (9 9wx-9 9wx37O6oV4T 2x!1i2x#12xA0a.d-zG *x$*>*x)j*>*x8)`'K $x$$Qi$x'$Q$x+$Q$x0#$D ?xx *i ?x, ?x0 ?x X xxxFR8-5 xxex-e_  x x!9xAx 1x=  xN  xI M  <]Dorado Hardware ManualOverviewAugust 1, 19856TimingThe terminology used in discussing timing is as follows:clockThe 32 ns (nominal) atomic time period of the machine. Clock period can becontrolled by the baseboard microcomputer or through the manifold system asdiscussed in the "Dorado Debugging Interface" document.1cycleThe duration of instructionstwo clocks or 64 ns except for instructions thatread/write IM or TPC.t0The instant at which MIR (MicroInstruction Register) is loadedthe beginning of acycle.t1The next instant after t0always one clock later.t2The instant following t1one clock after t1 except for instructions that read/write IMor TPC. Additional clocks intervening for these special cases, which only affect thecontrol section, are denoted by t1a, t1b, etc.t3, t4Subsequent instants for a instruction. t3 of the previous instruction coincides with t1of the current instruction; t4 with t2.First half cycleThe interval from t0 to t1 (or t2 to t3).Second half cycleThe interval from t1 to t2 (or t3 to t4).As implied by this terminology, Dorado initiates a new instruction every cycle. Instructions arepipelined, requiring a total of three cycles for execution. Timing for a typical instruction is shownin Figure 7. At t-2, the next instruction address is determined and instruction fetch from IMbegins; at t0, the instruction is loaded into MIR from IM. During the first half cycle, the selectedregister is read from RM or STK, and at t1 is loaded into a register. During the next two clocks(t1-t3), addition is performed in the ALU; at t3 the result is loaded into a register for writing intoRM/STK or T. During the final clock, RM is written.Since a new instruction begins before the previous one finishes, paths exist to bypass the registerbeing written if the following instruction specifies it as a source (These paths, inaccessible to theprogrammer, are not shown in Figure 1).Most registers load from B at t3 (i.e., at the mid-clock of the cycle following the load instruction).These may source B in the instruction after they are loaded. The load information and data arepipelined into the next cycle, as described above. Registers loaded at t2 may be used during thefirst half-cycle of the following instruction. Usually, this type of register is used for some type ofcontrol information, since control registers are normally clocked at t0 (= t2 of previousinstruction), data-oriented registers at t1 (t3 of previous instruction).Table 4 summarizes the time at which loading takes place and some other information. fp%5q5pGf bs ^p8 g[K6KYL,KW7Xu gUpK' &KS gR"QuKR"p$QUR"(@QR" /UQR"%KPW gNMuKNpMuNp gLL5uKLpxL5uLpxL5uLp KJNKI-!HupI-HupI- gG?FuG?pFuKG?px FuG?p-FuKEtpDuEtpDuEtp gCAxARuApARuApARuApARuAp g@>Jx=u>Jp=u>Jp=u>Jp=u>Jp :6+ 90Q 7f6u7fpJ 5 5u5pS 33Cu3p7 21yu2p1yu2p)1yu2p6 0;4 ,): *:+ )4' %%5u%p. #J "-+!u"-p b!F F up up *@up@up ~T m>PDorado Hardware ManualOverviewAugust 1, 19857Table 4: Load TimingRegister/ TaskLoad Data LoadCommentMemorySpecificTimeSourceControlMIR*not0IMJCNHolds current instructionCIAnot0TNIA,BNPCJCNHolds current instruction addressCIAinc*not1CIATPCI*not2TNIA, CIATPCyesFHCTPCIHOLDt2LINK(??)JCN,BReading/writing takes 3 cyclesLinkyest2BFFAlso loaded by CALL, RETURN, anddispatchesreadout valid t1 to t3IMnoBJCNReading/writing require 3 cyclesCTASKnot0NextSwitchCurrent taskCTDnot1CTASKCurrent task delayedReadynot0PEncSwitchTask-ready flipflopsStkPnot2BFFNew value read if it changes in thesame instructionRBaseyest2F2F1RAM writte at t3, bypassedCntnot2F2F1Br cond to sub 1 and testBFFALUFMnot2BFFAddressed by ALUFThe output is valid t1 to t3TIOAyest2BFFReadout valid till t3MemBXnot2F2F1Readout valid till t3MemBaseyest2F2F1Readout valid till t3MemBase xor 1FFShCnot3A,BFFRF_A, WF_A, ShC_Bt1FFASEL,BSELQnot3BFF,BSELt3ALU[15],,Q[0:14]FFMultiplyt3Q[1:15],,ALUcryFFDividet3QFFQ rsh 1, Q lsh 1RMnoSHCPd,MdLC,RSTKBypassedSTKnoSHCPd,MdLC,RSTKBypassedTyesSHCPd,MdLC,FFBypassedIFUMnoSHCBFFIFUMLH_/IFUMRH_BrkInsnot2BFFPC*not3BFFLevel F PC loaded, level X readBrnot2AFFBrLo_/BrHi_, _Pipe0, _Pipe1MapBuf*noFHCBASEL, FAWritten on Map_, TestSyndrome_,ProcSRN_, LoadMcrDBufnoFHCBASEL, FAWritten on Store_Mdyest5cacheBypassedCFlagsnot2MarFFFor debugging, initializationMcrnot3Mar, MapBufFFFor debugging, initializationAsrnnot2AsrnAddresses the pipe for ring refsProcSRNnot3MapBufFFAddresses the pipe for Pipe0 to Pipe5TestSyndromenot3MapBufFFFor debugging error correctionPipe0not3Br, etc.ASEL, FAWritten on ref., B_Pipe0Pipe1not3Br, etc.ASEL, FAWritten on ref., B_Pipe1Pipe2not3ASEL, FAWritten on ref., B_Pipe2Pipe3not14mapASEL, FAValid after any storage access or Map_Pipe4not14,t48map, ECASEL, FAValid after any storage accessPipe5not3,t4cacheASEL, FAWritten on ref., B_Pipe5*Cannot be read as data by the processor fp%5q5pGf#RbsX ^tx'G1 ]nxxxZP'G< ZuxZP'<1 YLxZP'<1! WxZP'< V<xZP'< U*xZP'SZP'<1 RhZP<'11Q < Ox<P'<1 NFxZP'<1 LxZP'<1 KxZP'<1 J#ZP<'1#1H GbZP'1 FZP'1D<' C@xZP'11A @~ZP<'1 ?ZP'1 =ZP'1<\' :ZP<'19P<' 89ZP<'6ZP'<1<5xZP'<14ZP'<1 2ZZP<'1 1UZP<'1 /xZP<'1 .<xPP'<1 -3<xZP'< +ZP<'1 *rxZ<'<1 )xZP<'11' &OxZP<'1 $xZP<'<1 #xZP'<1 "-xZP '<1 xZP'<1 kxZP'<1%  xZP'<1 xZP<'1 IxZP<'1 xZP<'1 xZP<'1 'xZP<'1 xZP<'1 (n ;VDorado Hardware ManualOverviewAugust 1, 19858Instruction FieldsThe 36-bit instruction is divided into the following fields:Table 5: Instruction FieldsFieldSizePurpose (may have other effects, described below)RSTK4 bitsSelects RM register to be read and/or writtenALUF4 bitsSelects ALU function or shifter operationBSEL3 bitsSelects source for BmuxLC3 bitsControls source and loading of RM and TASEL3 bitsSource/destination control for AmuxBLOCK1 bitBlocks from a higher task to the next highest piroritytask. Selects stack operations for task 0.FF8 bitsFunction FieldJCN8 bitsJump controlP0 and P12 bitsParity Total34 bits + 2 parity bitsThe above instruction layout emphasizes compactness at the expense of programming flexibility.The following comments explain some of these tradeoffs1.The RSTK field specifies only four of the eight address bits needed for addressing RM. Theother four are taken from the RBase register (loaded by a function). In the emulator task,BLOCK causes STK to be used instead of RM, and RSTK is decoded to cause modifications ofStkP.2. ALUF addresses the 16-word ALUFM memory in which 16 of 26-odd useful ALU operationsare stored. For the shift operation decode of ASEL, the first three bits of ALUF select the kindof shift, while the ALUFM address is forced to 168 or 178.3. BSEL decodes the most common data sources for B. Less common B sources are selected byFF, and then BSEL encodes one of several destinations for the source.4. ASEL specifies the source and destination for A. The default source is the RM addressselected by RSTK. Four ASEL decodes specify the most common memory operations, where thevirtual address is BR[MemBase]+A. These decodes consume the two leading bits of FF to specifyalternate sources (T or Id) or less frequent memory operations. The remaining four ASELdecodes select alternate sources T, Id, or the shifter, where the shifter decodes work incombination with ALUF, as discussed later. fp%5q5pGf bs ^px<>x;A>x9Cx8x7x5* 2pp1B 0K .Q )s &Op>' $7# "; HA } 6>TRSHIFTER161616>>{LC}16ALUFM>>{xxx} Source of ControlTask-Specific**{LC}{BSEL}ControlBAALUAddress LogicFF[4:7]0,,FFFF,,0FF,-1-1,,FF{ASEL}{ALUF}Q16R'T'Programmer's View>>>>ALU=0ALU<0SubTaskALU rsh 1ALU lsh 1To devices16R < 0>IOBALUFMShCTIOA, StkPAMuxAMuxBMuxFFRF_WF_ShC_SubTaskShiftControlsRMSTKRSTK[0:3]{FF}RSTK[1:3]StkpSaved StkpRQFF[4:7]Md*T{FF}>>>>>>>>>>>>>>>>>>>ShC16168B+RBaseCnt>>>>>>>>B>Stkp>>>>>>>>>>T*MemBase*TIOA*CntOverflowCnt=0&-1oPipe0Pipe1Pipe2'Pipe3'Pipe4'ConfigDBufooFaultInfo'gh>hgLinkRWCPRegoMemCMemDIFUControlBMuxghoPointers16IOBIOAB>>>>>>>>>>ALUBrLo_BrHi_CFlags_ghMarMuxLoadMcrAB>Mar+>>>>>>>>>>>>>>>>>>>>>>>MapBuf_>>DBuf_MemX>>Store_Map_LoadMcrLoadTestSyndromeFetch_Store_Map_PreFetch_IOFetch_IOStore_MemoryIFU>>To ProcessorTo ControlMd*Fout>>>>>Fin>IFUFetch>10161681681616F/GF/G>16{FF}{FF,ASEL}{ASEL}MultiplyDivideCDivideQ lsh 1Q rsh 1{BSEL}DoradoFigure 1From devices{JCN,FF}>>>>>RdTPC_LdTPC_IM_Link_{FF}MOS_GenOut_BrkIns_>{ASEL}MemX{FF}{shift mask}Md*/0Carry'IOAtten'>>>>{FF}o>IFUTest_{FF}{FF}MemBX>FF[6:7]BR{ASEL}IdPdPipe5'PdA_IdRisIdA_IdTisIdPdId{ASEL}{FF}ProcSRN_B[12:15]IFaddr>B[3:7]MemBIFUMRH_IFUMLH_Id0 or 1by IFU256 x 16256 x 16PCX'Junk'IFUMLH'IFUMRH'BMux>D1ProgView.sil87/28/85012345677654321021001221001233210tKDX 3 (%:  V    $UG d$Et d$C; d$A d$> d$< d$:W d$8 d$5 d$3 d$1s d$/: d$- d$* d$( d$&W d$$ d$! d$ d$s d$: d$ d$ d$V d$ d$ d$ d$ d$ r d$ d$9 d$T dZJ GVf #H6tG)e4<$#H3#H4d\$%:`;t\$7\_$7\_$]Xd_U$\$d\y$]5$]$ |[/ Y#tBf#H823$9$=f=f =f; ;u&W 87$9t8eJ|J= $U $U: $U! $U( $U* $< $UI d$L d$ K$NX $U$K$=ft?<@9$=f@=fE=fD r3Br$r3er1r$r1r/r$r01$/$0 1G$1 $u3e107$+W_$-b5$*:te 2@r$u2I1,rpIKV$sH$UH_y$H_$yGBV$sD$UCy$C$yrEt VJ $ VE$r VE$ G$R$VO-$tS A$sJ$E$sE$B$?$U?{$?{$yA$"sBB$-]$r(+W$ V(E$'sJ-> @-@ 9$V@9$ =$V=]$V=$ ?{$ V>$ VA&$B 7=f$U5+zr$#7$H_$E$#Gf#D#E#I)A G$(H$*HIK$|FYA rD rCK'sE='sC'sA's@='s>'s4K's2's0's/J's-'s+'s*J's(%'<(AI$1 $.$ 3U$ /$r /^y$ /^$ p0r1,$t1=fC$.$>^9$^.@ GX +>dpP]%:`$*:|[/*:\+\L=vrB$9B@=BABC=ft8e 7G6tS|U$7Q7PJ7LD7I$9:W$+:4G$>^H$+W;P9$5&$3$$3$$+|Lv+Lv0WpO7tN:&$-p;t-5's|:(=f$7tS>;^Q$A[$U>;Z$>;Z$y?W\<5W|K2$2]$2$2$dd$utt,,X,,,,,,X1s??7X777XHHtV|sd$"stdr$sd$,ur%| J/: JuV::V::@tY$GfM$ 9@tM$@tM$ ]ASARAQAP AOtANXApW7_'$\d$T$T$2 WW$^ $.|T*RL2_9$9_J$/uZJ /W H;tUH;Qf=|W=ZLQ/LOM;M;-tV?W|S!AuU.|W+WtXX*:ZJ$*W$JR$*BBd$,sA*-d$,,-I?W($d@-(?W#$@-$eKSXKJP$KQfJTt$KJUGfTdGGfSGH;SXGfQGXG:X!\G9!^ G$Z GG$X GG$U GG r,9GGrG:Gr:9G0GG-dGC;GH*GF+GFrG)rGs|U=V$d=tV%: :G%:#G0W :G/:#G#6,G$T$ rMG ,G,s, &9$GuZJGY.GXGVGU9t-#r#9;ub DXtVI|JIIIJDE-$EtE-$EEsEE-$E-O$E-$AVG23,32]$37I|:( +G&t<uBt5@4 =f:8e5<+W6tN{$6tLd$6tP&d$6tQd$<|N!<Lv>>>>>>>>>>>>>between R and T. When shift control istaken from ShC, ShC[2] = 1 selects T for SHAand ShC[3] = 1 selects T for SHB. When the>>The 32-bit quantity SHA..SHB is then left-shiftedshift 4, and shift 2 controls.through an 8-in multiplexor controlled by the shift 8,shift is FF-controlled, SHA and SHB are takenfrom BSEL as shown in the table below.BSEL.0=1BSEL.1BSEL.2when BSEL.0 is 1, and thesource for B is changed to Q.RF_ and WF_ are intended for use with "reasonable" values of P and S.undefinedPdthe Pd multiplexor when shifting. One ofexcept when BSEL.0 is 1 inD1Shifter.silFigure 4Shifter9/5/79stZJ 0WP0WR 0WK 9;S|$:R_$$VX p=)tY+[f$)Gf0WJ-0WT #Y.#PJ0WN)X:W|PZ:WPZ*:pS0WK$0WM$0WR_$7|P7P/:T$"sY @$#P&$(M_$(M_$/:M$ ([C$ :Vv :Vv7J=7J=W$Z& r$)tO#H5",.)FI(a`$/:^.$U(^ $(^ $y)p_0t`.0_+0^$0b,2C(2AI%2@-(2?'2=!2<\_U$ZU$[C$ [fWU$VCU$W_$ W9[C$9Z$9Z&$9Y$9Y $9X|$9W$9W_$VVf$Z$:X$U:YVY$TSRVB6A*Y$UJ$O-/4s44$5+W4346 ($$33B($91 11$1+1311($#030/^($#-*:-4--%($s++$++W+3+V0V-V+*($*^($3($$(+W((%($3(9;1$:W+$9;*@$:W.A$;t.9;*^$:W(H$99;(%@$;t(r1@$r+$r*$ .A$.e9-I;t, D@:Vp_ $t_ \ZXVf=R$=T $=U&$=VC$=W_$=X|$=Y$=Z$?Q$ 9;L$9L$9R_$?Vr$s-s00-|XWT=R'sUZ'sLv>O=>PZ>Qv>R>S>T>U>WtN'L,K+|VveT=tGf1E-FI6J-I&9((s((H$ (H$ V(H$ !(H$ )(H$ 0(H$ 8(H$ :W)A$;t';t&E*:0 AV2Bf);t-=u+ #r#r>uH_`Dorado Hardware ManualProcessor SectionAugust 1, 198510Processor SectionThe processor section implements most registers accessible to the programmer and decodes allinstruction fields except JCN. The FF field of the instruction is also decoded by the control,memory, and IFU sections.Read this chapter with Figure 1 in front of you.The processor section contains the Q, ShC, Cnt, StkP, and MemBX registers, the T, RBase,MemBase, and TIOA task-specific registers, and the ALUFM, RM, and STK memories. Itcontains the arithmetic and logic unit (ALU) and the shifter.The processor communicates with the control, memory, and IFU sections via B; with io devicesvia the IOB bus. It exports MemBase and Mar to the memory system for addressing, IOA todevices for io addressing, and branch conditions to the control section. It imports Md from thememory system and Id from the IFU.RM and STK Memories, RBase and StkP RegistersRM ("Register Memory," sometimes called "R") is the memory most easily available tomicroprograms; it stores 256 words x 16 data bits with odd parity on each byte of data. Each taskget 16 R memorys to work with. RM is read at t0 and latched at t1. Data may be routed to A, B,or the shifter, and branch conditions (see "Control Section") test the sign bit (R<0) and low bit (ROdd). RM may be written between t3 and t4 with data from Md or Pd.The RM read address is the contents of the selected Rbase for bits 0, 1, 2, and 3, and the RSTKfield of the mircoinstruction word for bits 4, 5, 6, and 7. The contents of RBase[0:3], and themicrocode value of RSTK[0:3] select 1 of 256 R memorys to use. Normally, this read address is also used for the write part of the instruction (if any). However,two groups of FF decodes discussed below modify the write address.The RBase_SC function loads RBase with FF[4:7], selecting any block of 16 registers; RBase_Bloads RBase from B[12:15]; Pointers_B loads RBase from B[12:15] while also loading MemBasefrom B[3:7] (Previous RBase value is used for both the read and write portions of the instruction.).The STK memory (sometimes called "stack") is accessible only to task 0. Since the emulatorcannot block, the instruction bit interpreted as BLOCK for I/O tasks is instead interpreted asStackSelect. When StackSelect is a 1, RM is disabled and STK used instead. Like RM, STK stores256 words x 16 data bits with odd parity on each byte of data. STK is addressed by the 8-bitStkP register, and RSTK controls the adjustment of StkP; StkP may be decremented orincremented by any value between 4 and +3.Unadjusted StkP is always the read address and normally the write address, but theModStkPBeforeW FF decode forces adjusted StkP to be used for the write. STK is divided intofour separate regions, each 1008 words long. Valid addresses are 1 to 778 within each region. Thatis, StkP[0:1] select the region, stack overflow occurs at the onset of a instruction that wouldincrement StkP[2:7] > 778, and underflow occurs when location 0 is either read or written or whenStkP[2:7] is decremented below 0. fp#$q5pG?f ar ^ep:" \R Z:W^q0 Sp*. R"*) PW= L,0 K/) IPI G" C@s- ?pN?w?;?wU?7 >'; <8);t<8p;t<8p :n%? 8"8t8p8t8p 5UR 3 S 1@ .MO ,B )C 'F@ %|Q " < ?[ tM E  $ / + q p?$@$ qp+  t p"t p CY x txpH ! g<[\Dorado Hardware ManualProcessor SectionAugust 1, 198511StkP[2:7] are initialized to 0, denoting the empty stack. A push could do StkP_StkP+1 and writein one instruction. A pop does StkP_StkP1, and the item being popped off can be referencedin the same instruction if desired.Table 6: RSTK Decodes for Stack OperationsRSTK[0]0 = no underflow on StkP = 0 at start or end1 = underflow when StkP originally 0 or finally 0.RSTK[1:3]Meaning 0no StkP change 1StkP_StkP+1 2StkP_StkP+2 3StkP_StkP+3 4StkP_StkP4 5StkP_StkP3 6StkP_StkP2 7StkP_StkP1In other words, RSTK[1:3] treated as a signed number are added to StkP[2:7] (StkP[0:1] don'tchange.). In the task 0, an attempt to underflow or overflow the stack generates the signalStkError.StkError generates the HOLD condition and wakes up the fault task (task 178) to deal with thesituation, so the instruction causing StkError has not been executed when the fault task runs.StkUnd and StkOvf are remembered in flipflops read by the Pd_Pointers function. These getcleared when the next stack operation is executed by the emulator. The fault task can read themto decide whether stack underflow or overflow action is necessary.Interpretation of underflow: StkP eq 0 denotes the empty stack. A stack adjustment may occureither by itself or with a read or write stack reference. StkP originally equal 0 underflows if thetop of stack is read or written; decrementing StkP below 0 is always an underflow error; StkPequal 0 after modification underflows iff writing at the modified address.StkP can be loaded from B[8:15] using the StkP_B function; however.StkP is saved at t2 of an instruction dispatched to by the IFU. The saved value may be reloadedinto StkP at t2 by the RestoreStkP function.Two groups of FF decodes change the RM address for the write portion of an instruction.The first group of 16 FF decodes forces the write address to come from RBase[0:3],,FF[4:7]. Thisallows different registers in the same group of 16 to be used for the read and write portions of theinstruction, or allows STK[StkP] to be used for the read portion and any of the 16 registerspointed to by RBase in the write portion.The second group of 16 FF decodes forces the top four write address bits to come from FF[4:7].The complete RM write address becomes FF[4:7],,RSTK[0:3]. Note that there is no way to read RM and write STK in one instruction.The RisId FF decode causes Id to be substituted for RM/STK in the A, B, or shifter fp#$q5pG?f bJ `S? ^#:[sX*Wu~t,~VD2Su~Pt~ O=~ M~ L5~ J~ I-~ G~ F$~ Bp&6 A. O ?dsp ;J;et;p  :'2, 8]E 6[ 4B 1UT /(qp - qpq +p0 (`C $$at$p7 #$ "t#$p  M cA ` 8$ )  T ; UF ? =]o1Dorado Hardware ManualProcessor SectionAugust 1, 198512multiplexing.There are branch conditions to test R[0] (R<0) and R[15] (R odd). These branch conditions areunaffected by the RisId FF decode; actual data from RM/STK is tested.Cnt RegisterThe 16-bit Cnt register is provided for use as a loop counter. Since it is not task-specific, I/Otasks must save and restore it.Cnt can be decremented and tested for 0 by the Cnt=0&1 branch condition; loaded fromB[0:15] or from small constants 1 to 16 (FF decodes), and read onto the Pd path (into T orRM/STK) by an FF decode.Q RegisterThe 16-bit Q register is provided primarily for use as a shift register with multiply and divide, butwill probably be used more widely by the emulator. Since it is not task-specific, I/O tasks mustsave and restore Q if they modify it.Q can be read onto B (BSEL) or onto A (FF); it can be loaded from B (FF) and when FFspecifies an external B source in the memory, ifu, or control sections, it can also be loaded from B(BSEL). Q can be left-shifted or right-shifted one (bringing 0 into the vacant bit) by two FFdecodes.T RegisterThe 16-bit T register is the primary register for data manipulation in the processor. Since it istask-specific I/O tasks do not have to save and restore it. T can be read onto B (BSEL) or A(ASEL); it can be loaded from Pd or Md (LC).BSEL: B Multiplexor SelectBSEL normally selects one of the "internal" processor sources for B, as shown in the "Primary"column in the table below (Note that although Md originates in the memory section, it is latchedby the processor and appears as an internal B source.). However, the FF field can be used tosubstitute some other source external to the processorthere are many "external" sources in thecontrol, IFU, and memory sections, and the FF decodes for these are 160 to 177. fp#$q5pG?f b ^A \q p; Ws TVpb R O> MO> K Fks Bp [ A.3. ?d% ;A :'%? 8]H 6 1ys .pJ ,<[ *r, %Xs !pA -3 Q8% %: O& q A ?p =3 ;! 8]@ 6I 3Cv 0tV .b -zK+ +8 )4*G 'h &,d $  "F Is4HtIspHt GpKGtGp E BlI= sX%:9t&,6  :8 &,*6::6 &,*6::5 &,*6::3 &,*6::2 &,*6::0 :. ::-z :+ :*r -:( :'i :% :$a :" :!Y :>:Z<  p O AB vtvp$,  0tp" V oP  3 P @ <^kDorado Hardware ManualProcessor SectionAugust 1, 198517external sources from the memory and control sections are not due to a slower data path. InternalA sources except shifter are ready in time for arithmetic. Unless explicitly disabled by theFreezeBC function, the branch conditions ALU<0, ALU=0, Carry' (ALU carry out'), andOverflow are available for testing on the ContA board at t3.The Overflow branch condition, defined as carry-out from bit 0 unequal to carry-out from bit 1, istrue iff a signed arithmetic operation yields an incorrect result.Normally, the ALU is routed directly onto Pd, and Pd is then written into either T or RM/STK.However, several functions route ALU output shifted left or right 1 position onto Pd. Note thatthe ALU output of this instruction are used (not the previous one) and that ALUcarry isundefined on a logical ALU operation. The right shifts are:ALU rsh 1(0 onto Pd[0])ALU rcy 1(ALU[15] onto Pd[0])ALU arsh 1(ALU[0] onto Pd[0] preserving the sign)ALU brsh 1(ALUcarry onto Pd[0])Multiply(ALUcarry onto Pd[0]).The left shifts are:ALU lsh 1(0 onto Pd[15])ALU lcy 1(ALU[0] onto Pd[15])Divide(Q[0] onto Pd[15])CDivide(Q[0] onto Pd[15]).Note: The barrel shifter discussed in the "Shifter" section also use the Pd multiplexor formasking, so it is illegal to combine barrel shifts and ALU shifts in the same instruction.Note: ALU<0, ALU=0, Carry', and Overflow branch conditions test the ALU output of theprevious instruction executed by the task and any shifting or masking that takes place in the Pdinput multiplexor does not affect the result of these branch conditions.Note: The value of Carry' and Overflow change only on arithmetic ALU operations. However,ALU_A may be either an arithmetic or a logical operation; in order to use XorCarry withALU_A, we will probably use the arithmetic form of ALU_A, but the consequence of this is thatCarry' will change on ALU_A. Programmers will have to be wary of this.Note: Overflow is implemented correctly only for the A+B, A+B+1, A-B, and A-B-1operations; other arithmetic ALU operations (A+1, A-1, 2A, 2A+1, etc.) may modify the branchcondition erroneously. fp#$q5pG?f bI `S./ ^/% \:\1t\p Yo_ WB T3)4 RhA PaPGPA N|N3:Kt~ :J~ :H| ~:F ~ :Et~ B%p:>t~ :=S~ :;~::K~ 6qp9 51+/ 1qpB /qpX .*qp. *qp1q p (9 '#9$ %XG !qpE \ Qd @=KDorado Hardware ManualProcessor SectionAugust 1, 198518LC: Load Control for RM and TThis field controls the loading and source selection for the RM/STK memory and T register. Theeight combinations are:Table 10: LC DecodesLC Meaning0No Action1T_Pd2T_Md, RM/STK_Pd3T_Md4RM/STK_Md5T_Pd, RM/STK_Md6RM/STK_Pd7T_Pd, RM/STK_PdThe only missing combination is T_Md, RM/STK_Md. T_Md, RM/STK_Md can beaccomplished by combining an LC value of 5 with the T_Md FF decode. It is illegal to useT_Md with other LC decodes.FF: Special FunctionThis field is the catch-all for functions not otherwise encoded in the instruction. For consistencywith the hardware implementation, the 8-bit FF field is shown below as a two-bit field FA (=FF[0:1]) and two 3-bit fields, FB (= FF[2:4]) and FC (= FF[5:7]). Field values are given inoctal.The FF field is interpreted as a function if:(BSEL not selecting a constant) andJCN does not select a "long" goto or callWhen ASEL selects one of the memory references, the FF decode is forced to be that of FA=0because the FA field specifies the source for A or alternate memory reference in this case.The decoding assignments have been made with the following considerations:Functions that source the external BMux are grouped for easy decode of the signal thatturns off the processor's B-multiplexors.Operations that might be useful in conjunction with a memory reference are put in thefirst 64 decodes (FA=0) since FA is decoded as zero on memory references.Functions decoded by different hardware sections are arranged in groups to reducedecoding logic. fp#$q5pG?f bs ^p#< \#+YsX:Vgu:S_t:Q:PW:N:MO:K:JG:H Etp8 C: A =s :'pS 8]K 6Y 4 1U-:-#:,) (R &2) #jJy"4y.)yUyIy'*y(  9 (9 9.  9 x;YDorado Hardware ManualProcessor SectionAugust 1, 198520Table 11c: FF Decodes (FA = 1)FBFCAction*The following 8 FF decodes drive Mar from A.20-1Unused2 2CFlags _ A' (see Figure 10) (Mar must be stable during prev. instr.)2 3BrLo _ A. BR[16:31] _ A[0:15]2 4BrHi _ A. BR[4:15] _ A[4:15]2 5LoadTestSyndrome from DBuf (see Figure 10)2 6LoadMcr[A,B] (see Figure 10)2 7ProcSRN _ B[12:15]3 0InsSetorEvent _ B. If B[0] = 0, then B[4:15] are controls for EventCntA and EventCntB;if B[0] = 1, then B[6:7] are loaded into the IFU's InsSet register.3 1EventCntB _ B or equivalently GenOut_B (General output to printer, etc.)3 2Reschedule3 3NoRescheduleB data must setup during previous instruction and not glitch when writing IFUMLH/RHsee IFU section.3 4IFUMRH _ B. Packeda_B.5, IFaddr'_B[6:15]3 5IFUMLH _ B. Sign_B.0, PE[0:2]_B[1:3], Length'_B[4:5], RBaseB'_B.6,MemB_B[7:9], TPause'_B.10, TJump_B.11, N_B[12:15]3 6IFUReset. Reset IFU3 7BrkIns _ B. Opcode_B[0:7] and set BrkPending4 0UseDMD (see "Control Section")4 1MidasStrobe _ B (see "Control Section")4 2TaskingOff4 3TaskingOn4 4StkP _ B[8:15]4 5RestoreStkP4 6Cnt _ B (overrules Cnt=0&1 in the same instruction)4 7Link _ B (overrules loading of Link by Call or Return in same instruction)5 0Q lsh 1 (Q[0:14] _ Q[1:15], Q[15] _ 0)5 1Q rsh 1 (Q[1:15] _ Q[0:14], Q[0] _ 0)5 2TIOA[0:7] _ B[0:7] (Note: loaded from left-half of B)5 35 4Hold&TaskSim _ B (Hold reg _ B[0:7], Task reg _ B[9:15].See "HOLD and Task Simulator")5 5WF _ A (load ShC with write-field controlssee "Shifter")5 6RF _ A (load ShC with read-field controlssee "Shifter")5 7ShC _ B (see "Shifter")6 0B _ FaultInfo'. B[8:11]_SRN for 1st fault, B[12:15]_number of faults6 1B _ Pipe0 (B_VaHisee Figure 10)6 2B _ Pipe1 (B_VaLosee Figure 10)6 3B _ Pipe2' (see Figure 10)6 4B _ Pipe3' (B_Map'see Figure 10)6 5B _ Pipe4' (B_Errors'see Figure 10)6 6B _ Config' (see Figure 10)6 7B _ Pipe5' (see Figure 10)7 0B _ PCX'7 1B _ EventCntA' (see "Other IO and Event Counters")7 2B _ IFUMRH' (low part of IFUM)7 3B _ IFUMLH' (high part of IFUM)7 4B _ EventCntB' (see "Other IO and Event Counters")7 5B _ DBuf (normally non-task-specific data from last Store_  see "Memory")7 6B _ RWCPReg (= Link_B' and B_CPReg)7 7B _ Link fp#$q5pG?fbsX ^u9 [t- Zf9 X9> W^9 U9 TV9 R9  QN9 O9 1NFC L9? K>9 I9 H6W F9# E-9=C1 B%9 @9' =9 <9  :9 9 9 79 69 494 29F 1y9% /9$ .q9vt ,9 +i98) (`97 &96 %X9 "P9D 9 H9 9 @9 9# 89 9 09 91 (9 9  91 9I 9" 9 p;\>Dorado Hardware ManualProcessor SectionAugust 1, 198521Table 11d: FF Decodes (FA = 2)FBFCAction0-1RBase _ FF[4:7]2-3Replace RMaddr[0:3] by FF[4:7] for write of RM.Forces RM to be written even if STK was read.4TIOA[5:7] _ FF[5:7] (TIOA[0:4] unchanged)50-3MemBaseX _ FF[6:7](MemBase[0] _ 0, MemBase[1:2] _ MemBX[0:1], MemBase[3:4] _ FF[6:7])54-7MemBX _ FF[6:7]60-16 2Pd _ ALUFMRW (Pd _ ALUFMEM as below, ALUFMEM _ B.8, B[11:15])6 3Pd _ ALUFMEM (Pd.0 _ DMux data, Pd.8 and Pd[11:15] _ ALUFMEM[ALUF])6 4Pd _ Cnt (If Cnt=0&1 in same instruction, unmodified value is read)6 5Pd _ Pointers (Pd[1:2] _ MemBX, Pd[3:7] _ MemBase,Pd[8] _ StkOvf, Pd[9] _ StkUnd, Pd[12:15] _ RBase)6 6Pd _ TIOA&StkP (Pd[0:7]_TIOA, Pd[8:15]_StkP; if the instruction modifies StkPconcurrently, the MODIFIED value is read)6 7Pd _ ShC7 0Pd _ ALU rsh 1 (Pd[0] _ 0)7 1Pd _ ALU rcy 1 (Pd[0] _ ALU[15])7 2Pd _ ALU brsh 1 (Pd[0] _ ALUcarry)7 3Pd _ ALU arsh 1 (Pd[0] _ ALU[0] preserving sign)7 4Pd _ ALU lsh 17 5Pd _ ALU lcy 17 6Divide (Pd[0:15]_ALU[1:15],,Q[0]; Q[0:15]_Q[1:15],,ALUcarry)7 7CDivide (Pd[0:15]_ALU[1:15],,Q[0]; Q[0:15]_Q[1:15],,ALUcarry')Table 11e: FF Decodes (FA = 3)0-3MemBase _ FF[3:7]4-5Cnt _ small constant (Cnt[0:10] _ 0, Cnt[11] _ 0 if FF[4:7] # 0 else 1,Cnt[12:15] _ FF[4:7]; i.e., values of 1 to 16 are loadable)6-7Wakeup[n]  Initiate wakeup request for task FF[4:7] fp#$q5pG?fbsX ^u9 [t9 Zf9/X- W^9) U9TVC R9 O9 NF9; L9A K>9B I90H62 F9KE-) C9 B%9 @9 ?9 =9. <9 :9 9 96 7974^sX 12t9 /9G.*< ,94T *:)=S+Dorado Hardware ManualProcessor SectionAugust 1, 198522Multiply and DivideThe Multiply, Divide, and CDivide functions operate on unsigned 16-bit operands. Unsignedrather than signed operands are used so that the algorithms will work properly on the extra wordsof multiple-precision numbers.The actions caused by these functions are as follows:Multiply:Result _ ALUCarry..ALU/2Q _ ALU[15]..Q/2Next branch address _ whatever it is OR 2 if Q[14] is 1.Divide, CDivide:Result _ 2*ALU..Q[00]Q _ 2*Q..ALUCarry -or- 2*Q..ALUCarry'Complete examples for Multiply and Divide subroutines are given in the microassemblerdocument. The inner loop time is 1 cycle/bit for multiply and 2 cycles/bit for divide.ShifterSee Figure 4.Dorado contains a 32-bit barrel shifter and associated logic optimized for field extraction, fieldinsertion and the BitBlt instruction.The shifter is controlled by a 16-bit register ShC. To perform a shift operation, ShC is loaded inone of three ways discussed below with 14 bits of control information, and one of eight shift-and-mask operations is then executed in a subsequent instruction. Alternatively, (a limited selectionof) shift controls may be specified in FF and BSEL concurrent with a shift; in this case, ShC isnot modified. ASEL=7 causes a shift and ALUF[0:2] select the kind of masking.The execution of a shift instruction (after ShC has been loaded in a previous instruction) proceedsas follows:ShC[2] selects between T and RM/STK for the left-most 16 bits input to the shifter;ShC[3] selects between T and RM/STK for the right-most 16 bits. Using the RisId orTisId FF decode in the same instruction allows Id to replace either T or RM/STK in theshift. This 32-bit quantity is then left-cycled by the number of positions (0-15) given byShC[4:7]. When ShC[2] and ShC[3] are both 1, then the shifter left-cycles T; when both0, RM/STK. In these cases it operates as a 16-bit cycler. When ShC[2] and ShC[3] areloaded with complementary values, then it left-cycles the 32-bit quantity R..T or T..R.The low order 16 bits of shifted data are placed complemented on A by the shift, andnormal A source is disabled (except when the source for A is encoded in FFsee theASEL section).ALUF[0:2] select one of eight mask operations (see below) and the first three ALUFMaddress bits are forced to 1, so that the ALU operation in either ALUFM 168 orALUFM 178 can be performed. This must be a logical ALU operation using the shifted fp#$q5pG?f bs ^p? \,5 [ W5 T3t9R9Q+9O8 L9K9I% F$pU DZW @s:xM x&Rx[!6x $q pxJxT xAx 7 t px M t MpB <]nDorado Hardware ManualProcessor SectionAugust 1, 198523data on A and data on B because there is insufficient time to propagate carries for anarithmetic operation. The intent is that ALUFM 168 contain the control for the "NOTA" ALU operation normally desired, while ALUFM 178 is used by BitBlt and otheropcodes that need computed ALU operations.ALU output passes to the masking logic. The mask operation determines which of twoindependent masks in ShC are applied to the data. LMask contains 0 to 15 ones startingat bit 0, RMask 0 to 15 ones starting at bit 15. The masked area(s) of ALU outputcorresponding to 1's in the mask are replaced either with zeroes or with correspondingbits from Md according to the shift-and-mask function selected. Replace-with-Mdgenerates HOLD if Md isn't ready yet, and the timing for this is the same as Md onto B(i.e., data is never ready sooner than the second instruction after the Fetch_).Masked data is routed onto Pd, then sent to the destination specified by LC.Note: The Pd input multiplexor is used to carry out masking, so it is illegal to combine ashifter operation with an ALU shift in the same instruction.Three functions load ShC: RF_A and WF_A treat A[8:15] as a Mesa field descriptor andtransform the bits appropriately before loading ShC; they also load ShC[2:3] from A[2:3]. ShC_Ballows an arbitrary value to be placed in ShC (used by BitBlt).Microcode for the Mesa RF (Read Field) and WF (Write Field) opcode is shown as an exampleof the use of the shifter. In these examples, a and b are the two operand bytes for the opcode, asdiscussed in "Instruction Fetch Unit." RF and WF both take a pointer from the top of the stackand add a to it as a displacement. RF fetches the word, and pushes the field specified by b ontothe stack; WF fetches the word, and inserts a field from the rightmost bits of the word in thesecond position of the stack into it, then restores the word to memory.RF:IFetch_Stack, TisId;*Calculate the pointer. a replaces BR[MemBase] (MDS);*this value is then added to Stack to compute the*address for the pointer.Stack_Md, RF_Id;*IFU supplies b, the field descriptorIFUJump[0], Stack_ShiftLMask;*Right-justify & mask the field, IFU to next instructionWF:T_(IFetch_Stack&-1)+T, TisId;*Start fetch of word containing fieldWF_Id, RTemp _T;*IFU supplies b, the field descriptorT_ShMdBothMasks[Stack&-1];IFUJump[0], Store_RTemp, DBuf_T;The shift controls come directly from FF if ASEL=7 (a shift) and if BSEL = 4, 5, 6, or 7,selecting a constant. This specifies complete shift control in the instruction which does the shift,so ShC doesn't have to be loaded in a previous instruction, and ShC isn't clobbered, so io tasksdon't have to save and restore it. When BSEL controls a shift in this way, the B source is forcedto be Q.The mask operations are as follows: fp#$q5pG?fxb?x`S$ _t`Sp!x^1]t^p x\*xYL3xWWxU,&xSVxR"@xPWBxNPxKLxGqpQxE< BlQ @'9 >? ;e: 9/wpwp% 7F 6wp>wp 4:O 2pG .t;$ wt$-31$+:*$ wt:(`$ * %X;$:#$ wt:" : b p5$ &P [ R b  p#   0^ .. +EL 'F & D $>*#t$>p! "s!t"sp=B !AFHTNIACIALinkJCNFFIFUAdQ[14]MIRTPCITPCOBNPCCIACIAIncLinkBLinkBMuxIMFFReadyBNTWakeupNextCTaskCTDTLinkAd>>>>rrCPStrbStartCycleStartCycleStartCycleSwitchT0T0T0T2T0SwitchT0T1T0TPCBypassPh3%4PErT0T2T3T2RSTK[2:3]rCBrRIMIMOutTPCAdT0T1T2T3T4T4T3T2T1T0T0T1T2T3T4T4T3T2T1T0T0T1T2T3T4T4T3T2T1T0T0T1T2T3T4CPRegUseCPRegRAPEncTLink*TPC*+1rrProcessorControlTPIMOutWriteT3WriteT3D1Control.silFigure 5Control Section9/5/796ttWAI^.=f^.:^.7I^.3^./:^.0[f$94;[f$97[f$9:[f$9>;[f$9A[f$98ed7aU$6tS7T-$6PJ-7Qr$<Gf$ 8eC9@$97VC$>;@$<9$;P8e:{0<7%$C7%$*3.9$9,$96",7 V$D $BB.M_ $.&$'s*:&$90+WsG."s $+,$9*,$9),$9(,$9.d<;U$A^.[f$9a'$$WrP& $yLrN$HWTtG :O 9$FIB$AV;-4/:$92$,s#H$7#H$*:*$9<>$99E-$9:_$97_$9>;_$UA_$9_$9X$rS$V6,$97Y.$9 V[Gs9$9$$M9$[C$]]|$@$@$J $K$G$9r[C$] 9]|]$ 9K$ 9K9$ 98e$r0z| 5  5 2;?D:FFJOQvQvUZVX!X! X!\0WX!3X!7X!:WX!=X!AX!A\=\:W\7\8b7U7P7M7H7D ;tD ==v9;=v;t;=;t6<;t.u;t"9;)u4)u2"7"7 71sX1st+t++ .")")'<()u))u*:)u+W)u.;.. WLvJ=&WKZ4KZ0)A$4%>G>$"s$-:;9s Q rI9AL W3S3J-4@-88e805Wd0WF %", T-7er$;td$7d$7d$@rW_$@9Mr$L$9L$9L$@Br$VA$A$A$@:<%r$;-$:; $:; $@)#%$.",$)"$$)"$@*:zr$.$*:]$*:]$@/zr$4;$/]$/]$@5W#%r$9",$5W"$5W"$@91r$>;0$90z$90z$@99^r$>;8e$98B$98B$@5WK&r$9J-$5WJ $5WJ $@5WN{$@5WT r$9S$5WR$5WR$@W$rX|r$:T$T$rJ-$7|'</: $9# y"s$6tGG8@tG9N$7KJ$U7Gf$?$s8e$2% G9.9$4;,sG,se$7e$2$5WOr$9;b$9;e$+W VG#.V$)%G 8rG,s$.9$0W$9.]$.$]-$0z$-$-$/:$97&$5W)r$9($5W($5W($5WN{$rW_$ :LGr@$uW5)$k5*$5*:$G:W)A$@5*^$5O$k5Or$:N$@9Nk$5O$k5P&$:WO $@:O k$7P&$7*^$]VIG;-4:W",$,$+9(k$:($@:)Ak$'s,sG0$?W$*-[C$]-|X!,t^.,s[:GAa9$>;c $W_$&u%(t((N+O $r   V  :   :   V :   # ( 0 ,s ( #  (,s05W9B>;95W09d>;dBdGdKd y$ G y$ y$+ y$+ ]$ ]$ ]$ @$ @$ ]$ @$ $$$ $$$ @$)e $$)e $- $- $$2I $2I$6$6 $;-$;-$?$?$D$H$F $[# $!V*%u+;tt<VQf6 (6tNV0$<&$ ;-30)e$"s1 $<5$;t|2|,sz$+X % $t, :H9;h $sW$W$X|r$5W,$93&$ *^",<1$8uM;8L8's8&W@t $rr"AurH_g110001000BRANCH CONDITIONALU = 0ALU < 0FUNCTIONSubroutine ReturnunusedRead TPCWriteTPCunusedunusedGlobal CallLong Jump/CallR is resultTNIA:01234567JCNADDRESS BITSADDRESS BITSADDRESS BITS01111Return001111BRANCHCONDITIONADDRESS BITSRETURNFUNCTIONNUMBERNEXTRead Instruction MemoryWrite Instruction MemoryIFU JumpLocal Jump/CallNext Address FormationJCN[5:7]0123456JCN[2:4]0123456Conditional BranchReturnRSTK[2:3]0123RSTK.0RSTK.1RSTK.2RSTK.3ALUF.0ALUF.1ALUF.2ALUF.3BSEL.0Par.16BSEL.1BSEL.2LC.0LC.1LC.2ASEL.0ASEL.1ASEL.2BLOCKFF.0FF.1FF.2FF.3FF.4FF.5FF.6FF.7Par.17JCN.0JCN.1JCN.2JCN.3JCN.4JCN.5JCN.6JCN.77when B_Link executed infollowing microinstruction.ConditionalJump/Callotherwise, it is a jump.before any modification of TNIA by branchA long, local, or conditional branch is a call iff,write the right half.Good (odd) parity is writtenif RSTK.1 is 0, else bad (even)parity is written.The most significant bit ofdata is RSTK.2 and the leastsignificant 16 bits are B[0:15].JCN.7JCN.6JCN.5JCN.4JCN.3JCN.2JCN.1JCN.0FF.0FF.1FF.2FF.3FF.4FF.5FF.6FF.7BLOCKRSTK.0RSTK.1RSTK.2RSTK.3ALUF.0ALUF.1ALUF.2ALUF.3BSEL.0BSEL.1BSEL.2LC.0LC.1LC.2ASEL.0ASEL.1ASEL.2RSTK.2B.0B.1B.2B.3B.4B.5B.6B.7B.8B.9B.10B.11B.12B.13B.14B.15Data appears on B[7:15]Cnt=0&-1 (decrement Cnt after testing)R < 0R odd-or-FF6061626364656667--Address is in Link.Address is in Link.Figure 6Carry'IOAtten' (non-emulator) -or- Reschedule (emulator)RSTK.3 is 1 to writethe left half of IM, 0 to0001x111undefined234567891011121314151514131211109876543223456789101112131415151413121110987654322345678910111213141515141312111098765432CIA[2:3]CIA[2:3]CIA[2:3]Link[2:15]CIA[2:9]JCN[2:7]JCN[2:7]000000FF[0:7]JCN[4:7]CIA[2:9]RJCN[3:4]0JCN[1:2]JCN[3:4]InstrAddr[4:13]15141312111098765432CIA[10:15] + 1CIA[2:9]Loaded into Link by Call, Return, or IFUJumpconditions or dispatches, TNIA[12:15] is 0;# 000xD1Branching.sil# 1116/26/80Overflow_ZUP_ZUVU Uu=ft;:u.rt-Ir,,r(r'r+r)pZ UFuPJ *pabXbXVbX bX bXbX9bXrbXaG d_ Z uUJ pKKK9KrKKFFVFrF9FFuPJO- PJ VKVJ FI Gfrt&rpF_rVu=f t; : 9 8e 7I 6, 5Vu. t-I ,, + ) ( ' &u?1,', :t$ :", :e :'s#$+#$0W#$4#$9;#$=#$B#$F#$#&z($K$e$9#$A(%$#$A$]#$($,s$0$5W$9$>;$B$G$#!z$]#!z(%$K!$9##($F!$B!$=!$9;!$4!$0W!$+!$'s!$'sH$+H$0WH$4H$9;H$=H$BH$FH$# ($K$9#(%$#$]#$]#(%$K$9#%($F$B$=$9;$4$0W$#",(",,s",1s",5",:W",>;",B",G",#e(e-e1se5e:We>eC;eH;e#(-1s5:W>C;G ! pP N *t?*A)*B3!H!+!5H5+5  $  $ $ $s $ $!V $% $9 $]Jt F A = 8 4; / * . $3 $7 $< $@t $D $IX $M $9*: $9$K$9 K$9K$9$K$*:$M$9IX$D$@t$<$7$3$.$9$]%$!V$$s$$$ $$  9     "s &  9 s!&W*/:4;8=AEtI 9#'s+0W4;8=AFJt#'s$+$8e&7I6, u=f9=f9t;9:9998e97I96,9593 r3$d$rt952H+pBBB B VBB9BrBB %:`$DX^$9%:^A$%:^$]'s^$+^$.^$0W^$2^$4^$DX^$B^$?^$=^$;t^$9;^$&Wt](]*]-]/:]1s]3]5]7]9]<]>;]@t]B]BX@tX>;X<X9X7X5X3X1sX/:X-X*X(X&WX9;Y$;tY$=Y$?Y$BY$DXY$4Y$2Y$0WY$.Y$+Y$'sY$%:Y$]%:YA$DXY$9%:[$%:V$DXT$9%:TA$%:T$]'sT$+T$.T$0WT$2T$4T$DXT$BT$?T$=T$9;T$7T$&WS(S*S-S/:S1sS3S5S7S9S<S>;S@tSBSBN@tN>;N<N9N7N5N3N1sN/:N-N*N(N&WN9;PJ$?PJ$DXPJ$4PJ$2PJ$0WPJ$.PJ$+PJ$'sPJ$%:P&$]%:P&A$DXPJ$9%:R_$%:M_$DXKJ$9%:K&A$%:K&$]'sKJ$)KJ$+KJ$.KJ$0WKJ$2KJ$4KJ$DXKJ$BKJ$?KJ$=KJ$;tKJ$9;KJ$7KJ$&WI(I*I-I/:I1sI3I5I7I9I<I>;I@tIBIBE-@tE->;E-<E-9E-7E-5E-3E-1sE-/:E--E-*E-(E-&WE-7F$9;F$;tF$=F$BF$DXF$4F$2F$0WF$.F$+F$'sF$%:F$]%:FA$DXF$9%:H$)Y$9)T$9)F$9%ZJ%UJ%Gf2IK )^$7^$9,s_J;t_J7Y$9.ZJ7ZJ:ZJZJ@ZJBZJ;tT$90UJ=fUJ)PJ$7PJ$9-P;tP&9$BPJ$9;tPJ$9=PJ$9BP=P+$@+$B+$E-+$5+$3e+$1,+$.+$,+$*+$(H+$&+$]&+A$E-+$9&-$7+$97+$:,s,,s&p.,*t@+9uO-9N:9t3X99Kc. %t2t1dt1ct1bt1at1t0t2t1dt1ct1bt1at1t0t4t3t2t1t0t4t3t2t1t0Phase 0Phase 0Phase 4Phase 3Phase 2Phase 1Phase 0Phase 4Phase 3Phase 2Phase 1Phase 0CTD_CTASKWRITE TLINKMIR LoadedqqqqMIR LoadedCTD_CTASKCTD_CTASKMIR LoadedMIR LoadedMIR LoadedqqqReturn:qMIR LoadedMIR LoadedqqMIR LoadedMIR LoadedqqqqqqqNormal:StartCyclePhase 0StartCycleStartCyclePhase 0StartCycleCIAInc_CIA+1CTD_CTASKCIAInc_CIA+1StartCycleLINK_CIAIncStartCycleCIAInc_CIA+1LINK_CIAIncLINK_CIAIncCTD_CTASKLink clobbered.LINK_CIAIncCIAInc_CIA+1StartCycleqqMIR LoadedqqqMIR LoadedWRITE TLINKCTD_CTASKPhase 0Phase 1Phase 2Phase 3Phase 4t0t1t1at1bt1ct1dt2CTD_BMux[12:15]qt2t1dt1ct1bt1at1t0Phase 4Phase 3Phase 2Phase 1Phase 0CTD_CTASKWRITE TLINKMIR LoadedqqqMIR LoadedqqStartCycleCIAInc_CIA+1LINK_CIAIncTPCI_TNIA (Link)Write TPCClear TLinkXqqRSTK[1]=0->odd1->evenparityTPIMO_IMTPIM Mux _ IMTPIM Mux _ TPCRSTK[3]=0->right half1->left halfD1InstTiming.silFigure 7Instruction Timing10/8/79Read RMALU operaionWrite RM<><><>Calculate next address<>Fetch next instructiont-1t-2qMIR LoadedFetch Instructionq<>Write IM:Read IM:Read TPC:Write TPC:B[12:15] = address (task number). Data from Link. Link clobberedB[12:15] = address (task number). Data to BLink. Data available on B next cycle ONLYLink = address, RSTK[2:3] = 9-bit byte, data to BLink. Data available on B next cycle ONLY. Link clobbered.Link = address, RSTK[2],,B[0:15] = data,Fetch next instructionLink _ CIAIncWrite TLinkFetch next instructionWrite strobeFetch next instructionFetch next instructionFetch next instructionLink_CIAIncTPIMO_TPCWrite TLinkLink_CIAIncCTD_CTASKCTD_CTASKModify address by b.c.Link_CIAIncCTD_B[12:15]?t575.5%:5V5r5 5?E-7E-.E-%:E-VE-rE- E-.UJ%:UJVUJrUJ UJ?c.7c..c.%:c.Vc.`R@$R $ S/C&CCC C/3&333 3.1$.,,$U..A$B,, @t1,$9@t.$@t.e$IX.e$A. B+ @t+z$?|)u@t+$9?/3;t$@t3$?>@t;-$9?9@t; $Bt: IX=$@t=$@t>^$@t@$9B; @tC$C_?W$KJ `$%`$.`$7`$@t`$X 0X BX 7]$7^d$#^$^$%^.$@tY $@tY $]?|W.WY $VWY.$9.Y.$9.Y $.S$%S$S$S$ S$R5W$ C$C$C$%C$.C$7C$73$.3$%3$3$3$ 3$rpUPJ$9PJ$9M$M$%M$ N$9 |K M$ VtM V; <%$ |:  r/ :@-$ :@ $+@ $.;=.=f$9.=$9WIX$9IIX$9:4IX$(lIX$ K$93IX$9WIX$9J IX$9:{IX$9(IX$9zIX$./%, $%,$ KJ$rpb&t` 0W`8` S S&S VO- 0Y @t]$V? 8C -; 83 V0 +/ ?W0 BY ?Gf?WH V 8", .|<r<$ Vtd $ | $9 ",$",$",$%",$.",$7",$@t",$";t$?<@t$9?@t$BtH A, IX$@t$@t$@te$9Bd .z$.$ ",",",&",/", #r#V#%:#.#7#?#!V.]$7$7|<7$7 d$. @$?Wt+6t+-+$+++ +/:&Ws 9. $B ? $? +$rH +$A B ?@$?W|;?d$9?W V];t$?$7$.$%:$V$r$ $ G$9  $$ t rH$| - 8t + >;+ *:+.$r1s d 0 $| %:H$%$%:<.$r.H$?H$2tGf8G8F:WE+0%+ /:#Gf)eFG98eFG9)G )F <u#rr =ut^.+W^. 9^.|Z$Z%Z%^G$2^r$6tZ>^$7Z?WZt\\$,s\9$|X-Xt[f`$ `$ r`9;$rc. c. Y.$9 |W Y $ VtX [$.[$9 [$+^.r|Y ^$s^r$\$d ZZrpG r7r%  tB %V 7m 9Gf( 9KO- N /="s@- /.e// ++ 6t A> ?W? Y VY [*:  !+ h9IbXDorado Hardware ManualControl SectionAugust 1, 198525Control SectionThe control section interfaces the mainframe to the baseboard microcomputer or the debugging Altofor maintenance. In addition, the control section stores instructions in 4k x 34-bit (+2 parity) IM("Instruction Memory") and contains logic for sequencing through instructions and switching amongtasks.The current instruction is clocked into the MIR (Micro Instruction Register) register at t0 andexported to the processor, memory, and IFU sections for decoding. The control section itselfdecodes the JCN field, the BLOCK bit, and its own FF decodes (Wakeup, B_Link, B_RWCPReg,Link_B, TaskingOn, TaskingOff, BDispatch_B, BigBDispatch_B, Multiply, MidasStrobe_B,UseDMD, and branch conditions).The control section also exports the task number via the Next bus, which contains the task numberthat will execute the next instruction at.Figure 5 shows the overall organization of the control section. Figure 6 shows how branch controlis encoded in JCN. Figure 7 shows the timing for regular instructions and for the multi-cycle TPCand IM read/write instructions.TasksDorado provides sixteen independent priority-scheduled tasks at the microcode level. Task 17 ishighest priority, task 0 lowest. Task 17 (the "fault task") is woken by StkError and by memory mapand data error faults. Tasks 1-16 provide processing functions for I/O controllers implementedpartially in hardware, partially in firmware; the present assignment of these tasks to devicecontrollers is given in the "Slow I/O" chapter. Task 0 (the "emulator") implements instruction sets(Mesa, Alto, SmallTalk ,Cedar, Lisp, etc.). In the absence of I/O activity, task 0 (always awake)controls the processor.I/O devices usually have 2 tasks associated with them, one for a input wake-up and one for an out-put wake-up.Each task has its own program counter and subroutine return link, stored in the (task-specific) TPCand TLINK registers when the task is inactive. TPC may also be treated as a memory, so programcounters for tasks other than the current task can be read and written by a program. fp##q5pG?f ar ^ep\ \a Z ZyZ ZyUZ4 Y U+U=UU0BU=U 7U=UUsUp S"; Q8 P4PEQ Ni J[ I-* EO C"@ B% = t 9pZ 7!B 6B 4:D 2p7- 0+7 . +ib ) &,N $a_ "PTL " =FDorado Hardware ManualControl SectionAugust 1, 198526Current Task ConfigurationTask #Task #Signal Wiring information on Right side panelOctalDecimalName00No name for task "0"None11TWReq.1Pin# 44 ContA22TWReq.2Pin# 45 ContA to IFU pin# 13 (JunkTW)33TWReq.3Pin# 48 ContA to DispY pin#121 (WakeDHT)44TWReq.4Pin# 56 ContA to DispM pin#121 (WakeAHT)55TWReq.5Pin# 57 ContA66TWReq.6Pin# 60 ContA to DskEth pin#121 (WakeEthTx)77TWReq.7Pin# 61 ContA to DskEth pin#120 (WakeEthRx)108TWReq.8Pin# 64 ContA to 10mb Ethernet pin#121 (WakeEthTx)119TWReq.9Pin# 128 ContA to DispM pin#120 (WakeAWT)1210TWReq.10Pin# 129 ContA to ProcH pin#109 (TestTW) Also the10mb Ethernet board will be wired to this task from pin#1201311TWReq.11Pin# 132 ContA to DispY pin#120 (WakeDWT)1412TWReq.12Pin# 133 ContA to DskEth pin#117 (DiskTW)1513TWReq.13Pin# 136 ContA1614TWReq.14Pin# 137 ContA1715TWReq.15 Pin# 140 ContA to MemX pin#132 (TWReq15) Task SwitchingWhen device hardware requires service from a task, it activates its wakeup request line at t0.Wakeup requests are priority-encoded, and the highest priority request (BNT or "Best Next Task")is clocked at t2 and competes with the current task (CTASK) for control of the machine. If BNT ishigher priority than CTASK, or if the current (non-emulator) instruction has BLOCK = 1, a taskswitch will take place; in this case, CTASK will be loaded from BNT at t4. This implies that theshortest delay from a wakeup request to the first instruction of the associated task is two cycles.The 16 Wakeup[task] FF decodes allow any task to be woken, just as though a hardware device hadactivated its wakeup line. A minimum of two cycles elapses after the instruction containing Wakeupbefore the task executes its first instruction. The task responding to a Wakeup must not blocksooner than the second instruction, or it will get reawakened.When a task has been woken by a FF decoded Notify[task] or has executed one or moreinstructions and then deferred to a higher priority task, the fact that it is runnable is remembered ina Ready flipflop. The Ready flipflop is cleared only when its task is restarted again after a higherlevel task blocks.Task # 0 has no Ready flipflop and cannot block; the BLOCK bit in the instruction is interpreted as StackSelectfor the emulator.Task switching may occur after every instruction unless explicitly disabled by the TaskingOfffunction. The TaskingOn function reverses the effect of TaskingOff. TaskingOff is "atomic"; aninstruction containing TaskingOff will be held if a task switch is pending; the next instruction willbe executed in sequence without any intervening task switches. TaskingOn is not immediatelyeffective; at least two more instructions will be executed by the same task before task switching canoccur. fp##q5pG?f bt ^p& \ Z1 Y)1 W^1% U1( S1( Q1 P41+ Ni1+ L12 J1* I 11G?; Et1* C1) A1 @1 >J1* 90t 5p%751s5p 3A> 33A23"3D33 2) 1s2)pR 0_%9 .8.s.p ,N )W_ '\ %9& #> K G T &yds)Fy p$9 D  ?& UE K  y>]Dorado Hardware ManualControl SectionAugust 1, 198527Next Address GenerationRead this with Figure 6 in front of you.For the most part, instruction memory (IMX) addressing paths are 16 bits wide, although only 12bits are presently used; the extra width allows for future expansion to 13 or 14 bits, whensufficiently fast 4kx1 ECL RAMS are economically available; there are no plans to utilize theremaining 2 bits, but since nearly all hardware components in the control data paths are packaged4/chip, the extra two bits are almost free. Also, the 16-bit wide Link register can be used to holdfull word data items.The various registers and data paths that contain IMX addresses are numbered 0:15, where bits 4:15are significant for the 4k-word microstore, while the quadrant bits 2:3 are not used until we go to a16k microstore. This numbering conveniently word-aligns the bits while also allowing for futureexpansion. The discussion below assumes a 4k-word microstore.Dorado does not have an incrementing instruction-address counter. Instead, the address of the nextinstruction is determined by modifying the Current Instruction Address (CIA) in various ways. TheTentative Next Instruction Address (TNIA) is determined from JCN[0:7] in the instructionaccording to rules in Figure 6. TNIA addresses IM for the fetch of the next instruction unless atask switch occurs. If a task switch occurs, the program counter for the highest priority competingtask (BNPC or "Best Next PC") addresses IM. fp##q5pG?f bt^qX( [:pH YoP WY UT TG RE N W MZ K>L Is> F8+ D7+&/CD7+YCD7 2QCD7 BBl MB"Bl>BBl BBl ! @@! >F = , 9 =.Dorado Hardware ManualControl SectionAugust 1, 198528IMX is viewed as containing 64 pages of 64 instructions. Values in JCN are provided for thefollowing kinds of branches:Local branches to any of the 64 locations in the current page;Global branches to location 0 on any of the 64 pages of the current quadrant;Long branches to any location in the quadrant using the 8-bit FF field to extend JCN (normalinterpretation of FF is disabled);Conditional branches to any of 14 even locations in the current page, if the selected condition isfalse, or to the adjacent odd location, if the condition is true (7 branch conditions areavailable);IFU jumps are made of 8 bits from the ifu, 2 bits from JCN, and 2 bits from CIA.Return to the address in Link;Branch conditions may also be specified in FF. Several dispatches may also be specified in FF.These 'OR' bits into the branch address computed by the following instruction.If IM is expanded to 16k words, branching from one quadrant to another will only be possible byloading the Link register with a 14-bit address and then returning; jumps, calls, and IFUJumps willbe confined to the current 4k-word IM quadrant.Conditional BranchesIM is organized in two banks, with odd addresses in one bank, even in the other. For this reasonconditional branches select between an even-odd pair of instructions (i.e., between the two banks)according to branch conditions.Alternatively, a conditional branch may be encoded in FF in conjunction with any addressing modeexcept a long branch in JCN. When this is done, the result of the branch test is ORed withTNIA[15].This implies that for both FF-encoded and JCN-encoded branch conditions, the false target addressis even and the true target is odd.It is possible to conditionally branch using only JCN, while using FF for an unrelated function, orto encode a branch condition in FF while using any addressing mode in JCN. If branch conditionsare encoded in both FF and JCN, the branch test results are OR'ed, providing further flexibility. fp##q5pG?f b@ `Sy]q p0y[qp>yXxq pHyV"yTqpA yRE*/yPz yMqp>yK>qp GE F8qp BS @E >/ 9t 6opQ 4N 2 /h2. -B + (` U &# #$^ !YD B H=HDorado Hardware ManualControl SectionAugust 1, 198529The branch condition encodings are:Table 13: Branch ConditionsJCN[5:7]FFBranch Condition060ALU=0161ALU<0262ALUcarry'363Cnt=0&-1 (decrements count after testing)464R<0 (RM or STK, whichever is selected, not overruled by RIsId)565R Odd (RM or STK, whichever is selected, not overruled by RIsId)666IOAtten' (non-emulator) or ReSchedule (emulator)67OverflowALU=0 and ALU<0 are the results of the last ALU operation executed by the current task.ALUcarry' (the saved carry-out of the ALU) and Overflow are the result of the last arithmetic ALUoperation executed by the current task (ALU_A may be stored in ALUFM as either an arithmeticor logical operation, so programmers should be wary of smashing these branch conditions whenALU_A is used.). These are saved in a RAM and may be frozen by the FreezeBC function forone cycle. In other words, the branch conditions are ordinarily loaded into the RAM at t3, but ifFreezeBC is present, then the RAM is not loaded and values from the previous instruction for thesame task will apply.The IOAtten' branch condition tests the task-specific IOAttention signal optionally generated by theio device associated with the current (non-emulator) task.Subroutines and the Link RegisterDorado provides single-level subroutines by means of the (task-specific) Link register. A Calloccurs on any instruction whose destination address is 0 mod 16 before any modification of TNIAdue to branch conditions or dispatches. On a Call, Return, or IFUJump, Link is loaded withCIA+1.Link may be loaded and read by programs, so deeper subroutine nesting is possible, if Link issaved/restored across calls. fp##q5pG?f b#!]tX Zfu~!Y:W;s~!Y:U~!Y:T3~!Y:R~!Yvs:Q+~!Y'vs:O~!Y(vs:N#~!Y0:L~!Y IPp9 G?q p E1+ C3) B%.+ @[5$?s@[p >C < 9T X 7: 2pt! .p8' -3+4 +iV ) &,2+ $a $>CDorado Hardware ManualControl SectionAugust 1, 198530DispatchesSeveral FF decodes are dispatches which OR various bits with TNIA[8:15] during the followinginstruction. The dispatch bits must be stable by t2.Dispatches are:BigBDispatch_BB[8:15] (256-way dispatch)BDispatch_BB[13:15] (8-way dispatch)MultiplyOR's Q[14] into TNIA[14] (The value of Q[14] is captured in a flipflop at t2 of theinstruction containing the Multiply function and is OR'ed into TNIA[14] during the nextinstruction for the same task.)Example:BDispatch_T;*T=7Branch[300];*branches to 300 OR 7 (IMX location 307)The two B dispatches load Link register from B, then OR appropriate bits of Link into TNIAduring the next instruction for the task. Since Link is task-specific, this works correctly across taskswitching. The Q-bit is only loaded during a multiply, and tasks other than task 0 are not allowedto use the multiply function.IFU AddressingThe IFU supplies ten bits of opcode starting address to the processor. During the last instruction ofevery opcode, exit to the next opcode is accomplished by IFUJump[n] (n = 0 to 3) which selectsamong four entry locations for the next opcode. The starting address supplied by the IFU is usedfor TNIA[4:13] and TNIA[14:15] are set to [n]. If the IFU is unprepared, it supplies a trap addressinstead of a starting address, and control goes to a reserved location in microstore. See page 30 table14 for the locations reserved. IFUJump's always load Link with CIA+1. This is necessary to implement the following conditionalexit feature for opcodes.If an FF-encoded branch condition is true in the same instruction as an IFUJump, IFU advance tothe next opcode is disabled. This kludge allows an opcode with common and uncommon exitconditions to finish, for example, with IFUJump[2,condition]. If the condition is false (commoncase), then the IFU advances normally to the next opcode, starting at location 2 of the entry vector.Otherwise (uncommon case), control continues at location 3 of the entry vector, but the IFU doesnot advance, so emulation of the current opcode can continue. fp##q5pG?f bt ^pq p2q \p3\Ts\p Y:Vs :U :S_;RS_Q#4PW Mp:J :H6 ( DZ BR A.Q ?d :Kt 6pM 5L 3CQ 1y6. /R - *rE ( %5D #j)/ !'9  Z  G @=8 =LDorado Hardware ManualControl SectionAugust 1, 198531IFU trap addresses and other reserved locations in the microstore are as follows:Table 14: Reserved Locations in the MicrostoreReasonLocationsCommentReschedule request*14-17Indicates that some previous instruction executed the ReSchedulefunction.IFUM parity error*74-77Indicates a hardware failure in the IFUM storage.IFU not ready*34-37The instructions in this vector should contain IFUJump[n], waiting forthe IFU to become ready.IFU data parity error *4-7Parity wrong on data from cache.IFU map fault *0-3The IFU buffers the fact of a map fault and completes all opcodes inthe pipe ahead of the one experiencing the fault. Upon dispatch tothe first instruction for the opcode affected by the fault, this trapoccurs.Midas Call command 7776Midas Crash detect 7777*Ifu traps OR the 1's complement of the instruction set into bits 8:9 of the trap address, so actual trap locations forReschedule, for example, are 14-17, 114-117, 214-217, and 314-317.IM and TPC AccessSee figures 6 and 7.IM is read and written by programs using a special decode of JCN in conjunction with the RSTKfield of the instruction; TPC is also read and written using a special JCN decode.After the read or write instruction, control passes to the next sequential instruction, i.e., to CIA+1(with wrap-around at 64-word page boundaries). CIA+1 also winds up in Link.Total time for an IM or TPC read or write operation is 6 clocks (i.e., thrice as long as a normalinstruction).A 34 (+2 parity)-bit IM word is read as four 9-bit quantities. The read address is taken from Link.Data must be read from Link[7:15] in the instruction immediately after the IM read; this data isinverted; Link[0:6] contain 1's, so that when the entire word is 1's complemented the desired datawill have leading 0's. The byte select is RSTK[2:3].IM writes also take the write address from Link, 16 bits of data from B and 2 bits from RSTK; thehalf-word affected is also specified in RSTK.Any task can read or write TPC for an arbitrary task other than itself (an attempt to set TPC of therunning task is unpredictable). The task number is B[12:15], and data is taken from or written intoLink. The assembly language notations for these are RdTPC_B and LdTPC_B. After RdTPC_B,the 16 bits of data in Link are 1's complemented. fp##q5pG?f bQn^tX/x[vR'xXxsR%5$%5WxUMR%5(xS R%5 6%5R"xPWR%5xN R%55%5M,&%5K,%5JjxHRxFR B3D @[B UDorado Hardware ManualControl SectionAugust 1, 198532HoldMany events in the memory system, StkError and the hold simulator in the processor, and severalIFU error conditions generate hold (The IFU error conditions cause a one-cycle hold if anIFUJump occurs on the first cycle of the error.). The control section itself forces hold when a taskswitch occurs concurrent with TaskingOff. This signal, clocked at t1, occurs when the currentinstruction cannot be completed. Its effect on the hardware is to suspend the current instruction,while completing parts of the previous instruction that have been pipelined into the current cycle.Approximately, it converts the current instruction into a Goto[.] while preserving branch conditions.Higher priority tasks are not prevented from running when the current task is experiencing Hold.RemarkThe fact that the address of the next instruction is needed at t0, while Hold is not generated until t1 means thatconcurrence of Hold and BLOCK with a switch to a lower priority task produces an anomalous situation called "NextLies". The hardware disables clocks to CIA, TPC, and MIR when this occurs, so that the current instruction is repeated.Program Control of the DMuxDorado contains a large number of multiplexors called mufflers which allow a selected signal from aset of up to 2048 signals to be observed on a one-wire bus called the DMux located at Pin # 186on the left side panel for all of the boards. This provides a passive method by which the Baseboardsection or the external Midas debugger can examine internal control signals and registers nototherwise observable.The particular DMux signal is selected by shifting in an 11-bit address one bit at-a-time. Eachboard with mufflers contains a 12-bit address register that responds to the shifted address bits; thehighest bit is ignored for the purposes of selecting the signal to be read. "Dorado DebuggingInterface" discusses a clever generator algorithm that allows all 2048 signals to be read into a tablein 2048+11 shift-read cycles.In addition, the DMux address can also be executed as a control function. In this case the full 12-bit address determines what function is executed. This "manifold" mechanism is used to controlpower supplies, set clock rate, enable/disable error halt conditions, and test IM without involvingother hardware.The DMux facility can also be controlled directly by Dorado programs by means of theMidasStrobe_B and UseDMD functions. Essentially, the DMux address mechanism is controlledexternally by the Baseboard or by Midas operating through the Baseboard when Dorado isn'trunning, and by Dorado when Dorado is running.The MidasStrobe_B function causes B[4] to be shifted out as an address bit. This takes threecycles, so the program must execute three more instructions before doing another MidasStrobe_Bfunction. The DMux signal selected by the last 11 address bits shifted out is read on B[0] when thePd_ALUFMEM function is executed.The UseDMD function causes the current DMux address to be executed as a manifold operation. fp##q5pG?f bt ^pS \1( [e YLDXsYLp WB! UJ ST PzqpC LXv Gs>FG%FG ET D7N* @t =/p!B ;eF 9!C 7O 6 2 R 0 [ .K -3P +i 'W &,_ $aP " %(, Z: 1( . S] #; :*  9" :>Z+Dorado Hardware ManualControl SectionAugust 1, 198533The following subroutine reads the DMux signal selected by the address in T:Subroutine;ReadDMux:Cnt_13S;RdDMuxLp:MidasStrobe_T;*Shift out address in T[4]Noop;Noop;T_(T) lsh 1, Goto[RdDMuxLp,Cnt#0&-1];T_ALUFMEM;*T[0] returns selected DMux addressReturn; fp##q5pG?f bL:^s :]K[:ZCX "sW;UT3%R "s#Q+2 Q5KIMemBase *Md *Time from0Time fromAddressingCache dataMain storage16<1582Ad><<SINSOUTFIN77 rows x 4 col6..2121..27Real page Flags64K x 19282816816187tb !Vua< KtaHueg 5pe e 9e Gc.G*dVG*bGd 9GbG.et_J-Z&$7I\9$7|Y>0WD$VCO$DtOt5N$/F&$4S$/U&$3>^$4;/$+=$'s=r$(% $ Ve$ V ]$ d* +3$<=-I_$!V$y$"sH_$;->^$+W>^$_$"s_$)1$#GB$+W/-|+ rt $$r$ H$]$ |; 8eO's5 's: $u!Vt'<9&Wu(.u/@t9t.u.u"sAY :AY"sH#Km$#D{$!H$!tb!|]V1$ $$9(tVV $D{r$ y$($"V$$%y$( -%$$%$&"$7 !$!!>$ r rs V,- b!J-)e ! *$9*$9! )e V& : :;V&%:&W/'s8k$;8$=?{$:A/@-*?{$5W?{$/:ABA$UAI?{$]AI?{y$D?$9AIAU$;D$9?{$9?{$9Cr$A@-:@-^ $'s5$5{ $5{$  D$GB$!J $$J-$d!Km$ rH$r $ ]$+$ 9$$ e$9A$$U@$$y9!z$ !$9, $y9, @$ V,,$U9/^$ /$ 0z$1$/:1r$]5t>;.&$&z$1s0$-0z$.>^$0>^$*?{ $-|,"&W)A$'s<%]$'s:{ $$'s6's8ut_J#_#G"sH-/^d$Gf/^$)>Y $>V$9=|S!V4^$"st3+W"$*|u*)A$+t($r$*^V$ ]$! G$9*: G$9 G$9|tst!Vt%t)ttV9;]$8_$:W_J7[$9!V&V4=f2I>2I=f/:>/:=f,s>,s=f4>K\JCJt4;I&F@?W  +  +3Iu,sC,sCtHIXHu` dGsbGbG(bG! $0t[ HudJ !J $B #r+&V3B $3B$]V4^$Bu9'st(! $8 # $V|t3 8;tQ3L3Q$* **&.1sE1sT$-k$V$ $ V,,,$3]KdFigure 945678910111213141516171819202122232425262728293031VAxxxStored in address section<>Row><4k-wordCacheMunchWord in256-wordPagexxxxxxxxC2C3C4C5C6C7C8R2R3R4R5R6R7R8Word in pageC1R1C0R0xxCache, Map, and Storage Addressing<><>Map Addressing101112131415RPRPRPRPRPRP24252627VAVAVAVA00010203040506070809RPRPRPRPRPRPRPRPRPRPReal page from Map>ColStorage Addressing3130292827262524232221201918171615141312111098765445678910111213141516171819202122232425262728293031VABRMar4567891011121314150123Mar + BR = VAStorage size3210151413121110987654MarBRVA3130292827262524232221201918171615141312111098765445678910111213141516171819202122232425262728293031Virtual AddressingBmux,,Mar + BR = VA456789101112131415Bmux,,MarBmux(long Fetch)(Normal Fetch)765423VNVsAd.0-sAd.7CacheA AddressingCache4k-wordVA31302928272625242322212019181716151413121110987654CacheD Addressing4567891011121323Dad.0-Dad.13 (Bits 2 and 3 not used)Dad.0 and Dad.1 are made up from Hit or Victim.Dad.0-Dad.13103287654104567823xxMapAd.0-MapAd.8#r@?$@->;$>?4$>$%:>;$'s>;$)>;$+>;$4>;$2>;$0W>;$.>;$=>;$;>;$9>;$7I>;$r>;$>;$>;$>;$#>;$ >;$>;$V>;$ G>;$ >;$>;$>;$>;$>;$>;$t>r>>> > V>H>>>>s>>>>!V>#>%>(>*:>,s>.e>0>2>5>7>:>>>Bp>8B?$+8e$48e$28e$0W8e$.8e$=8e$;8e$98e$8e$8e$8e$97I8e$9t8r88's8e$%:8e$r8e$8e$8e$8e$#8e$ 8e$8e$V8e$ G8e$ 8e$8e$8e$8e$9)8e$99V9 +$|6< 9$$6<-ts-,$,$ #%:'s)+,$+,$rV2  ss,$9,$ r,$ ,$+r" r 9$ r|f,sf,sVp(@-8e$9r2$(Ht*-I/2I4(H*-I/2I47I97I9HHHH #H%HHHH #H% $',H$5W|XrXC;pC;t ! & # ( + - 0 5 2 ? < : 7 7 : < ? 2 5 0 - + ( # & !   H H        H    + 9r$r$:r$r$r$$r$'sr$)r$.r$1sr$3r$8r$;tr$=r$$-$ r$sr$s+$"s+$,s+$rH  $6,$Bfp$=t%:;%:9%:7I%:4%:2I%:0%:-%:+%:)%:'s%:%:%:#%: %:%:%:%:%:d%:r%:%:%: %: %:V%:%:%:d%:$$G$$$$d$$+$$ $$ $$$$$$ :$$"s$$$$V$$$$$$6$$8$$;-$$=f$$-$$/$$2$$4;$$+W$$)$$&$$$$$$$$?4$?$$'?$r2$r$@t$rV$6tV$6tr$AuG 0t 0W 0WpR $$Au+%:|6<(6<%:9$(H9d$&t9%:9$p>tFIJtNX$ NX$#NX$7INX$9NX$;NX$=NX$.NX$0WNX$2NX$4NX$+NX$)NX$'sNX$%:NX$@-NX$ApFAIAIN%tN(HN*N,N.N1,N3N5WN7N9NNsNeN!N#NVNX$VN4#$VP#$pR t  Va#$V^#$V^$#_J!_Je_Js_J>_JtZV pdda]$^$^$^$r^$^$^$^$V^$ G^$ ^$^$^$^$^$^$t_Jr_J_J_J _J V_JH_J_J_J_Js_J_JAIp_J Ga%:9$%:9$2e 0R5t83e81,8.8*:8,s8&W;,s: pA@--$9B,B.%:-$'s-$7I-$9-$;-$=-$.-$0W-$2-$4-$+-$B1>t2;.&W.(..$%:,:$%:-$%:-$-I/./ #%-$- $ -%$$ $& $) $+W $- $ $ $V $ $"s $ : $ $ $ $ $+ $d $ $G $ $ $ !V! !!,,!)!'!%!#! !!r!!+!d!!!9!!!!V$.!+K&bX(BusyRefMapTestSyndrome is xor'ed with the checkbits on storage writes>VA[4:15]EmuProcSRN[0:3]<><><>B_Pipe5(B_PRef)Trouble'MemError'ECFault'Bit in word<>Word code'>dVA_VicFDMissUseMcrVDisHoldReportSE'NoWakedVA_Vic = put contents of cache address memory addressed by row of last reference and columnof Victim into Pipe0 and Pipe1>1514131211109876543210VA[16:31]<1514131211109876543210<>>><<1514131211109876543210Real page no. (RP)<>15141312111098765432101514131211109876543210WP15141312111098765432101514131211109876543210--------------WP------1514131211109876543210LoadTestSyndrome1514131211109876543210LoadMcr--1514131211109876543210Emu><<>MapTroubleMemErrorEcFaulttruefalsexPage faulttruetruexMap parity errorfalsefalsefalseNo errorfalsetruexUncorrectable error (DE)falsefalsetrueCorrectable error (SE)ReportSE' = when true, wakeup fault task on correctable errors (SE's), provided NoWake is falseWord CodeDisHold = prevent hold from occurringNoRef = prevent storage references011101110111Meaningword 0word 1word 2word 3otheruncorrectableChip SizeMapDirtybMapParityM0, M1, M2, or M3 indicates that a storage boardpair is plugged into slot 0, 1, 2, or 3.Chip Size0 = 4kx1 ic's1 = 16kx1 ic's2 = 64kx1 ic's3 = 256kx1 ic'sTaskD1MemReg.silFigure 10The Pipe and Other Memory RegistersReverseda1111Pipe5[0:7] are in the Pipe, Pipe5[8:15] are values read from cache address section during last ref.CFlags_A'ProcTag6/26/80t;tH+I";,,|" " &3 $t% HdH;t<H 'A:5W6,5W25W.5WA%=%:%6,%2%!<;t<X-I d? Et+H+8*8+0+-+Q+b-)[Y eC>;$Lc.$9 c >^$ c $]b$%:b$4b$b$b$!Vb$)b$-b$0b$8b$@tb$DXb$H;b$araVa:aa#a&a*a.a2a6,a:a=aAaEaIaV#R?WX-XE%I%XUVU VR<+<VTtA&< ';t<p_J]dbrLf VtSX29]=< -<1,<9;<8;tF<5"s&3 $-%2"s5W s5r$(5r$( ]$s ]r$"s -Jt$LJt$rpOWrIr5 U 9 rG rN&WtH 2Y.3 3X 3 d s|`wK`wd'r$2tc7Id'$-Y.5W +5U$H5$ |2V2s2+2 H ]$+ ]U$Vst +|rp<r:tGHIG"I!G1G -H+$7Hr$-|E=;tE=?WtH ^$L^u$9 `>;$*_ _n$0_n$ |[^$ Z&>;$LX$9sY $&WY d$s|UZ+UZ0Y $:WY $^$LNX$9 Pm>;$'sN OQH$2OQ$ |KKK^$LG$ J >;$<:$s:$I:E:A:=:::6,:2:.:*:&:#::::V:r::H;:$DX:$@t:$8:$0:$-:$):$!V:$:$:$4:$%::$:$ ;P$] ;P>^$L;t$9 =>;$6,<<4;$s4;$I3eE3eA3e=3e:3e6,3e23e.3e*3e&3e#3e3e:3eV3er3e3eH;4;$DX4;$@t4;$84;$04;$-4;$)4;$!V4;$4;$4;$44;$%:4;$4;$ 4$] 4>^$L4$9 6>;$<)$s)$I)E)A)=):)6,)2).)*)&)#)):)V)r))H;)$DX)$@t)$8)$d0)$-)$))$!V)$)$)$4)$%:)$)$ *^$] *^>^$L*$9 ,>;$+++++"+&+*:+5+IX+AI+=+<$$s$$I#E#A#=#:#6,#2#.#*#&####:#V#r##H;$$DX$$@t$$8$$0$$-$$)$$!V$$$$$$4$$%:$$$$ %$] %>^$L%:$9 'O>;$rp&r$e<$s$It,E,A,=,:,6,,2,.,*,&,#,,:,V,r,,H;$DX$@t$8$0$-$)$!V$$$4$%:$$ l$] l>^$L$9 >;$+p=t< $s $I E A = : 6, 2 . * & #  : V r  H; $DX $@t $8 $0 $- $) $!V $ $ $4 $%: $ $ @$] @>^$L d$9 y>;$- 0 ]9$: ]$;|0< ]$I ]9$<KuEt Et :Et+tDD!D%D +BB!B%B+AA A%A+@@!@%@+?? ?%?d_8uE- t%"9C9B9A9@t?uE-?tC?B?A?@t9;?W??W =5W E-5D4I5H4200(1s2 7I2 7I07I/7I.#XBu "sr H+#2tIhcrcVc:c8cp+W t<;tDXu JLfg 00010203040506070809101112131415WORD0DROW1514131211100908070605040302010000010203040506070809101112131415WORDDROW1514131211100908070605040302010012301234567xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx007206106307046247147346026227127326067266166367013212112313052253153352032233133332073272172373015214114315054255155354034235135334075474174375016217117316057256156357037136236337076277177376Check bits are EXOR ofdata bits marked xand number ofones inSyndrome isandfurthermoreTHEN0ALWAYSALWAYSNO ERRORNot 0ODDsyndrome bitsSINGLE ERROR (data bit)Bits 4,5,6 give bad word:4 5 6word0 1 11 0 11 1 01 1 101230 0 0 00 0 0 11 1 1 01 1 1 1...Bits 3,2,1,0 give bad bit:3 2 1 0bit00011415...Bad bit will be corrected iferror correction is enabledNot 0ODDin SyndromeSINGLE ERROR (check bit)Syndromebad check bit20010004002001000400200176543210Not 0ODDsyndrome bits4,5,6 have 0or 1 ones onTRIPLE ERROR!!(but no data bits will be changed)Not 0EVENALWAYSDOUBLE ERRORNo data bits will be changed.Syndrome is nonsense.Syndrome is nonsense.No data bits will be changed.4,5,6 have 2or 3 ones onexactly 1 oneInterpretation of SYNDROMEcomputed check bitsTestSyndromemessy EXORnetwork>Quad-wordin Cache>>r(usually zero)>>Quad-wordin storagecheck bitsnetworkEXORmessy >computed check bitsr>>>SYNDROME>qin CacheQuad-word>EnableqPipe 4rrin storage/4x1688other stuffErrorCorrectorcdeffedcSYNDROMEfor errorin bitIfSYNDROMEisD1ErrCorr.sil9/5/79Figure 11Error CorrectiontQPONMLfKJJ-IGFEDCBfAIpNXLKIXFrSXGr@Gr@tGr,,Gr,sGr?G568e:t-./:0W1s2345789;:W;t<=)e(H',&$#"! eH,p%$"s r*Gr+GrGrGrGrG +tr   9 Vrp1s +RV$r$NQV$PV$OV$N{V$M_V$LBV$K&V$J V$HV$GV$FV$EV$D{V$C_V$BBV$A&V$,V$-V$/V$03V$1PV$2lV$3V$4V$5V$6V$7V$9V$:4V$;PV$V$*^V$)AV$(%V$'V$%V$$V$#V$"V$!zV$ ]V$AV$%V$V$V$V$V$V$NV$kV$V$V$V$ V$ V$ V$ 2V$OV$kV$V$V$V$V$V$V$ SX SX VSXSXSXVSXSXSX tP N Lf J- G E C AI - /: 1s 3 5 8 :W < (H & # ! e ,   r    V    O N KJ J- F E Bf AI - . 1s 2 5 7 :W ;t ', & " ! H ,   r    V r   r$P VLf VM VKJ VJ- VAI VBf VD VC V/: V0W V. V- V5 V7 V9; V8 V# V$ V" V! V V V V V V V Vr V V Vr V VGIFEAIBfDC/:0W.-1s243e H,r  9 3421s-.0W/:89;75:W;t=<(H)e',&!"$#,H e  9 rr VVeV VHV,VVVVV#V$V"V!V&V',V)eV(HVVVVV VVrVVVVVVrVV V 9V VGVIVFVEVAIVBfVDVCVLfVMVKJVJ-VNVOVQVPr$PPQONJ-KJMLfCDBfAIEFIG3421s-.0W/:89;75:W;t=< Vrr  9 QNLfKJGFDAI-0W2378:W=)e&#"eH V 9 rr$Pr$PQPONMLfKJJ-IGFEDCBfAI=<;t:W9;8754321s0W/:.-)e(H',&$#"! eH,r V 9  r rU& V$ S$9rS$9S$9rS$9S$9 V U!?-G(Bf (AI(@- 0AI0@- B@-$=)=2=:=!=B-$#;-*;-0;- :;-:9=7A7=6,=5=3=2B6,B5B3B2A2$=7$=-=,=)e=(H?Wp+?W+W?W*B(H$V:t1,=/B/B-B,B)eB(HC;p+C;+WC;*=/^$!$-$:t&:%#"*"0! :"=!DX! C$ >e>H>,>>>>>GGGGGG,GHGe!A-$#+*+1s+ 1s 1s :+:"!A-$#+*+3+:+ : : :'s d$80W d$89 dG8! d$8! @-$N @$8B!C_-$:0: 08 0" +pDXrZJ$rVZ&$9]| $V[$9[ @$9[$t[9^ $9^ @$V^.$9_ $^. r] r[ rZ|Y>Vd'$r`$UV`@$V`$ytb aV^$VZ&$r\$|Y>[v ^$9 [vVu_&[$&[$-[$ &d$rc s$%|ZZ%_Z&_'$'stb 's` 's] 2`C$2d$3`3b3c.2`C$8`g$r-c r$0|_Z0t\0W\_$0W\_ @$;t\$0W^ $4^.$94;|Z4Y.$U4Y $-^ $/:V$9/:VV$6,UZ6,S!=d9$DXa$U=a`]$=a`$y/:c $/:e $9c.$9c U$<_Z=Y $GW$=W_ $$=W_$@ttWBY $y<|T=?W]!H;tbH;c. Ga`$yGa`]$NXa$UGd9$F|_Z?^.$U>;t]B|]!9P $GN$99N{$9N{$]>tO-BP$B|M;c.>;b = V$ :|[v :[v[v[v7UZ7UZ7UZ7UZ#^ $$]$:WWU$;W$tUTt SX$Bf!AI$@->u @t!rG LBe ~Dorado Hardware ManualMemory SectionAugust 1, 198534Memory Section Dorado supports a linear 22-bit to 28-bit virtual address space and contains a cache to increasememory performance. We currently use a 25 bit + parity virtual address with 256 word pages.All memory addressing is done in terms of virtual addresses; later sections deal with the map andpage faults. Figure 8 is a picture of the memory system; Figure 9 shows cache, map, and storageaddressing. As Figure 8 suggests, the memory system is organized into three more-or-lessindependent parts: storage, cache data, and addressing.Inputs to the memory system are NEXT (the task that will control the processor in the next cycle)from the control section, subtask from io devices, Mar (driven from A or by the IFU), MemBase,B, the fast input bus, and an assortment of control signals. Outputs are B, Md to the processor,the F/G registers for the IFU, the fast output bus (data, task, and subtask), and Hold.The processor references the memory by providing a base register number (MemBase) and 16-bitdisplacement (Mar) from which a 28-bit virtual address VA is computed; the kind of reference isencoded in the ASEL field of the instruction in conjunction with FF[0:1]. Subsequently, cachereferences transfer single 16-bit words between processor and cache; fast I/O referencesindependently transfer 256-bit munches between I/O devices and storage. There is a weakcoupling between the two data sections, since sometimes data must be loaded into the cache fromstorage, or returned to storage.The storage pipeline allows new requests every 8 cycles, but requires 28 cycles to complete a read.The state of the pipeline is recorded in a ring buffer called the pipe, where new entries areassigned for each storage reference. The processor can read the pipe for fault reporting or foraccess to internal state of the memory system.Memory AddressingProcessor memory references supply (explicitly) a 16-bit displacement D on Mar and (implicitly) a5-bit task-specific base register number MemBase. MemBase addresses 1 of 32 28-bit baseregisters. The full virtual address VA[4:31] is BR[MemBase]+D. D is an unsigned number.The 28 bits in BR, VA, etc. are numbered 4:31 in the discussion here, consistent with the hardwaredrawings. This numbering conveniently relates to word boundaries.Note that although the VA path is 28 bits wide, limitations imposed by cache and map geometry limitusable virtual memory to only 224 words.MemBase can be loaded from the five low bits of FF, and the FlipMemBase function loadsMemBase from its current value xor 1. The intent is to point base registers at active structures inthe virtual space, so that memory references may specify a small displacement of 16 bits ratherthan full 28-bit VA's. In any cycle with no processor memory reference, the IFU may make one. IFU references alwaysuse base register 31.Programmers may think of Mar as an extension of A since, when driven by the processor, Mar contains thesame information as A. fp#$q 5pFHf ar p ^eW \U ZA Y S W;C Up7 QZ P4C NiR LW I-\ Gb7qp& EB C!M" Bqp2 @7D >m :O 90%8 7f$< 5. 0s -pFqp +E(/ ){?y&tutLy%XBy";(y!!! p; A" /:% d G (yftD#y =Y)*Dorado Hardware ManualMemory SectionAugust 1, 198535The base register addressed by MemBase can be loaded using BrLo_A and BrHi_A functions. Processor Memory ReferencesMemory references are initiated only by the processor or IFU. This section discusses whathappens only when references proceed unhindered. Subsequent sections deal with map faults,data errors, and delays due to Hold.Processor references (encoded in the ASEL and FF[0:1] instruction fields as discussed in the"Processor Section" chapter) have priority over IFU references, and are as follows:Fetch_Initiates one-word fetch at VA. Data can be retrieved in anysubsequent instruction by loading Md into R or T, onto A or B datapaths, or masking in a shift operation.Store_Stores data on B into VA.LongFetch_A fetch for which the complete 28-bit VA is(B[4:15],,Mar[0:15])+BR[MemBase].IFetch_A fetch for which BR[24:31] are replaced by Id from the IFU. WhenBR[24:31] are 0 (i.e., when BR points at a page boundary), this isequivalent to BR+Mar+Id, saving 1 instruction in many cases.PreFetch_Moves the 16-word munch containing VA to the cache.DummyRef_Loads the pipe with VA for the reference without initiating cache,map, or storage activity.Flush_Removes a munch containing VA (if any) from the cache, storing itfirst if dirty (emulator or fault task only).Map_Loads the map entry for the page containing VA from B and clearsRef; action is modified by the ReadMap function discussed later(emulator or fault task only).IOFetch_Initiates transfer of munch from memory to io device via fast outputbus (io task only).IOStore_Initiates transfer of munch from io device to memory via fast inputbus (io task only).(Inside the memory system, there are three other reference types: IFU reads, dirty cache victim writes, andFlushStore fake-reads that result from Flush_ references which hit dirty cache entries.)The notation for these memory references has been confusing to people who first start writingmicroprograms. The following examples show how each type of reference would appear in amicroprogram:Fetch_T;*Start a fetch with D coming from T via MarT_Md;*Read memory data for the last fetch into TStore_Rtemp, DBuf_T;*Start a store with D coming from an RM*address via Mar and memory data from T via B.PreFetch_Rtemp; fp#$q 5pFHf bO ]s Zfpq pD XS V$ S_K QSxNJx"*M,;*Ka'xHJxxF$ Jz{$*DZ!xAJ(*?:*>&*<\j:x3x7Jxx$*6(x3Jx'*1-x/!Jx)*-Vqp,*+x(Jx)*'#x$Jx(*"x btRxX pO +-  :\t!+:!+:T!!!.:o L=XUDorado Hardware ManualMemory SectionAugust 1, 198536Flush_Rtemp;IOFetch_Rtemp;IOStore_Rtemp;Map_Rtemp, MapBuf_T;*Start a map write with D coming from an RM*address (Rtemp) via Mar, data from T via BRMap_Rtemp;*Start a map read with D coming from an Rm*address (Rtemp) via Mar.LongFetch_Rtemp, B_T;*Start a fetch reference with*VA = BR[4:31]+(T[4:15],,Rtemp[0:15]).IFetch_Stack;*Start a fetch reference with Id replacing BR[24:31]*and with D coming from Stack.IFetch_Stack, TisId;*Start a fetch as above and also advance the IFU to the*next item of _Id.The tricky cases above are Store_, Map_, and LongFetch_, which must be accompanied byanother clause that puts required data onto B. DBuf_ and MapBuf_ are synonyms for B_, anddo not represent functions encoded in FF; these synonyms are used to indicate that the implicitlyloaded buffer registers (DBuf on MemD and MapBuf on MemX) will wind up holding the data.The encoding of these references in the instruction was discussed in the "Processor" section under"ASEL: A Source/Destination Control". The ten possible memory reference types have thefollowing properties:Fetch_, IFetch_, and LongFetch_These three are collectively called "fetches" and differ only in the way VA is computed. In anysubsequent instruction, memory data Md may be read. If Md isn't ready, Hold occurs, asdiscussed below. If the munch containing VA is in the cache and the cache isn't busy, Md will beready at t3 of the instruction following the fetch, with the following implications:If Md is loaded directly into RM or T (loaded between t3 and t4), it can be read in theinstruction after the fetch without causing Hold. This is called a deferred reference.If Md is read onto A or B (needed before t2) or into the ALU masker by a shift (neededbefore t3), it is not ready until the second instruction after the fetch (Hold occurs if Mdis referenced in the first instruction.). This is called an immediate reference.The above timing is minimum, and delays may be longer if data is not in the cache or if the cacheis still busy with an earlier reference.Md remains valid until and during the next fetch by the task. If a Store_ intervenes between theFetch_ and its associated _Md, then _Md will be held until the Store_ completes but will thendeliver data for the fetch exactly as though no Store_ had intervened.Store_Store_ loads the memory section's DBuf register from B data in the same instruction. On a hit,DBuf is passed to the cache data section during the next cycle. On a miss DBuf remains busyduring storage access and is written into the cache afterwards.Because DBuf is neither task-specific nor reference-specific, any Store_, even by another task,holds during DBuf-busy. However, barring misses, Store_'s in consecutive instructions never fp#$q 5pFHf:bAt :` :_9 :]!%!\T+:Z !*!Yo:W!!V&:U !4!S:R"!!P Mrp; K+/ IA H0( DA! B.) A   8$ C? A \ <]LEDorado Hardware ManualMemory SectionAugust 1, 198537hold. A fetch or _Md by the same task will also hold for an unfinished Store_.PreFetch_PreFetch_ is useful for loading the cache with data needed in the near future. PreFetch_ doesnot clobber Md and never causes a map fault, so it can be used after a fetch before reading Md.IOFetch_An IOFetch_ is initiated by the processor on behalf of a fast output device. When ready toaccept a munch, a device controller wakes up a task to start its memory reference and do otherhousekeeping.An IOFetch_ transfers the entire munch of which the requested address is a part (in 16 clocks,each transferring 16 data+2 parity bits); the low 4 bits of VA are ignored by the hardware. If notin the cache, the munch comes direct from storage, and no cache entry is made. If in the cacheand not dirty, the munch is still transferred from storage. Only when in the cache and dirty is themunch sent from the cache to the device (but with the same timing as if it had come fromstorage). In any case, no further interaction with the processor occurs once the reference has beenstarted. As a result, requested data not in the cache (the normal case) is handled entirely bystorage, so processor references proceed unhindered barring cache misses.The destination device for an IOFetch_ identifies itself by means of the task and subtask suppliedwith the munch (= task and subtask that issued IOFetch_). The fast output bus, task, andsubtask are bussed to all fast output devices. In addition, a Fault signal is supplied with the data(correctable single errors never cause this fault signal); the device may do whatever it likes withthis information. More information relevant to IOFetch_ is in the "Fast IO" chapter.IOFetch_ does not disturb Md used by fetches, DBuf used by Store_, or MapBuf used by Map_.There is no way to encode either IOFetch_ or IOStore_ in an emulator or fault task instruction, and thereshould never be any reason for doing this.IOStore_IOStore_ is similar to IOFetch_. The processor always passes the reference to storage. Thecache is never used, but a munch in the cache is unconditionally removed (without being stored ifdirty). A munch is passed from device to memory over the fast input bus, while the memorysupplies the task and subtask of the IOStore_ to the device for identification purposes. Thedevice must supply a munch (in 16 clocks, each transferring 16 bits) when the memory systemasks for it.The Carry20 function may be useful with IOFetch_ and IOStore_. This function forces thecarry-in to bit 11 of the ALU to be 1, so a value can be incremented by 16.Map_Writes data into the Map from the Bmux. fp#$q 5pFHf bO ]q ZfpA XL TVq Pp@ OF MO Iqpqp8 H"A FHH D}] BI @31 ?S =SI 9H 8.+ 6K\ 412 2U /D!9y,tRy+"* 'q #p%7 !': S . Q c)2  'M \K q p' v ^ ?3, >& :O 7Bqp@ 5x)8 33 t3p3 t3pqp 1)8 0> , $qp *1q p 'iH %X #8 " \ ?G t [q pT c TO M L M =])Dorado Hardware ManualMemory SectionAugust 1, 198540There are six other ways for the address section to be busy:(1)A cache reference or PreFetch_ that misses, or a FlushStore, transfers storage data intothe cache. At the end of this reference, as the first data word arrives, storage takesanother address section cycle.(2)The preceding cache reference hit but cannot be passed to the cache data section becausethe data section is busy transferring munches to/from storage (or to an io device if anIOFetch_ finds dirty data in the cache). Total time to fetch a munch from storage isabout 28 cycles, but the cache data section is busy only during the last 10 of these cycles(9 for PreFetch or IOFetch_ with dirty hit), while data is written into the cache. Thecache data section is free during the interim.(3)The preceding storage reference, or cache reference or PreFetch_ that missed has notbeen passed on to storage because the storage section is busy. Storage is busy if itreceived a reference less than 8 cycles previously, and may be busy longer as follows:successive cache references must be 10 cycles apart;successive write references must be 11 cycles apart;with 4k storage ic's, successive references must be 13 cycles apart.(4)A cache write (caused by a miss with a dirty victim or FlushStore) ties up the addresssection until the storage reference for the write is started; this happens 8 cycles after thestorage reference for the miss or FlushStore is started. Note that the new munch fetchstarts before the dirty victim store and that hold terminates right after the store is started.(5)A reference giving rise to a cache write that follows any other cache miss will tie up theaddress section until the previous miss is finished.(6)The address section is busy in the cycle after any reference that hits a cache row in whichany column is being loaded from storage.Any reference except IOFetch_, DummyRef_, or Map_ that hits a cache row in whichany column is being loaded from storage remains in the address section until theBeingLoaded flag is turned offi.e., for the first 19 of the 28 cycles required to service amiss, the reference is suspended in the address section; during the last 9 cycles of themiss, when the munch is transferred into the cache data section, the reference proceeds(except that a fetch or store will still be held because the cache data section is busyduring these 9 cycles). This is believed to be very infrequent.References to storage arise as follows:A cache miss (from a cache reference or PreFetch_) causes a storage read.A cache reference or PreFetch_ miss with dirty victim also causes a storage writeimmediately after the read.A Flush_ which gets a dirty hit causes a FlushStore read reference which in turn causesa storage write of the dirty victim.every io reference causes a storage read or write.A Map_ causes a reference to storage (actually only the map is referenced, but thetiming is the same as for a full storage reference).The following table shows the activity in various parts of the memory system during a fetch thatmisses in the cache and displaces a dirty victim; the memory system is assumed idle initially and fp#$q 5pFHf b< _xSx]).x[ YLxCxWGxUJ xS#8xR"BxPW. MxPxK?xJ#C:G4:E4:CD ARx7x?1,x=>x;qpJqp 9TxSx74 4xFx3 q px0Jx.q p< x,q p;x+"Qx)W,+x'Rx%@ "P'xIx@xIxPx$xB2xJx4 g[ C j U<]CDorado Hardware ManualMemory SectionAugust 1, 198541nothing unusual happens.Table 15: Timing of a Dirty Miss Time Time(Cycles)Activity of Fetch(Cycles)Activity of Dirty-Victim Write 0Fetch_ starts 1in address section 2-9in address section (wait for map) 3-18in ST automaton (generatesyndrome, transport to storage) 2-9in map automaton *10-17in map automaton * 7-14in memory automaton *15-22in memory automaton *14-21in Ec1 automaton22-29in Ec1 automaton **21-28in Ec2 automaton29-36in Ec2 automaton ** 27_Md succeeds* The map automaton continues busy for two cycles after a reference is passed to the memory automaton becauseit is necessary for the Map storage chips to complete their cycle.** The work of the dirty-victim write is complete after it has finished with the memory automaton, but itmarches through Ec1 and Ec2 anyway for fault reporting.The MapVA is transformed into a real address by the map on the way to storage. The hardware is easilymodifiable to create a page size of either 256, 1024, or 4096 words and to use either 16k, 64k, or256k ic's for map storage. The table below shows the virtual memory (VM) sizes achievable withdifferent map configurations. Table 16: Map Configurations ICPageVMAddressedSizeSizeSizeBy64k256225VA[8:23]Current configuration64k1k226VA[6:21]requires 16k-word cache64k4k228VA[4:19]requires 16k-word cache256k28226VA[6:23]256k210228VA[4:23]The cache handles virtual addresses, so the map is never involved in cache references unless theymiss.A consequence of virtual addresses in the cache is that it is illegal to map several virtual pagesinto the same real page (unless all instances are write-protected). This restriction prevents cacheand storage from becoming inconsistent.A map entry contains a 16-bit real page number (RP) and three flags called Dirty, Ref, and WP,which have the following significance: fp#$q 5pFHf b!^vF!y[u)WyZ )W1yWtyV!)W1)WT11S_yQ)W1yP)W1yO=)W1yM)W1yL{yI[yH|ByE(AyD}7 ?s <p3, :K#? 8N 6 2psX:-3q@!:+i@!:(s@(v!(s':&Op@&t!&Op':$@%t!$p':"#Gt@"p#Gt!"p: !|t@ p!|t! p },x  AH vE ' := qpqpqp o&L ( IqpD Gq p@xEQ 0xB5@6? :q 7fp R 5G 3 0_'qp* .q pE ,O )W/+ '!; %[ # $t#p$t#pE "-+ #yt#utu tyutut3y8t JRy<y9K y8Fy6Ky3Sy1I y0y-z'.y++ (=A &s` $ !Yu tm ZAut ut4utut [ ut` utu tut  nO K \#; [O yXUst stst s1yVdyULtsyT3tstst st sts"yR* Opqpqp7 MJ KM H|/:E2:D' ?q <\p[ :K 8T 6- 3$qp# 1B /C .*% *_ (qp 9 '#E %XH #? !M B F /sp@ 0/ ' ^ B  *, UK  C=[GDorado Hardware ManualMemory SectionAugust 1, 198545Tasks 1 to 16 generally cannot find out the SRN for their last reference. Even if this weredetermined somehow by polling all the pipe entries, there would be no assurance that, meanwhile,a higher priority task didn't clobber the pipe entry.Because of its single pipe entry, the task 0 must wait for an earlier reference to finish or fault,before starting another. Of all task 0 references, only a fetch, Store_, or PreFetch_ might fault.However, PreFetch_ doesn't use the private pipe entry, so only a preceding fetch or Store_ mightstill be in progress when a new reference is issued. If the new reference is another fetch orStore_, it will hold until the preceding one finishes (no problem). Hence, the only restrictionimposed by the private pipe entry is that the task 0 must cause hold with _Md before issuingMap_, Flush_, or DummyRef_, if a fetch or Store_ might still be in progress.When the Pipe is AccessedConceptually, the pipe is a history memory of events that happen in the memory system, it is usedonly for debugging. It is 6 words wide by 16 locations. Each memory or pipe reference stores thefollowing information:VA (28 bits)Task (4 bits),Subtask (2 bits),Cache control bits, (15 Bits)The 20 bits of map informationThe error correction-detection information. (12 Bits)The memory system needs one cycle for each of these accesses.Faults and ErrorsErrorsSeveral events cause memory errors from which the system does not recover. Errors halt theprocessor if the MemoryPE error is enabled (see "Error Handling"). If MemoryPE is disabled, theprogram will continue without any error indication. MemoryPE conditions are:Byte parity errors from the cache data memory (checked on write of a dirty victim, not on_Md or IFU reads); the processor checks Md parity and the IFU checks F/G parity;Byte parity errors from fast input bus;Cache address memory parity errors.FaultsOther events cause faults. A fault condition is indicated in the MapTrouble, MemError, andEcFault fields of Pipe4 when it occurs; in addition, the fault task is woken to deal with thesituation unless NoWake is true in Mcr. The encoding of the various errors is as follows: fp$q 5pFHf b/- `SE ^5 [R YL30 WP U)5 S5+ R"4( PWL Lq HpF F,4 E  C@ Au ? = < :K6 6= 2pr .*q *p@ (qp*qp '#5qpy$&3y"5y 'y}# 8q pqp)qp qp7 1qp; =V!Dorado Hardware ManualMemory SectionAugust 1, 198546Table 17: Fault IndicationsKind of ErrorNameMapTroubleMemErrorEcFaultMap parity errorMapPE11Page faultPageFlt10Write-protectWPFlt10Single errorSE001Double errorDE011In the above table, WPFlt and PageFlt have the same encoding; these must be distinguished bymeans of the Store' bit in Pipe5 and the WP bit in Pipe4; WPFlt can only occur for Store_,IOStore_, or dirty-victim stores that encounter WP true.MapTrouble might be true and reported to the fault task on a fetch or store that misses or anIOFetch_, IOStore_, FlushStore, or dirty-victim write. Flush_ and DummyRef_ never causeMapTrouble. Map_, PreFetch_, or IFU fetches might record MapTrouble in the pipe but neverwake the fault task. Map faults on IFU fetches are reported instead to the IFU, which buffers thefault indication until an IFUJump occurs to an opcode with at least one instruction byte in theword affected by the map fault; then a trap occurs, as discussed in "Instruction Fetch Unit".SE and DE may occur on any cache reference or PreFetch_ that misses or on an IOFetch_.Map_, IOStore_, DummyRef_, and Flush_ never cause these errors. Also note that fault taskwakeup on an SE requires not only NoWake false but also ReportSE true in Mcr; the faultindication transmitted with the munch for an IOFetch_ is set only for DE, never for SE.The special things about a fault are:If a program obeys the rules given earlier, hold will occur until any fault is reported oruntil the program can proceed safely.EmulatorFault in B_FaultInfo is set true if a fault is described by the emulator or faulttask pipe entry (0 or 1) pointed at by ProcSRN;FirstFaultSRN in B_FaultInfo is loaded if FaultCnt is -1 (indicating no faults) or ifFirstFaultSRN was previously zero;FaultCnt in B_FaultInfo is incremented;B_FaultInfo stuff is updated and the fault task is woken at the end of the storagepipeline, but sufficiently in advance of hold termination that it will surely run first. Forthis reason, any operation that might fault is illegal with tasking off.References leave the pipeline in the order that they entered.Pipe entries identified by EmulatorFault, FirstFaultSRN, and FaultCnt representcomplete storage references;The task that faulted is not blocked; hold terminates as though no fault had occurred;the task will continue unless the fault task 17 changes its PC.The fault task 17 is expected to read B_FaultInfo, service all faults it describes, service stackunderflow or overflow, then block. Because it is highest priority, the fault task cannot do muchcomputing (io tasks that are lower priority have to be serviced); probably it should not make any fp$q 5pFHf!brX:^q #$ ,5:\pq&-p/D6:ZC q&,p/D6:Xx q&,p/D6:V q&,p/D6:T q&,p/D6 Pqpqp ) N qpqpqp M0qp Iq p5 GR Fq p0q p D7 T BlF @C =/qpqp. ;eE 9 qpqpqp 75qp qp 4^%y1UKy/%y,q p:y+"/y(q pqp#y&q py$qpy!}@qpyYyHyI=y:q p;q pqp yyB*,yw? :' ;M pI x )=\qDorado Hardware ManualMemory SectionAugust 1, 198547memory references itself. Its normal actions are:crash (uncorrectable data errors, map faults by tasks other than the emulator);block letting the task that faulted continue (correctable data errors); orchange the TPC of the emulator to an appropriate trap routine (emulator map faults,stack overflow or underflow).EmulatorFault and FaultCnt are automatically reset by B_FaultInfo. These can be read withoutreset in B_Pipe2 (primarily for use by Midas).Several faults could occur while the fault task is running (due to references initiated before thefault task was awakened). In this case, when the fault task blocks, it will continue because of thepending wakeup, and so service the faults. Only while the fault task is running or while tasking isoff is it possible for FaultCnt to become greater than one.Error Correction Faults For error correction purposes, 16 word munches are divided into four quadwords, each containing64 data and 8 check bits.At the end of a storage read, the hardware indicates DE after a double-error or SE after a singleerror as discussed earlier. The SE or DE indication is unambiguous assuming at most two bits inerror in any 64-bit quadword; for an odd number of errors greater than 2, the hardwareerroneously reports an SE; for an even number of errors greater than 2, DE is reported. If severalquadwords in a munch suffer errors, the hardware reports the first DE, if any, or the last SE, if noDE's.Error correction can be enabled/disabled by the LoadTestSyndrome function. When enabled, thehardware will correct any single error. For double errors the hardware does not modify any bitsfrom storage. The normal mode of operation is: single error correction and double error reporting.The absolute address of the quadword containing the reported error isRP[0:15]..VA[24:27]..quadword[0:1].SE and DE are derived from the 8-bit syndrome field in Pipe4. Syndrome = 0 means no error;neither DE nor SE should be true in this case. Syndrome non-0 with an odd number of 1'sshould have SE indicated. Syndrome non-0 with an even number of 1's or an invalid word codeshould have DE indicated.See Figure 11 for the correspondence between syndrome and bits within the quadword. fp$q 5pFHf b2y_Oy\JyY>yW; Sq pqp? Q. N T LG J"B I-qp Dqr Aup'qpqp ? <8X :nDqp 8$2 6-6 5=qpqp 3C 1yO />" -b *r>3? (# %5A #jT !@  cqS %< IsQ G D7!= Bl9 >&r :pqp< 8@ 7U 5UU 30 0G .M%: ,I * 'F+qpqpqpqp %|>qp #K !, t P Eup S '7 J1/ ; sp )%Bsp b  s p-  $ :q 7Bp6U7B67B+67BE 5x^ 3Px1q~p*~/D1~-z3~+!#~)3~(:x%|q~p.~#>x!q~p9~Hxq~p'~xAq~p-xq~pAqp~0x:q~p7~o (=X*Dorado Hardware ManualMemory SectionAugust 1, 198551DisHold"Disable Hold" unconditionally prevents hold and BLretry from occurring.NoRefDisable storage references.WMissWakeup fault task on every miss.ReportSE'Don't wake up fault task after (correctable) single errors.NoWakeNever wakeup fault task.During normal operation every bit in Mcr should be 0, except possibly ReportSE', if correctableerrors are not being monitored. It is illegal to load Mcr while references are in progress.TestingThe memory system of the Dorado is designed so that each board can be run with the boards above removed. Themain memory diagnostic MemA can be broken down into 4 parts:1. MemC board.2. MemX board.3. MemD board.4. Storage boards. (MSA)Each part of MemA can be run alone.MemA runs all of the 4 tests and takes about 5 minutes with 64k memory chips. (21 minutes with 256k chips)MemMisc is a test of the map and long fetches.To test a memory system fully you need to run: Testall, MemA, and MemMisc. fp$q 5pFHfxbq~p0x_q~px\q~pxZCq~p;xWq~p TFqp R6& Mr JpXl I-< G F$ D C A# >j ;. 8J 6B1VInstruction Fetch Unit OrganizationBMux.0..15Jump displacementPcJpAdder>>>>>>baiiWantIfuRef'pTo memory>>>Jump displacement H if LengthK=2; SignK extends H.0=BMux.0..15ToProcessor=SignK supplies top 11 bitsTwoAlphaK..NK if LengthK=1;PC PipelineTypeJumpMSignMLengthMIfuRBaseSel'MemBMTypePauseK'TypeJumpK'TwoAlphaMTwoAlphaKMemBKRBaseSelK'LengthK'SignKNKNMSignXLengthXNXTwoAlphaXJHIfuAddr'InstrAddrK'FGpp918{GDv'}{PcFG.15}FGefcdFGParityErrBrkInsTestH8>>>>>>>>>>t1t0t0,t1t0t0t0t1t3t1t0,t1efcddcfeefcdRamParityErrMemoryTo IFUFGAlphaMCache>InsSet28igh>To control section>>To processor sectionTo processor section2311418SectionPCX'Junk'IFUMRH'IFUMLH'M-LevelX-LevelK-LevelTrapAddr'101TrapConditionTrapAddressF>RamParity.0other bitsother bitsother bitsRamParity.1RamParity.2IFUM1024 wordsRamParityErrInsSet..74Not ReadyInsSet..34RescheduleInsSet..14FGParityErrInsSet..04K FaultInsSet..00Lowest priorityHighest prioritypIfuFaultTo IFUhgId.signghId.0..3Alpha/Betat0AlphaX.0..3AlphaX.4..7t0Id.4..7pppToProcessorSection15Mar.1..15'16PcFPcFGPcJPcMPcX>>>>>>>>>>>>>>>>>>>>>>>x 27 bitsD1IFU.silFigure 129/5/79rr#t] +\+Z\ $Z 9$Et|U]|+$ZJ$UZ&N$Z&$ydt[f[$[$U\$`C+$#]$]|N$]|$YQ$YQN$#Yu$\+$Z$+^$Z$|[/WX!YXW+]!+]!+[/#^9$+\$`$$et` -_$5|\9u_J %|W&\+$*Yu$&YQN$&YQ$#Z$-IYQ$-IYQN$1sYu$-I\+$,,W*Z$2W3\+$8Yu$3YQN$3YQ$1sZ$+tc.a!G`8Zd$>U$?WX >X$AuW<?WV Gta_`8e;P$?9$8e9$8e9$8e6$8e6$?7$8e8$ pU .t,s 01s07I.& 0W)"/ "- /:4; "4 "*:"'s "7"2I":1s::W1s:7I;t:9;4; .e2$51,$.e1 $.e1 $.e6$.e6$57$.e8$.e(%$5&$.e&z$.e)A$.e)A$5)e$.e*$.e$$5#H$.e#%$.e5{$53$.e9$.e9$59$.e;P$.e-$5,,$.e, $.e, $8e1 $8e1 $?1,$8e2$?3$8e5{$7%+$5$94N$4$]<%$]<%N$^+$VL$ L$Hp5WH< N9$ L9$ E9$ G9$ E$]VE$9M;$GM$GNX$GG$GF$GF$G0t#"$ dL$dK$ K$ J$dG$dH$ G$ I$dG$ pM; FdJQG$|FG2I$tKO-$+PuFD t6 G/$ G03$ G0z$ G0$ G1 $ G1P$ G1$ G1$ G2%$ |.u .u .u .u G0$t1, 6$ +:{r$ +3 :X(HX.X5X!`g=fM;HF*3$*z$*$*$*O$*$*$*%$*l$,|,-I-I-I-I,,*$*A$*$*$*k$*$$*$*$*O$*k$*$*$*A$*$*$*$*]$*$,,-I-I0O$0k$0$1,$1,kV$2It UT-:GBGUBGUBG 9pQuItJt 5$.e$0W<8e>$8eA>$A>$?=Br$?:{$A:{$A;$?7$B7$B:{$DX9$DX<$Et<IX|<IX9IX..Fu8D7 D5%:^u$$t_J._ $ZJ$$e[f p^. :Z'Z.Z5Z9YQ$9W$9V$=|W=U=T==R-I9-I6-I4-I0-I..-I).-I&g-I#-I JC;9C;:C;8.C;67I47I67I07I..;t +G7I97I<]|$1 9$:t' ?Wu !r ?WudC9dJ b MEMORYSYSTEM//ISJ-LEVEL2 BITSM LEVELX LEVELPCFGPCMPCXPCJIFU DATATO BYTEPOINTSTO WORDOP AT JOP AT MOP AT XNKH181+1+1+1PCFPOINTSTO BMUX16 BITSHDVMDVBRKINSTESTIFUBMUXIFUBMUX16 BITS8 BITS + SIGN EXTENDNXILXINSTRUCTION SETIS.0ADDERBMUXBMUXENABLE16 BITS16 BITS16 BITSINSTRADDR10 BITSRAMPARITY3 BITSM LEVELILNMEMB01342MXSIGNRBASESELTYPATYJMPM LEVELK LEVELMEM FAULTTO IFUMAR16 BITSVALID RAM = JDV + NO PROBLEMSKREADY = FOR AN _IFU DATA THE FOLLOWING THINGS WILL COME OUT OF THE IFU ON IFU DATA:DURING A JUMP YOU WILL ONLY GET INSTRUCTION LENGTH FOR AN _ ID.JDV + LENGTH = 1JDV + HDV + LENGTH = 2JDV + HDV + FGDV + LENGTH = 3KREADY = KREADY = JDVEXECPTIONADDRESSPROCESSORRAM OUTPUT27 BIT/1K RAMFDVFGDVKREADY0:30:1ALPHA 0:7ALPHA 0:3F-BYTE 0:7G-BYTE 0:7F-BYTE 8:15G-BYTE 8:15TO CONTROLPageDateRevDesignerProjectFileXEROX1CSLVESTDORADOIFU BLOCK DIAGRAMIFUBLOCKDIAGRAM.SIL1. ENCODED CONSTANT (N)2. 3. BETA4. INSTRUCTION LENGTH0:30:10:9N= 17 MEANS THAT THERE IS NO CONSTANTIF YOU DO SEVERAL _IFU DATA'S YOU WILL EVEUTALLY ONLY GET THE INSTRUCTION LENGTH(COULD BE TWO FOUR BIT QUANTITIES IF 2ALPHA BIT SET)FG 0:7 + PARITYPCFG.15GDV'S1S28 BITS + PARITY"H" LOADSAT T1X0X1X2X3GDVIFU DATA GOES TO THE PROCESSOR AND ALSO TO THE MEMORY SYSTEMPCFG.15IS.0XOR WITHPCFG.15"J" LOADS AT T0D5-14-82tZYsM_LBI V$$G$9G y$G$]G$9VH_ J sJ $HKJG$A$A$$7H$$A4$U4^k$4^$y5]-%$y]-% r$$-I$U]0z r$%.e $$(%0z9$/^-I$U(%-%]$(%-%$y(%4^$y(%4^]$/^4$U(%79$ 0$+z0$(G9$/:D{$U(DX]$(DX$ysOt $+WH$+W7$ &C;$&C;$]K&$8Yu$y8Yu $BY$U8\ $BP$U8P$y8eDX$y8eDX k$BD{$U8eG G$8B7 $B4$U8B4^ $8B4^$y8B-%$y8B-% $B-I$U8B0z $9;Q9^59^.e9;E+z',$"' $"$e$=QC<[C$$B>^B@GC;JAd$LA$CR< +$LR<$ B[ $;_$>;]5$9;ZCI$C;V$BSX$=R_:{&:$&R_$$&R$$&R$$&S4$$&S$$&R$$&zR$$F&BB$$FIBf$$FmB$$FB$$FmB$$FIB$$F&C$$"s#$$"O"$$","$$""$$!"s$$!"O$$!",$$+1 $$+0$$+0$$+z0$$+W0$$+30$$+1 $$+8B$$+8$$+z7$$+W7$$+37$$+8$$*8B$$+H;$$+H$$+zG$$+WG$$+3G$$+H$$*H;$$+WG$G&Z$$&Z$$&Z$$&[$$&[f$$&[C$$&z[$$C;Q$$CQ$$BR$$C;R$$CR$$BR_$$BR<$$C;Z$$CZ$$BZ$$C;[$$C[f$$B[C$$B[$$=1 $$<0$$<0$$<0$$<0$$Tt$$>]X$$>]5$$>^]$$>;\$$>]$$=]5$$=]X$$!V1 $$!30$$!0$$ 0$$ 0$$ 0$$ 1 $$Jt$$JQ$$J-$$sJ $$OJ-$$+JQ$$Jt$$Km$$KJ$$K&$$sK$$OK&$$,KJ$$Km$$Km$$KJ$$K&$$K$$eK&$$AKJ$$Km$$>^_G$=(l$$<(H$$<(%$$<($$<(%$$;/^$@ $@ $@ $@ $&WXU$/^X|$$/X$$/X$$/X$$/Y $$/Y.$$/^YQ$$)X$0WX| 0WW_,s`-l[C$-[$$-[$$-[f$$-l[C$$-I[f$$-%[$$-[$$.e]-^$$-^u$$-^Q$$-l^.$$-I^ $$-%]$$-]$$rer, rK @ ,  r r 2K$2K$5L$d2M_$/A&2$03?<% ; 9;$" $ . k0$0$$0$$0$$k0z$$H0$$$0$$0$$V0$$20$$0$$0z$$0$$0$$0$$0$O8B$$+8$$7$$7$$7$$8$$y8B$$k8B$$H8$$$7$$7$$7$$8$$8B$$9^$$9;$$9$$8$$k9$$G9;$$$9^$$29^$$9;$$9$$8$$9$$9;$$]9^$$9$$!V$$$!3$$$!$$$ $e$$ $$$ $$$ $$$e$$$A$$$$$$$e$$$$$$$$$$$? H Ir$BF9$C>$FF+$FB$D{f$ 7$4$U 4^$4^$$8B$$d8$$A7$$7$$7$$8$$8B$$@t$@7$ O7$ O@t$@O8B$$,8$$7$$7$$7$$8$$z8B$$O8B$$+8$$7$$7$$7$$8$$z8B$$@t$@7$ O7$ O@t$@8B$$8$$7$$7$$7$$d8$$A8B$$2%M_$$2%K$$2O 2%N$$2%PJ$$2PJ$5O $d2N$2N$5PJ$$4;M$$4M$$3M$$3M$$3M$$3M$$3eM$$3M$d0N4$0K&$20K]$3J $3J $4JQG$4^J-G$4J G$3BG$$4I$$4J $G4I{$$4I$G4IX$$4^I$G4;H$G4H$G3H_$$3H;$$3H$$3G$$3eG$$3eG$$2H$G2H$G3H$$2H;$$2H_$$2H$$2lI$G2IIX$G2%I$k2J $k2I$2J $$2J $$2J-$$2lJ-$$2IJQ$$2%JQ$$3eC;$G7?$@3B3eB$3eB$5A&$1; 6PA$$6,Am$$6 AI$$5A&$$5AI$$5Am$$5{A$$1,B9$1,A&$1,>^$@1,>;d$2<$5>^$@4^>;$4^<$4^<$$C_!C_$', $% VZ V^. VY. V\ - OOt$$sK&$kOO$$O$$OQ$$OOQ$$Jt$$JQ$$J-$$lJ $$HJ-$$%JQ$$Jt$$GrNXGGrrGr!VGr:Gr>;GrGGrG>;t390Gr!pUNXGH;3t%:p9!tNXGrrrH$$]$$$$$$A$$d$$k$$$$k$$k$$9$$9A$$d$$d$$d$$dG$d$$d$$A$$k$$2k$$k$$$$$$]$$$$$$$Gr rV)!V)U19=$r%7$G$A$$ dP H5S&WQC$P$rP$&WP$@:\_V$:Y V$:ZV$:^ V$:UJ$ rU&]$rU&$ r_$VUVUU&$:V$:U$\_$S$ rR $_'$sO$UM(E+WFI+WE-^.\ZY./?$@/?$2?$$4^Ay$4^?$@4?U$5?{$G1,?{$G2?$$2>;$$3?9$3?4$3A$2IBBd$2IA$2A$$2A$$2lAm$$2IAI$$2%Am$$2A$$1A$$2IAm$$2?$d2A&$$2?G$1,A$37$3eC_$r2LB$A$VV9$ +<)SX)Q)R<2IR5A$]8$N7$$8$$7$$r7$$N7$$+7$$7$$8$$N7$N8$$9$@7$$H;tp>tNh.Dorado Hardware ManualInstruction Fetch UnitAugust 1, 198552Instruction Fetch Unit The instruction fetch unit, or IFU, decodes a stream of bytes from memory into a sequence of 8-bit opcodes and operands using a writeable decoding memory, and presents the results to theprocessor for efficient interpretation. The next section contains an overview of IFU function,supplemented by details in later sections.Read this chapter with Figure 12 in front of you.Overview of OperationThe IFU handles four independent instruction sets. Opcodes are 8-bit bytes, which may befollowed in memory by 0, 1, or 2 operand bytes. The total length of an operation is 1, 2, or 3bytes. The first operand byte is called a (Alpha), the second b (Beta).The term PC refers to the displacement of an opcode byte from the codebase, which is BR 31.PC's are 16-bit items, where 0:14 are an unsigned word displacement relative to the codebase, andbit 15 selects the byte. In other words, codebase points at a 32k segment of virtual memory; a PCselects a byte in this segment. The PC's are named PCF, PCM, and PCX, where the final letter inthe name denotes the level in the IFU pipeline.For Alto compatibility reasons, we currently have the following kludge. Instruction sets 0 and 1treat byte 0 in the selected word as bits 0:7, 1 as bits 8:15; instruction sets 2 and 3 treat byte 0 asbits 8:15, 1 as 0:7. Eventually, this may be changed so that all instruction sets use 0 for the bytein 0:7 and 1 for 8:15.The IFU is started by first selecting an instruction set (InsSetOrEvent_B function) and thenloading the F-level PC (PCF_B function). The IFU then starts fetching the byte stream startingat the word BR[31] + PCF[0:14], byte PCF[15], from the cache and prepares opcodes forinterpretation by the processor.Bytes from the cache then march through the IFU pipeline beginning with the F and G full-wordbuffer registers on the MemD board; single bytes from F/G then move into J and H on the IFUboard. InsSet[0:1] and the opcode byte in J address the decoding memory, IFUM, a 1024-word x24-bit (+3 parity) RAM containing the information in the table below. Although IFUM iswriteable, it will normally be loaded with the microprogram and not subsequently changed(Diagnostics are, of course, an exception.). fp"sq5pFHf arp ^eB \? Z,3 Y*UqX1 Pzs MpR K> T Is)tptp Fqp6qp D7E Bl] @L >/ ;e_ 9d 7V 6 2A 0(7 .2# -3 ) O '9" &,] $a!6 "= ,  =GDorado Hardware ManualInstruction Fetch UnitAugust 1, 198553Table 18: IFUM FieldsNameBit Size ContentsLength' 2Opcode length: 1, 2 or 3 bytes (0 length is illegal).TPause' 1The opcode is of type pause.TJump' 1The opcode is of type jump.IFaddr'10TNIA[4:13] of the first instruction to be executed in interpreting this opcode(TNIA[14:15] from the IFUJump in the exit of the previous opcode).RBaseB' 1RBase initialization.MemB 3MemBase initialization.Sign 1Operand sign extension.Packeda 1Packed a, use the Alpha byte as two 4 bit nibbles.N 4Operand encoded in the opcode.Length', TPause', TJump', Sign, Packeda, and N are used by the IFU to prepare operands and tosequence correctly to the next opcode; IFaddr' is passed to the control section; and the processoruses MemB and RBaseB' to initialize MemBase and RBase when the microcode for the opcodecommences.Length' determines the number of operand bytes; a for a two or three-byte instruction will be inH, while b for a three-byte instruction will be in F/G, when the assembled instruction is ready toproceed. The assembled instruction and a then drop into the M level.IFU JumpsIFU jumps are often talked about in simple terms, but a lot of things have to be in place beforean Ifu jump can work.1. Ifu memory has to be loaded with values that decode the 8 bit opcodes in the "J" register. The"J" register address 1 of 256 different locations in the Ifu memory.2. Virtual Memory must be loaded with the high level program that we are going to run. (Cedar,Mesa, Lisp... etc.)3. Instruction Memory must have microcode loaded that correspond with the opcodes that arebeing decoded.4. The IFU - F/G, H, and J registers must be loaded. This is accomplished by a PCF_Binstruction.IFUJump[n] causes the Ifu memory to decode the opcode in "J" and produce a 10 bit value usedto make a Instruction Memory address. where TNIA[4:13]_IFaddr, TNIA[14:15]_n (n is a 2 bitfield) is the location of the entry instruction. IFaddr may be overruled by a trap address whenappropriate.Instructions that implement the opcode then reference operands in sequence using the A_Id,RisId, or TisId operations discussed in "Processor Section" or the IFetch_ operation discussed in"Memory Section," which read operands from the X level. The operand sequence delivered bythe IFU in response to _Id is as follows: fp"sq5pFHf%9bsX_uxZ]KvxxZ/[xxxwvZ xxxwvXx x2!~W;BUxT3xZRxZQxtvxZtv*O`xZ Lq tpqp/ JGqp4 H|qpqp; F C@qp)tp) AutpX ?(tp <8s 8p;% 7 3[ 1D /<" .* ,_Z * (: ' #j8$ ![ 2qp  5% $= M 9) ( &wvwv(wvwvwywv 6p+tptp 4:#qp& 2p%9 0-tp .tp tptpqp %q -ptp' )6qp# '4qp" & qpE $>y qpq tqp0y*uvpuvpyqpqtpqptpqpytpqpyv qp F :+qp oqp9 D & ^Jw$<v$';$'  9t$v't8v$'x6(ZZ6tv4S3C$x1yZ>/w$-v$,$',+"$')$'tv.(&$' %X$'#$'"$'!6$'$. x ZZ;x@Z @8xuZ6xZ,(JB xZ%w Tm%. =>m<%.x:ZZV9 M89) 3Cs /pA . T ,<G '#s* #p Y !(6 2 \ *5 _ JS -/ U s T=YDorado Hardware ManualInstruction Fetch UnitAugust 1, 198557The IFU may trap for not ready, reschedule request, map faults, cache data errors, and IFUMparity errors. When a trap condition occurs, the IFU substitutes a trap address for IFaddr on thenext IFUJump.IFU trap Locations in the MicrostoreReasonLocationsCommentReschedule request*14-17Indicates that some previous instruction executed the ReSchedulefunction.IFUM parity error*74-77Indicates a hardware failure in the IFUM storage.IFU not ready*34-37The instructions in this vector should contain IFUJump[n], waitingfor the IFU to become ready.IFU data parity error *4-7Parity wrong on data from cache.IFU map fault *0-3The IFU buffers the fact of a map fault and completes allopcodes in the pipe ahead of the one experiencing the fault.Upon dispatch to the first instruction for the opcode affected bythe fault, this trap occurs.*Each trap has 4 locations in microstore reserved. A map fault for IFUJump0 would go tolocation 0 in microstore, IFUJump1 would go to location 1, IFUJump2 would go to location 2,and IFUJump3 would go to location 3. Each trap vector is dispatched into by IFUJump exactly as though it were an opcode. The relative priority of traps is as follows: IFUM parity error is highest, then NotReady,reschedule, cache data parity error, and map fault.The NotReady trap occurs whenever the IFU does not have both an opcode and its associatedoperands (a, b) ready for the processor. Since PCX, MemBase, and RBase are invalid, the trapmicrocode must wait for the IFU to become ready. If the IFU detects bad parity on any read ofIFUM, the IFUJump to the opcode affected by this parity error will trap to the IFUM parityerror trap location.The IFU will trap at the cache data parity error location, if it detected invalid parity on any bytesent by the memory system. PCX will always correctly point at the opcode that would have beenexecuted next had the trap not occurred; however, the opcode and operands pointed at by PCXare not necessarily the ones that suffered the parity error. This occurs because the Opcodes arefetched ahead of PCX. The most confusing case occurs when the opcode following PCX was ajump; in this case the opcode fetched by the jump may have caused the parity error,.The IFU will hold an IFUJump in the cycle prior to a cache data parity error or IFUM parityerror trap.The Reschedule function is used by I/O tasks to request service by the emulator (task 0). TheIFU will honor this trap request on the second IFUJump after it is executed. The RescheduleNowfunction is like the Reschedule function, but the IFU honors it on the first IFUJump after it isexecuted, rather than the second.An IFU fetch may experience a map fault. The memory system does not report map faults fp"sq5pFHf b[ `S5- ^ cYLsX$xV!wR'xSvR%57%5QxOR%5(xN# R%5*%5LxJR%5xI- R%5%5G#%5Fk'%5E  ?p4# >&"9 <\' 8U 5xL 33 0;N .q tptp@ , qp". *+/ ) %[ #+3 " N ?a t5$ T 8? m ? 1(qp fFqp ! F <]L?Dorado Hardware ManualInstruction Fetch UnitAugust 1, 198558caused by in IFU memory fetch to the fault task (task 17). Instead, it signals the IFU that a mapfault has occurred, and the IFU passes this indication through its pipeline. Eventually, theIFUJump instruction that would have sent control to the opcode affected by the map fault willinstead transfer to the map fault trap vector.An IFU fetch may experience single or double storage failures. Unlike map faults, these arereported to the fault task just as on processor fetches. The memory system pipeline will finishloading the cache munch just as though the data were ok, and the cache entries will have validbyte parity. The IFU will continue running just as though no error had occurred.However, the fault task will be woken soon enough that it will run before the IFU's F/G registeris loaded with a byte from the bad munch. Hence, the fault task will run before the emulatorcan possibly execute an IFUJump to the byte that suffered the error.For a recoverable error, the fault task can simply carry out some logging action and block; noharm will occur because the IFU will actually have gotten valid data, and the cache will containvalid data. For an irrecoverable error, the fault task must clear the bad cache munch and use theRescheduleNow function to trap the next IFUJump to code for dealing with the irrecoverableerror. fp"sq5pFHf b*8 `S> ^#: \. YL\ W` U? SQ PzA NN LD IsB G2. E<& D2( BI t B<& Dorado Hardware ManualInstruction Fetch UnitAugust 1, 198559IFU ResetThe processor can reset the IFU by executing the IFUReset function. This clears all IFU errorconditions, prevents further IFU memory references, clears the BrkIns_ feature, and generallyputs the IFU in a clean and operable state. The Reschedule feature is not affected by IFUReset.ReschedulingI/O tasks request service from the Task 0 by first indicating a request in some way (Presently anRM location is used as a 16-bit table in which 1's indicate requests.), then executing theReschedule function. The IFU and the processor store the reschedule condition in flipflops whichremain set until the NoReschedule function turns them off.The next IFUJump after Reschedule transfers to the entry vector for the opcode as usual; thereschedule trap address will drop into the IFAddr register at t2 of this instruction, and the firstIFUJump after that will dispatch into the reschedule trap vector. This means that secondIFUJump will trap unless the second IFUJump occurs on the instruction immediately after thefirst IFUJump, in which case the trap will not occur until the third IFUJump. IFUJump's thatexperience a NotReady trap are not counted. The entry vector at the reschedule trap location is entered as though it were the next opcode.When Reschedule is used by I/O tasks to request the wakeup of another process, this fact isunimportant. However, the other use of Reschedule is in continuation from map (and other)faults. In this application, the reschedule trap will wind up restoring the IFU state by executingan appropriate number of _Id's and eventually branching back to the instruction that experiencedthe fault. When the reschedule trap vector is entered, the IFU is in an undefined state except for PCX', andPCF_B is needed to restart the IFU at the continuation address.BreakpointsBrkIns_B implements debugging breakpoints straightforwardly. The idea is that a one-byteopcode, BrkP, is used to transfer control to a debugger while saving emulator state needed tocontinue later, and another opcode, Continue, is used to continue from breakpoints (For Mesa,BrkP and Continue are special cases of Xfer.).BrkP may be substituted for any opcode in a program. The debugger gets control when BrkP isexecuted, saves state, and eventually can execute Continue to restore state from values saved byBrkP.Reading and Writing IFUMIn addition to its function related to breakpoints, BrkIns_B is used to address IFUM whenreading or writing that memory.When IFUM is loaded, it is addressed by the instruction set InsSet[0:1] and BrkIns. The datamust remain on B for two cycles, so tasking must be disabled and the instruction following the fp"sq5pFHf br ^pC \S [Q Ur Rp,5 P L ND M,: Iqp&. G?GbsGp F$ L DZ O BX @, =S%q!p ;'4 9@ 7S 6(K 4^ 0<% /!? *r &pN $,1 #W !6. +1 )7 / r pD  X M0. =]Dorado Hardware ManualInstruction Fetch UnitAugust 1, 198560one with IFUMRH_ or IFUMLH _ must put the same data on B.WriteIFUM:IFUReset;*Stop future IFU fetches and clear the pipeT_41C;Cnt_T;IFUReset, GoTo[.,Cnt#0&1];*Reset after previously issued fetches completeInsSetOrEvent_RMaddr0;*Load 2 instruction set bits forming IFUM addressBrkIns_RMAddr1;*Load 8 opcode bits forming IFUM addressTaskingOff;*Ensure no B glitch below and let BrkIns_ settle for 1 cycleIFUMLH_RMdataHi;*Write high part of IFUMB_RMdataHi;*Keep data good a little longer (mustn't glitch)IFUMRH_RMdataLo;*Write low part of IFUMB_RMdataLo, TaskingOn;*Keep data good a little longerIFUReset, Return;*Clear BrkInsReadIFUM:IFUReset;*Stop future IFU fetches and clear the pipeT_41C;Cnt_T;IFUReset, GoTo[.,Cnt#0&1];*Reset after previously issued fetches completeBrkIns_RMaddr1;*Load 8 opcode bits forming IFUM addressInsSetOrEvent_RMaddr0;*Load 2 instruction set bits forming IFUM addressNoop;*Two instructions must elapse after loading BrkIns*one after loading InsSet (?Two noops after loading InsSet*might be better since this is a tight path?)RMdataHi_IFUMLH;*Read IFUM into RM.RMdataLo_IFUMRH;IFUReset, Return;*Clear BrkInsIFU TestingThe IFU test control register is loaded by the IFUTest_B function; when not testing, this registershould contain 1, and it is loaded with 1 by the IFUReset function. IFUTest.15 disables theperiodic wakeup request to the Junk task. when IFUTest.15 is 0, the junk wakeups occur 60times/sec and are dismissed by any IFUTest_ function. (The Junk task wakeup is wired to task 2and is used to keep the time of day clock)IFUTest.14 (TestEn) enables IFU test mode; it is illegal for this bit to change from 0 to 1 whenthe IFU is active because, if this occurred in the same cycle that an IFU memory reference wasissued, then the IFU would pollute the Mar bus indefinitely, making the memory system unusableby the processor.The test features aim at two situations. First, they allow the IFU clocks to be controlled by aprogram, so a diagnostic can slowly step the IFU through its stages. Secondly, they allow datasupplied by a diagnostic to be substituted for signals that would otherwise come from the memorysystem. This allows the IFU to be tested in the absence of the memory system, which allowsscope probes to be inserted easily and decouples IFU problems from memory system problems.The IFUSimple microdiagnostic is designed to run without the memory system removed.The TestFH' and TestSH' bits in the IFUTest register enable the first-half-cycle and second-half-cycle clocks, respectively, which will occur between t2 and t4 of the cycle after the one issuing theIFUTick function. Thus, the IFU can be stepped through a PCF_B function as follows: fp"sq5pFHf b9 ]s \T&+ZYX2&)V&1Up&(T &)R&QN &0O&N&M,&yJI-&+GFkE &)C&(BI&1@&2&?:&>&-<&;e:& 5r 1p V / N .#6 ,<@ *r* 'Y %5E #j.0 ! .J c T ` < &4 9S ?" 6osposp qp 2T qp FN Bqp BsBp3BsBp  @qp @8s@p<@8s >p9>ms>p =/0- ;e15 99 s9p/9 s9p 6Kqpqp% 2\ 1'q p /D6q p q -zpq p (`r $p M #$*9 !Y<% ! B RK Q ] R ()4 ]6  Z K=X]Dorado Hardware ManualInstruction Fetch UnitAugust 1, 198562Pipe control is straightforward in principle. The F and G levels are 16-bit registers filled from thecache. Following PCF_B, if there is space in the pipeline for another word, the IFU will start areference at t1 of any cycle in which the processor is not using Mar (so as many as 2 IFUreferences can be outstanding). Cache words are stored in F at t1, then dropped into G at t2;bytes drop into H at t3 or J at t4; there are bypass paths to get bytes directly from F/G into Jwhen H is invalid. As the processor executes opcodes, F and G become invalid, and the IFUrefills them from memory automatically. This continues until the IFU is reset by the processor, orencounters a pause opcode.The F and G registers are physically located on the MemD board. The four bytes in F/G are inputs to amultiplexor controlled by the IFU, and the multiplexor output is sent across the backplane to the IFU.BrkIns[0:7] or IFUTest[0:7] replace F/G data when using breakpoints, reading/writing IFUM, or using IFUtest features.The J and H levels are one byte wide. For one-byte opcodes it is possible to consider H and J asindependent levels of the pipe; however for two or three-byte opcodes, it is appropriate toconsider J/H as a single level in which J holds the opcode and H holds a.If J is invalid, then it will be loaded from the next opcode (which may be in G, F, or H accordingto various conditions) at an even clock (t0) and H will be loaded from the byte after the opcode(which is always in G) at the following odd clock (t1); if the byte after the opcode isn't ready, itwill drop into H at the next odd clock after it is ready. The InsSet and J registers address IFUMand IFUM outputs reveal whether the byte in H is a (Length = 2 or 3) or the next opcode(Length = 1).The conditions under which the M level can be loaded from J are that M is invalid (or about tobecome invalid) and:Length = 1 -or-Length = 2 and H is valid -or-Length = 3 and H is valid and either F or G is valid.If these conditions are met, then the M level is loaded (t2) with information from IFUM and witha, if Length = 2 or 3. If Length = 3, then b will drop from G into H (t3).If Length < 3, then the H/J level is now free to work on the next opcode. If Length = 1 and thenext opcode happens to be in H, then H will drop into J at the same time (t2); otherwise, J willbe loaded from the next opcode in F/G when it is ready.When the processor does an IFUJump[n], level M presents information needed by the nextopcode as follows:IFaddr is TNIA[4:13] for the IFUJump;MemBase is set to 0.MemBX.MemB[1:2] or 348+MemB[1:2];RBase is set to 0 or 1;N, Sign, Length, Packeda, and a are loaded into the X level;b is loaded into the M level if Length = 3.Referencing IFU operands with A_Id, TisId, or RisId affects the IFU in two ways: it causes theIFU to advance to the next item of Id, and for a 3 byte instruction when a is taken (a[4:7] whenPackeda = 1) it causes b to drop from M to X, freeing M for the next instruction. fp"sq5pFHf b] `S># ^ ]s^pJ \,\1s\p\1s\p ZZfsZpZfsZp> Y)G W^'< U qpyRsQyQqE!yP70yN KapB I[ GGtp DZ<& B*BsBp* @!@8s@p/ >I =/-tp% ;e 7^ 6(:2:0:/!5 +:+"s+p )tp+tp)Ws)p &qpD $> $>s$p #7 Q :R%:)sp ::tptp:(tp* *4 8tp tp tptp9 <\2oDorado Hardware ManualInstruction Fetch UnitAugust 1, 198563IFetch_ also uses Id, as discussed in memory section, but does not advance the IFU to the nextitem of Id.For a one or two-byte opcode, it is permissible for the processor to do an IFUJump beforereferencing any operands with _Id; this will advance normally to the next opcode. However, fora three-byte opcode the processor must reference all of a, so that b drops into X, before doing anIFUJump.When a pause or jump is recognized, the IFU may already have filled the F and G levelserroneously (i.e., 4 bytes ahead). These levels are flushed and refilled along the jump path. fp"sq5pFHf b"< `S \D ["= YL8tp tp W Tqpqp3 RE#; | Q< [Dorado Hardware ManualSlow IOAugust 1, 198564Slow IO (Input/Output)The slow I/O facility allows data transfers between the processor and any of up to 256independently addressed I/O registers. It is intended that the slow I/O facility will be used toload and read control information associated with high speed I/O devices (> 20 x 106 bits/sec),which will then use the fast I/O system for their data transfers. Low speed devices (< 20 x 106bits/sec) will use the slow io bus for all phases of their operation. Very slow or polled devicesmay be driven directly from an emulator.Device controllers for Dorado interact with the processor by exchanging data over a 16 data +2parity bits bidirectional bus called IOB ("Input/Output Bus"). There may be a total of up to 256I/O registers in all controllers connected to a single system. The unique 8-bit device numbersassigned to particular devices or uses that appear in every system are discussed in subsequentchapters and summarized in the table below.Table 21: I/O Register AddressesNumberNameComment10DiskControlDisk control register11DiskMuffDisk muffler control12DiskDataDisk FIFO data13DiskRamDisk format RAM14DiskTagDisk tag register15EDataEthernet input or output data16EControlEthernet control and status360PixelClockDDC pixel clock361MixerDDC mixer (Dorado Display Controller)362CMapDDC CMap363DWTFlag* (DispM analog of DWTFlag)364DHTFlag* (DispM analog of DHTFlag)365BMapDDC BMap366NLCB* (DispM analog of NLCB)367Statics* (DispM analog of Statics)370StatusDDC muffler and OIS data372MiniMixerDDC MiniMixer373DWTFlagDDC word task control374DHTFlagDDC horizontal task control375HRamDDC horizontal waveform control376NLCBDDC next line control block377StaticsDDC debugging control fp&q4]pG?f araaHaYa ^epV \H ZH []sZp Y`Ys W;pS Up( Q// P4%OP4)OP4-OP4( Niq p= L;# J+GbtX!yCq "s@p "s? "s=S "s ; "s9 "s7 "s6( "s4^ "s2 "s +2<212<262<2 0 "s. "s"-3 "s"+i "s) "s' "s"&  "s$> "s "s "s  "s "s "sI "s  3, GH FS BI!H?tXy;q 89p  6o 14 up2 1 (/D -z ++"s +p"))Ws )p#('s (p&O%s &Op$#s $p t pB R MSsp E KJ \ 9 DD y qpS T 2=]UDorado Hardware ManualSlow IOAugust 1, 198566to affect MemBase[2:3].In the memory section, the task and SubTask that issued an IOFetch_ is bussed to fast outputdevices with data from storage. The device receiving the data identifies itself by means of thisinformation. IOStore_'s are handled similarly.A task presenting SubTask signals generally must Block at the same location each iteration sincethere is only a single TPC value for all of the SubTasks. Hence, the full generality of tasking isunavailablethe microcode for these tasks must be coded as though the wakeup mechanism werea priority interrupt. fp&q4]pG?f b ^F \a [/ W,q*p U V TV RE d Q< ODorado Hardware ManualFast IOAugust 1, 198567Fast IO The Fast IO is used by the Dispy and DispM boards to drive the black/white and color displays.The fast input/output system provides high-bandwidth data transfers between storage and I/Odevices. Transfers occur in units of one munch (= 16 words). One word is transferred everyclock, for a peak bandwidth of 533 x 106 bits/second. A fast device is also interfaced to the slowI/O system, from which it receives its control information, since there is no way for the device tocommunicate directly with the processor using the fast I/O system.A single transaction of the fast I/O system transfers exactly one munch. Successive transactionsare completely independent of each other, whether they involve the same or different devices, asfar as the I/O system is concerned. The only relationship between transactions is that storagereferences of two transactions occur in the order that they were issued.Each fast I/O transaction is initiated by an IOFetch_ or IOStore_ reference coded in ASEL.Once this instruction has been executed, the transaction proceeds without further interaction withthe processor (except for fault reporting). The transaction itself involves a storage reference, andtransport of the data between main storage and the device. In the case of a fetch, transporthappens at the end of the reference, after the munch has been error-corrected. For a store,transport happens at the beginning of the reference, in parallel with mapping the VA and startingthe storage chips. As a result of this difference, the transport for a fetch may overlap or evenfollow the transport for a following store.TransportThe device is only concerned with the transport of the data, and has no way of knowing exactlyhow or when the storage reference take place. The transport happens in 16 clocks, eachtransporting a single word using the Fin bus (IOFetch_) or Fout bus (IOStore_). The two bussesare independent, and transport can be happening on both of them simultaneously.The two busses have much in common. Both have Task and Subtask lines, on which the memorypresents the task and subtask involved in the transport about to begin and a Next signal used forsynchronization. The Fout bus has a Fault line which is high at the time the last word of thetransaction is delivered if there was a memory fault during the fetch (other than a corrected singleerror).Both data busses are 18 bits wide: 16 data bits, numbered 0..15, and two byte partiy bits,numbered 16 (bits 0..7) and 17 (bits 8..15). The parity bits have the same timing as the data bits.A device is invited to check the parity of data on Fin, and is required to generate parity for dataon Fout.Wakeups The normal interface between a device and its task involves one wakeup for each munchtransferred. The device must keep track of the number of wakeups it has issued, since data maynot arrive from storage for several microseconds, but there is no way to stop the data fromarriving once the task has started the memory reference. fp&q5 pFHf arp ^eV ZW Y/. W;'WsW;p - Up"A SB P4$= NiF LJ JH Gb5% EA! CC" Bqp2" @7O >m)8 <\ :+ 5t 2Lp%9 0Q .7( ,O ){7# '@! %I $Q "P > ,8 I/4 ~ et p? )+4 ^#8 8 L=\/Disk ControllerTagRegisterControlRegister16-wordFIFOFormatRAMSubsectorSequencePROM4ReadPROMSequenceWrite884OtherControls>IOB12>DriveTagCylinderTagHeadTagControlTag12TagBusWordCounter>1216-word>>>16TagTW6Divider4>>SubsectorCounterSectorTWiiiselectedbabaIndexTWqqcdeffedc18>NotOnLineNotReadyNotSelectedHeadOvflSeekIncDevCheckcdeffedcReadOnlyFIFOControlFifoUnderflowFifoOverflowRdFifoTWWrFifoTWShiftRegister>iSelectErrorsFromDiskDrivesTo DiskDrives>DriveErrorsFromController<Radial cable iSelected.0Selected.1Selected.2Selected.3Selected.iBitClock.iData.iSubsecIndex.i16>>16Subsec.iIndex.iSubsec.iIndex.i>>&StatusCylinderOffsetNoTerminator<>MuffRegister168MufflerMultiplexorsDMuxAddress84fedcMultiplexor controls11<<>DMuxData>DMuxDataDMuxClockBoardSelectBoardSelectabFigure 139/5/79 rUHT G$HJk$I4$I4$HIX$M$H6 $H2%$rT$rT$HU$rX$%Gd$+D$%C$%C$ dZ$ dZ@$Z$ d^$tONKHI42VfdUJ&FI \< ZZ ]X _ a< dc$_$ d_@$ d_$ bXZn$a$`g$d\$\$^ $`C$]$U^$:X$+`$b+[$]_9$_$`_^V|S!tVW:|\HTk$#U$HXG$#O r$#N4 r$#L r$#Km r$&tO&NX &L&K #R $%R(R<&WQ$W<UHV$,|S!Vf$tWWP$N$#J$ rP$O$ 9N$|KM,L/.N$d.etOt"sI$@I!F$!E$#HEt$#F&E-+E$-Et$,F$e|B/-B/.C$.C$5WD$.Gd$/tFI 0E-@D ,, G1uD(HD7D7tD6Cd$5WE$=|B/=B/0BB$3@$y ; ;AtA/|?3e?51515151253U$24$24$24^$24$23$23$23B$22U$8e4$2/U$2/$203$20z$20$21 $21P$21$21U$5..5..5..5..9;0$U 4$3$Ht4+|0g8$V$8V$8V$8]V$8V$8V$9t 9H:e 9998e0$5|&5&5&5&2*U$2*^$2*$2)$2)$2)A$2($2($2(lU$8e,$2+U$2, $2,P$2,$2,$2-%$2-l$2-$2-U$5*J5*J5*J5*J9t:H6$kH6$7$GH<%$898 97 @=@?4+$6 G$#H2I$2%k$2%$e43|0g1!39$19$1l9$19$8$87It"sBuBBB-NG@-N@-M>;|K*$)$s(% d$6,$7t#9;)$U8e)$H2%$2I$Bu2IB1,B0 |0g0g9t2 9+W +5G+5W.e4$-5+W-G+..-$.e.e=u -IKJG92O-+Wr G,s7I|9A$?!39$? y]$u,s2t!V 2 2 2, ) / .(H 8',$7l's$8's$?'O$B's$?*$B $;B$;Bd$ |%"$u(t+ |'<t,s|*J9t: 9K&$|GvJ$tK1/G1(HG#)$$e&$U#&z$#&z$y$e(V$&)$e'OV$&'s(Bf(@+|%J+#Bu+BH V$9VGG(BB9$(@H$8:{$8V$9t8OV$9s 8erG G#H4$#H|0gs(G,P$s/V$- $ /$$.$ #%$+uH$G$!$UH!zk$H!z$ydt#!"$d!V"$#$d$d$d$d$d$kd$$d$d$d$Od$d$d$yd$2d$Ad$]d$d$udH H$yHk$$UH G$t,Ar$#%r$e$d $!$!$d :$9$,$|ees$",z$ :u!Vk G$$dst$V$r2@$2$ k$$ 9HGB | l$+$H$!3 $+H$$$$d $ $r $ $u #| u  +$$@+ rt  "s =|>=>?WAm$?WD$"sI{$e$"sr =ud~9dAbXDorado Hardware ManualDisk Controller August 1, 198568Disk ControllerThis chapter describes the Dorado disk controller, which uses the Slow I/O system to control upto four Century Data Trident disk drives. Either the 80x106-byte T-80, 300x106-byte T-300 or the315x106-byte T-315 drives can be used. Keep Figure 13 in view while reading this chapter.The disk controller uses task 148 and the first five values of the TIOA addresses 108 - 148 . TheEthernet controller, on the same logic board, uses the other two 158 - 168. TIOA assignments are as follows:108DiskControlOutput_B to control register118DiskMuffOutput_B muffler control and Pd_Input to read muffler128DiskDataPd_Input to read FIFO or Output_B to write FIFO data138DiskRamOutput_B to format RAM148DiskTagOutput_B to tag register158EthDataPd_Input to read FIFO or Output_B to write FIFO data168EthCtrlOutput_B to control registerNote: other tasks must not select these TIOA addresses at any time; doing so may cause the disk controller tomalfunction.The controller is interfaced to the disk drives by a daisy chain cable bussed to all drives and by anindependent radial cable to each drive. The radial cables contain the following signals:data line (bidirectional, differentially driven)data clock (from drive, differentially driven)subsector/index line (from drive)selected line (from drive)select line (from controller)sequence line (from controller, controlled by the baseboard for drive 0 and groundedfor other drives)two VCC lines and scope trigger (from controller)The daisy-chain cable contains the following signals:16 control "tags" driven by the controller and received by the selected drive9 error and status signals from the drive as follows:CylOffset'ReadOnly'NoTerminatorHeadOvfl'SeekInc'DevCheck'NotOnLineNotReadyIndex' fpX" q0pG?f ar ^ep!> \5](s\p](s\p Z[]sZp!pW^qX2 SpS_S3S_SS_S QCQqQQqQ NF"yJJGsJp  yI H|sI p 5yG?FsG?p 4yEtDsEtp yCCsCp yAARsAp 4y@?s@p x=vts t$s7x< 8p2qp 6 q pAy30y2).y0_!y.y,y*-')4y'i1 $a5y!YMy5 / d:o  (% <QQ;)Q9 7QQ6(6 3Q%Q2 0_ Q  00_Q./D.Q--- *QQ){' 'FQ % $ #$ Q!Q bQQA t  &' ;Q : 90 7 Q6oQ5Q3Q2LAQ0A +EuX 'pX $aqpqp7 "G 3- qp:qp 7 T lS  0S eX  '>J2'= ';':x9 F/x7.x6/ 2pO 0L -V/0 +#< ) &O4- $)9 "H ] %%qp Z<% * ,7 Sqp' S S d ) , =Y)*Dorado Hardware ManualDisk Controller August 1, 198572Format RAM and Sequence PROMsThe format RAM is a 16-word by 12-bit register that holds commands and delay counts used bythe controller during a transfer. Words within the RAM are used according to the followingtable; the example values are appropriate for Alto Diablo disk emulation (2-word header, 8-wordlabel, and 256-word data record).ExampleAddrDescription Value00Word count of the first block000101Word count of the second block000702Word count of the third block037703Word count of the fourth block000004Control tag command for a read operation010405Control tag command for a write operation020406Control tag command to set Head Select000407Control tag command to zero the tag bus000008Word count to write zeroes before writing the 1st block of a sector003309Word count to write zeroes before writing the sucessive blocks000610Word count to wait before reading the 1st block of a sector001111Word count to wait before reading the sucessive blocks000212Word count of ECC words plus one000213Word count of 2000114Word count of 1 (minimum count)000015Not used0000There are two sequence PROMs, one for reading (or checking) and one for writing. The PROMsare addressed by a program counter that is initialized to zero at the beginning of a sector and isincremented upon completion of each PROM program action. Either the read PROM or thewrite PROM is selected according to the operation being performed on the current block.The sequence PROMs are clocked by WordClock, which is derived from the disk bit clock, whichin turn is derived from timing information pre-recorded on the disk pack. The subsector pulsesgenerated by the drive are also derived from this timing information. This enables very preciseplacement of the data on the disk, in a manner that is independent of the disk's rotational velocityor the Dorado's clock rate. fpX" q0pG?f bu ^p.- \3( [M YL!9VDtU 9F]Rs:_]QN:_]P:_]N:_]M(:_]LX):_]K&:_]I':_]HC:_]Gb>:_]F$;:_]D6:_]C:_]Bl:_]A.:_]?:_ :_]J+:_]H<:_]G+]FH+]E :_]C@t9? 9 ]=/s):_];&:_]:(:_]9w*:_89tD]6s:_]5 :_]4@:_]3C$:_]2<:_]0(:_]/*:_.MtD]-s:_]+ :_]*@:_])W$:_](<:_]&+]%+]$a:_]#$ uX pH #= = 0Q e"= >wp  \ d ;X <[Dorado Hardware ManualDisk Controller August 1, 198574Bits 4 through 15 of the tag register are interpreted according to the following table:Tag[0]Drive select and subsector countTag[4:15] are interpreted by the controller to effect drive select or subsectorcounter changes. The tag timing and wakeup circuit is not activated; firmwaremust take care of the timing by first loading Tag[4:15] as desired but withTag[0:3] equal 0, then or-ing in the Tag[0] bit and outputting again. 4:9Subsector countDivide the 117 subsector pulses from disk by subsector count+1 to form Sector pulses(Tag[4:5] are presently unimplemented).Tag[4:9] = 3 yields 29 sectors large enough for 256-word data blocksTag[4:9] = 6 yields 16 sectors large enough for 512-word data blocksTag[4:9] = 148 yields 9 sectors large enough for 1024-word data blocks 10Load subsector from Tag[4:9] for the drive selected prior to the execution of this taginstruction.11:15Drive selectThe basic controller handles up to 4 disk drives; additional units may beaccommodated by adding drive dependent logic on an additional board and connectingit in in place of drive 3. To allow this, the 5 bit drive select field is interpreted asfollows. 0 - 3select drive 0 to 3, respectively 4 - 368select drive 3378don't select any driveTag[1]Head TagLoads a register in the drive that selects the head to be used during subsequentread/write commands. A Tag wakeup occurs at completion (1.6 ms). 4:7Unused 8Off Cylindermay be activated during a read to attempt recovery of unreadable data.It causes cylinder positioning to be offset 80 micro-inches. 9Determines direction of offset if bit 8 is set.10:15Head numbervalues from 0 to 4 are valid for a T-80, 0 to 19 for a T-300. Thedrive will turn on "EndOfCylinder" (alias HeadOverflow) error if an invalid headaddress is issued.Tag[2]Cylinder TagCauses the drive to seek to the specified cylinder. A Tag wakeup occurs afterthe tag timing sequence has completed (1.6 ms), and the NotReady status bit israised until the seek has completed (3 to 55 ms depending on the seek distance). 4:15Cylinder number (0 to 814 for Trident disks presently in use). An illegal cylindernumber will cause DeviceCheck to be raised.Tag[3]Control TagA Tag wakeup occurs at command completion (1.6 ms) and upon completion ofthe last read/write operation in a sector. Generally, Control Tag commands areissued only by the controller itself (using tag commands from the format RAM)rather than by the microcode; Device Check Reset and ReZero are anexception. fpX" q0pG?f bWx^\3[=YL:WETs~~S_F ~Q'~PD~O=D~M MOM8K~0ts~JG H~ ~F1~EQ<~CH~B@@~"s@?A>"s?A@== "s=x:Kp8=6=wp3s~1~6~0_<.*~ %+~0~*7~)4x%p $/"P%wp" 9s~:~c+xp J/wpqp >M% :X2]Dorado Hardware ManualDisk Controller August 1, 198575 4AltoLeaderspecial flag to the controller that allows disks written by an Alto TriconController to be read. This bit should only be used for the Alto Trident simulation. 5Unused 6Strobe Latecauses data recovery circuits within the drive to sample data early withinthe data bit time (for recovery when the drive is experiencing excessive read errors). 7Strobe Earlylike StrobeLate except in the obvious way. 8Writeturns on the write circuits. 9Readturns on the read circuits. 10Unused 11Reset Head registerzeroes the head address register in the drive. 12Device Check Resetresets all latched error conditions in the drive. 13Head Selectturns on the head selection circuits, in conjunction with a Read orWrite. 14ReZerorepositions the heads to cylinder 0 (if the heads are loaded) and resets thehead address register; resets SeekIncomplete and DeviceCheck error conditions. 15Head Advanceincrements the head address register in the drive.FIFO RegisterData to/from the disk is buffered through a 16-word FIFO (25 ms of buffer), which isread/written with Pd_Input/Output_B when TIOA selects DiskData. Each FIFO word holds 16data bits, 2 parity bits, and a 2-bit field indicating that the next word to be read is either write,read, or read-and-check type data. During output to the disk, the controller checks parity bothwhen receiving data on the io bus and again when reading the FIFO. During a disk read, parityis computed before writing into the FIFO, is passed through the FIFO, and is then written on theio bus for the processor to test.Muffler InputDorado uses a multiplexor scheme called the muffler system for reading miscellaneous logicsignals during debugging from the Alto or baseboard. The disk controller also allows a muffleraddress to be specified on an Output to the DiskMuff register; in this way, any DskEth boardsignal available through the multiplexors (mufflers) is also available for firmware sampling. Otherbits of the DiskMuff register output specify other operations as follows:B[0]Simulate read data of 1 for 1 cycle (for use by diagnostic programs)B[1]Simulate read clock of 1 for 1 cycle (for use by diagnostic programs)B[2]Clear CompareErrdone by disk task if a read&compare is found to be OKB[3]Set ReadDataErrdone by disk task to inhibit future writesB[4]Clear the index wakeup flip-flopB[5]Clear the sector wakeup flip-flopB[6]Clear the tag wakeup flip-flopB[7]Clear all error flip-flops within the controller (not the disk drive)B[8:15]Muffler addresssignals are enumerated belowFollowing an output to the DiskMuff register, the firmware must wait one cycle before inputtingthe selected muffler signal with Pd_Input. The state of the signal selected will be driven onIOB[15], and the remaining bits will be zero. For the purpose of examination from Midas, thesignals are grouped into 16-bit words, as shown in the following table. The bits within each wordand an appropriate explanation follow: fpX" q0pG?fbAs~'~`'.^~\w~?~[(.X~1V~ Ty~ RE~P~BM~>K~H~JGH~2~FND}~; @[uX  (U &O %<( #GIx s FExk Fx. Fx :x xu !x8 x Ex , np#< [ Y 6, D& <\cDorado Hardware ManualDisk Controller August 1, 198576KSTATEvarious bits indicating the state of the controller 000TempSensesee "Dorado Debugging Interface" document 001IndexTWdisk task wakeup is due to an index pulse; index pulses occur once/diskrevolution (16.7 ms) and are used to synchronize the hardware subsector counterand the firmware sector counter. An index pulse also causes a SectorTW. 002SectorTWdisk task wakeup is due to a sector pulse. To maintain a reliable sector countin a race-free manner, the microcode must (a) check for SectorTW, and uponfinding it set increment the sector number and clear SectorTW; (b) check forIndexTW, and upon finding it set zero the sector number and clear bothIndexTW and SectorTW. 003TagTWdisk task wakeup is due to completion of a Head Tag, Cylinder Tag, or ControlTag command. This occurs 1.6 ms after issuing an Output to the DiskTagregister, and also upon completion of the last read/write transfer in a sector. 004RdFifoTWdisk task wakeup is due to presence of at least 3 words in the FIFO during anormal read or 1 word during a read-and-check. During a normal read, anInput that reduces the FIFO below 3 words will drop RdFifoTW in time for aBlock to take effect on the 5th cycle following the Input; this permits a 2-cycleloop (Input, Block). During a read-and-check, an Input that empties the FIFOwill drop RdFifoTW in time for a Block to take effect on the 3rd cyclefollowing the Input; this permits a 4-cycle loop (Input, no-op, no-op, Block). 005WrFifoTWdisk task wakeup is due to space for at least 4 words in the FIFO. An Outputthat reduces the free space below 4 words will drop WrFifoTW in time for aBlock to take effect on the 5th cycle following the Output; this permits a 2-cycleloop (Output, Block). WrFifoTW is enabled to occur by selectingTIOA[DiskData] when a write command is in progress; it is disabled byTIOA[DiskControl], which the microcode executes after outputting the last dataword of a block. One more WrFifoTW will occur after all data has actuallybeen sent to the disk. 006ReadDataData bit from the disk (available for diagnostics) 007WriteDataData bit to the disk (available for diagnostics) 010EnableRunFormat RAM has been written, and wakeups are enabled 011DebugModeController has been placed in debug mode 012RdOnlyBlock'The controller is processing a block in normal read mode 013WriteBlock'The controller is processing a block in write mode 014CheckBlock'The controller is processing a block in read and check mode 015ActiveThe controller is processing a command for the current sector016:017Select.0..1The address of the currently selected drive unitKSTATvarious bits indicating the status of the drive/controller. The controller will turnon WriteInhibit for the remainder of the sector after any of the following errorsare detected, but will still go through all the motions of word transfers. 020SeekIncThe disk drive has not correctly positioned the heads within the last 700 ms. AReZero command must be issued to clear this error. 021HeadOvflThe head address given to the disk drive is invalid (i.e., greater than 4 for a T-80 drive). 022DevCheckOne of the following errors occurred:Head select, Cylinder select, or Write command and disk not readyIllegal cylinder address.Offset active and cylinder select command.Read-Only and Write.Certain errors during writing, such as more than one head selected, notransitions of encoded data or heads more than 80 micro-inches off cylinder.A ReZero command may be necessary to clear this error. fpX" q0pG?fxb\3`Ss\&^\C]K0[$$ZC\*!X4W0V!"tTsS\> Qws P=Ni\2M3K< JG%,HMG)F$0D}\+C/AJ@[C D3>0=5<88:90\.7\,5\.4:\ 2\ 50\ //D\ 8-\:+\ 0x(p\),\&!0\%J"Ps\9 2H\0 @\" bA b~ b* b b\4 b.T6 1:'UDorado Hardware ManualDisk Controller August 1, 198577 023NotSelectedThe selected drive is in "off-line" test mode or the selected drive is not poweredup 024NotOnLineThe drive is in test mode or the heads are not loaded 025NotReadyThere is a cylinder seek in progress or the heads are not loaded 026SectorOvflThe controller detected that a command was active when the next sector pulseoccurred. This error implies either a hardware malfunction or a discrepancybetween the sector format of the drive and the word count the program thinks isappropriate. 027FifoUnderflowEither the FIFO became empty while writing (task got behind) or the FIFO hadtoo many words taken out of it while readng (microcode word count or wakeuperror). 030FifoOverflowEither the FIFO became full while reading (task got behind) or the FIFO hadtoo many words put into it during writing (microcode word count or wakeuperror). 031ReadDataErrA flip-flop in the controller for latching one of three errors:CompareErra read-and-check operation was executed on a block, and themicrocode did not issue ClearCompareErr before thebeginning of the next block.ECCErrorthe microcode can set the ReadDataErr flag if it determinesthat the ECC words after reading one block are non-zero inorder to inhibit future writes.ECCComputeErrThe ECC hardware within the disk controllerfailed to generate a single "1" bit (i.e., a hardwaremalfunction). 032ReadOnlyThe "Read-Only" switch on the drive is on. 033CylinderOffsetThe cylinder position is currently offset. This is a mode used for recovery ofbad data. 034IOBParityErrThe controller detected bad parity on the IOB bus. 035FifoParityErrThe controller detected bad parity on the data out of the FIFO. 036WriteErrOR of errors on muffler addresses 020-035 037ReadErrOR of errors on muffler addresses 020-031 and 034-035KRAMcontents of the format RAM040:043Address of format RAM word044:057contents of format RAM wordKTAGcontents of the tag register060:07720 bit value last loaded into the tag registerKFIFOstate of the io control logic 100ShiftInThe controller is currently shifting data into the FIFO 101ShiftOutThe controller is currently shifting data out of the FIFO 102ComputeECCThe controller is currently shifting data and computing the ECC checksum 103NextBlockOccurs between blocks within a sector 104LoadTagIndicates that the next word read from the format RAM should be loaded intothe tag register as opposed to the count register 105CntDone'Indicates that the count register is again zero, and a new value from the formatRAM will be loaded next 106OutRegFullThe holding register on the input to the FIFO has been loaded, but nottransferred into the FIFO. fpX" q0pG?fbAs\ :`_9\2]\;[\ #&Z/Y)&)W V!\ FT =S_Q\ 5PW? NMO\ > bK (7(JGJ K%(H bG?(&(E2(D} bB .(Au%&,(@ >m\'<\ C;e9\ /8\ <6o\'4\3x1yp\.s\-\x)p\'s\.x#p\ s\s4\s6\ s&\s\s6 1\s'Bw\ s* 8W;Dorado Hardware ManualDisk Controller August 1, 198578 107InRegFullThe holding register out of the FIFO has been loaded, but not read viaPd_Input or loaded into the output shift register.110:113FifoWaddrThe 4-bit address indicating where the next word will be written into the FIFO114:117FifoRaddrThe 4-bit address indicating where the next word will be read from the FIFO.if FifoWaddr equals FifoRaddr then the FIFO is defined as empty.Error Detection and CorrectionTo allow high data density and a few surface imperfections during manufacture, Trident diskpacks are not required to be perfect. A disk pack is defined as suitable when no more than threebad areas occur on any data surface; a bad area is defined as one which could potentially causeread errors of no more than 11 bits in length. To correct errors arising from these imperfectionsas well as other (infrequent) read errors, the controller implements an error detection andcorrection scheme which will detect (with very high probability) errors of any length, and willallow correction of any burst error of 11 bits or less.Error correction is accomplished through a mixture of disk controller hardware (for ECCgeneration and checking) and system software/firmware (for error recovery). This is acompromise between capability, speed, and cost. fpX" q0pG?fbs\s.`2^\s+#\\s8[]@ W;uX Sp= Q2/ P4P Ni#? LG JJ I 7 E*- D7##$3 B1 " Bk<%Figure 14Display ControllerD1Display.sil18Fout>>T0T1ROdd1616REvenFIFO256 x 32RAM>>T1pAReaderPtrBReaderPtrAWriterPtrBWriterPtrFIFO is written during FH andis read during the SH; readsalternate between channelA and channel B (irrespectiveof whether or not the channelwants the FIFO).>>>>7ACanReadFIFOAWritingFIFO>>1HWindowChannelOnChannelOffCursor video1st FIFORead2nd FIFORead<><><><><>32LeftMargin15><>16CursorX><18128 words ofFIFO used by A,128 by B.NLCB16 x 12RAM12CLCB<>RAMHRamHRamAddrHRamOut1024 x 33>>32FIB>>32SIB32>SR8A or B channel timing (in pixel clocks, not to scale)3>10Permuter>32>8SR>32SIB32>FIBT0DblCursorDataAItem.0AItem.1AItem.3BItem.0AOnBOndcAItem.2PolarityMiniMixer256 x 4 RAM48>4AItem[4:7]8dcCursorDataAItem.0BItem.0PolarityefcddcVBlankHBlankdc1AltoVideoPClkPClkVariousregisters>of NLCB and CLCB registersNLCBAddr412ItemClk'sPClk/2hg18IOBp16RIOBRIOBT3See Figure 15 for layoutHorizontal Blanking<>Visibleleft margin8/30/81RIOB>>RIOBMiniMix7-WireInterfacepTo TerminalHSyncHBlankVSyncVBlank6VCWSyncGenerator3pVisible data>Visibleright margin>>>>>>>Video$r !d<u 6$3$ 2$ 2$ -$y -$-$U 1 $4$ 4;$ Gt5W4 |0/$G/^+$ + u6 1,4 +$t4d4;$5W.$0/+6 $-$V+-$+-$y/^ +$p2t0/|+0u6,9|0 V(% $ t(H V& $ & V%^ $ % V# $ $ V#H$V&3$%$-,s+W*:)(:|$u:#:!: Jt& , $+,, * $+* V)$V+z$+z$]:|(X:&+$st,,V` (])[>\?[_F$2ZJ$UHZ$V3e\ :Z$U,a`g^.$9$e^.$9"sa#`g*^.$|b :b*_Jtb[/+[/H[/[/HW1W rt^u^+$ ^r$^u H^+$^G$!^u^$"s^$#H|[/[/$e^9$(H^9$)e[/$e[/3t^u*^$*|[/?[/6,tZeZH[C$#[C$2[C$7[CU$9|W2W&t^u,s +W*: -$ )$ )$ F$dBf$ BB$ BB$ pEt tC BdD$DX$EtdpEt `9$|\+\`$ t: 9$ 9$d9$ p< @$d?$ >$ >$ t?Wd<%U$=B$d;t$;P$;P$H; ;-;$9<d;+$ >^$ r|8.8ue1s$t2+3$.0$+0z2$+0z$2,1s |..1s...1$20z$220z2$50$23$/t20W1s$3e1s71s$6t29;3$$pXX5;t$t<?$ r| 8C$@t<$981s=-A& $-? $->^ $-< $AAp@-#H?$e?$%?W%= $A$$XSyncEnableFakePixelClockUseFake------DWTShutupDHTShutupNLCBAddr[0:3]<>NLCB data<>KeepHRam'WriteHRam'LoadHRamAddr------------------------>Data[0:7]><--------<>KeepMixer'WriteMixer'LoadMixerAddr--<>--><--AddrLoadWriteKeep1514131211109876543210--------Address[0:7] OR Data[0:7]<>377 (Y)367 (M)DDC**Addr[1:10]375 (Y)HRam374 (Y)373 (Y)DWTFlag*8/29/81372 (Y)MiniMixer360 (M)PixelClk361 (M)Mixer362 (M)CMap365 (M)BMapRed[4:7]Blue[0:7]<>Green[0:7]Red[0:3]<<>>01370 (Y)----1514131211109876543210MapInLo1>><TIOAOutputTIOAInput376 (Y)366 (M)364 (M)363 (M)361 (M)360 (M)TIOAInputNoPEData*Data** Parallel registers DispY/DispM0VCW*VBlankVSyncOddFld111BMargin10--AMargin*Left margin count (negative)<>2AWidth*12BWidthWidth count (negative)<>3AFifoAddr*13BFifoAddrFifo Address (even)<>414BScanPolarity*ResolutionSize8Size4Size2Size15MixerMode24BitBBypassA8B215Cursor position (negative)<>CursorX*6--16CursorLo*7--17CursorHi*Cursor data [8:15]Cursor data [0:7]<<>>TerminalTerminalMufflerMultiplierDivisor<<** Only starred bits or fields are usedon DispM; all others are ignoredStatics**NLCB**Status**MapInHi**AScan**DHTFlag**WCB*0*Map'Map'Map#r V9Cu =Lf$Lf$J-tKJFIKJBfKJ>KJ:KJ6KJ3KJ/:KJ+WKJ'sKJ#KJKJKJKJKJKJHLf$DLf$ALf$9;Lf$1sLf$-Lf$)Lf$!Lf$Lf$VLf$5WLf$%Lf$:Lf$rL$]rL>^$LL$9r^ >;$re>;$L`$rr`>^$ra$:` $d%` $d5W` $dV` $d` $d!` $d)` $d-` $d9;` $dA` $d_J_J_J_J_J#_J's_J*_J/:_J3_J6_J:_J>_JBf_JFI_JJ-_J` $d=` $drJ>;$LG$rF>^$rF$:F$%F$5WF$VF$F$!F$)F$-F$1sF$9;F$AF$DF$HF$EEEEE#E'sE+WE/:E3E6E:E>EBfEFIEJ-E=F$=@$@$J-?FI?Bf?>?:?6?3?/:?+W?'s?#??????H@$D@$A@$9;@$1s@$-@$)@$!@$@$V@$5W@$%@$:@$rA&$rA&>^$LAI$rE >;$r>>;$L;-$r; >^$r; $::$%:$5W:$V:$:$!:$):$-:$1s:$9;:$A:$D:$H:$99999#9's9+W9/:93969:9>9Bf9FI9J-9:$=:$=4$4$J-3FI3Bf3>3:36333/:3+W3's3#333333H4$D4$A4$9;4$1s4$-4$)4$!4$4$V4$5W4$%4$:4$r4$r4>^$L5$r8>;$r>;$L$Urz>^$rz$y:$%$5W$V$$!$)$-$1s$9;$A$D$H$:::::#:'s:+W:/::3:6:::>:Bf:FI:J-:$=$= $ $J-eFIeBfe>e:e6e3e/:e+We'se#eeeeeeH $D $A $9; $1s $- $) $! $ $V $5W $% $: $r $yr >^$L!$Ur$A>;$r,>;$L&$r&z>^$r&z$@:&$%&$5W&$V&$&$!&$1s&$9;&$A&$D&$H&$%:%:%:%:%:#%:'s%:+W%:/:%:3%:6%::%:>%:Bf%:FI%:J-%:=&$bVb Vc r$$c $V|_Z,s_Z.tc..b2c2b2a5d5cu:WbX>;bXBbXFcEtbIdIcu\ r\+$\U$r|Y>Y>2t\ \H$8\$|Y>KY>G$H.$tIXH;+IX+H;IHGf:HeIXeGf#HGf',Gf*Gf.Gf2Gf6Gf:Gf>Gf#HIX%I+$9I$K|F%FAItGfE-GfIGfBBBBeB#HB',B*B.B2B6B:B>BBfCABAAFCEBICJ-B<<<<e<#H<',<+<.<2<6<9=9<==><>;tBf;tB<A=Et=F<FI;tI=I;td6t r6 $!6 $r|3.,s3.:Wt6t -6 $?6 $K|3.-3.t",",",",|<&$*.$Ht)H(+)+(V*V)eV(H)e|&K&t+!+z$9;+z$G|'!'2t+ I+IX+e#H',+.26:>BfFI5bX5a<D` $dH` $dIXbX1s` $dH<="$G"$K|=t0W/:1s00=.e$J--FI-Bf->-:-6-3-/:-+W-'s-#------H.e$D.e$A.e$9;.e$1s.e$-.e$).e$!.e$.e$V.e$5W.e$%.e$:.e$r.$r.>^$L.$r2>;$.e$e0W#0W's0W+0W70W-0$D0$-|-K-pdbXIta<Fpa<4;tIX pH;H;C=<Dup55 !!((/:/:00$t)e7)e )$()r$-) $<)$-|&-&(.$)t', C;',' $/:' $='$G'$|#=#<#K#)&$-&$Mt)eM',L+z$M*$pt  =$$J-FIBf>:63/:+W's#H$D$A$9;$1s$-$)$!$$V$5W$%$:$r $yr >^$L +$Ur ]>;$pt GK|<=G $= $/: $ $C;t G) G r>;$L$Ur>^$r$y%+$5W+$+$!+$)+$-+$1s+$9;+$A+$D+$H+$ V V V V V# V's V+W V/: V3 V6 V: V> VBf VFI VJ- V+$=+$-| - <A$-A $(Ar$A$7t $K|  tV rA$A$r| s pffUSXB;t  t+ G MGMGL$9r[>;$ZZAZEtZHZrZ&>;$X:XsX:ZsZrX|>;$X-XYQr$:YQ$|UKUtW<W<:W<sW<-W<rV>;$WH$8eWH$|SKStUU :UsU 7IU-UV$@tU 9$-U +$-|RLKRLrU&>;$tS:SsS1S 7S =SASESIXSrS|>;$R<R< =R<E-R<IR<rQ>;$:P-PPH$9P+$|MKKMKrP&>;$stPNN:NsN rN{>;$M;M;:M;sM; 8N8M;|KIKKKI=S$AS$DS$HS$5WS$1sS$-S$tH :+$V+$IH+", C;"," 9$/" V$-|K-I-OQ $-M $AOQ $AM $t'9 pb 9S tSpB EtAJtA//0WN{f`sDorado Hardware ManualDisplay ControllerAugust 1, 198579Display ControllerThe Dorado Display Controller (DDC) uses the fast I/O system to obtain representations of videoimages from storage; it then transforms these representations into control signals for monitors. Itsthree design objectives are:(1) To handle a variety of color, grey-level, and binary (black-and-white) monitors;(2) To utilize the full power of the fast io system in producing high-bandwidth computergraphics;(3) To allow various compromises in color and resolution for experimental purposes.Clock rates, video signals, and other monitor waveforms should be controllable bymicrocode.There are two independent video channels capable of running in a variety of modes. Twochannels allow text to be displayed on one channel, graphics on another, or the main picture onone, cursor on the other.The DDC must LF (large format) monitors which are standard for most systems. Bit maps,display control blocks, and monitor control blocks, similar to those used on the Alto, provide thesoftware interface to the DDC. The "seven-wire" video interface makes provision for one or morelow bandwidth input devices (keyboard, pointing device, etc.); our current provisions for keyboardand mouse input are also discussed in this chapter.Keep Figure 14 in view while reading this chapter.Operational OverviewVideo scan lines are encoded in bitmaps, which are contiguous blocks of virtual memory; the twochannels, A and B, have independent bitmaps and data paths in the DDC. The high-priorityDWT (Display Word Task) runs on behalf of either A or B using the subtask mechanism; ittransmits each bitmap to a FIFO consisting of 15 munches/channel. The bitmap stream emergingfrom the FIFO is then sorted into items (1, 2, 4, or 8 bits wide) for each channel which arecombined, mapped, and transformed into pixels (picture cells) on the screen.In addition to the two channels, the DDC supports a programmable cursor that is 16 pixels x 1bit/pixel wide.A lower priority DHT (Display Horizontal Task) handles horizontal and vertical retrace and setsup starting addresses and munch counts, cursor data, and formatting information in the NLCB(Next Line Control Block) for the DDC. The NLCB is then copied into the CLCB (Current LineControl Block) during horizontal retrace prior to the next scan line.The rate-of-flow of items is governed by the resolution and pixel clock period. Resolution may beindependently programmed for each channel so that items flow at 1/4, 1/2, or 1 times the pixelclock period. If the DispM board is present, then the pixel clock period is also progammable;otherwise, it is determined by a crystal oscillator on the DispY board, which must have afrequency appropriate for the monitor being driven. The current crystal used is 50 mhz for the LFdisplay. fp" q3fpG?f ar ^ep^^e^^e^^e. \B# ZyW^=yU8ySyQ?yP42yNi J qp > I-I Gb CP B%+7 @[00 > U <3t9TqX2 4:s 0pqp - .Y -3qp> +iB ) qp5 ''qp $aG " %qp- ZRq p!(qp E S(q pqp 7' != Y )D ^ S <J :+ 5s 1q .*pH ,_+t,_p +t,_p, *7*t*p*t*p (L '` %5 A %\ Z 30 )4 S,5 F ! L.3 :' D  p=\IDorado Hardware ManualDisplay ControllerAugust 1, 198581munch for the previous scan line, or at the beginning of the first munch for the current scan line;the read pointer has to be reinitialized to skip over these. FIFO reads alternate between channelsA and B, so the data rate for one channel is limited to 32 bits/2 cycles (=16 bits/cycle).Item FormationAt the output end of the FIFO there is a multiplexor shared by both channels and, for eachchannel, two intermediate buffers (FIB and SIB), and a shift register SR. The multiplexorpermutes the 32-bit quantity emerging from the FIFO so that when the double-word has marchedthrough FIB and SIB and is finally loaded into SR, successive shifts will produce successive itemsof the selected size (8, 4, 2, or 1 bits).The SR is tapped as follows:SR.0Item[0] for item sizes 1, 2, 4, or 8;SR.16Item[1] for sizes 2, 4, or 8, gated to 0 for size 1;SR.8, SR.24Item[2:3] for sizes 4 or 8, gated to 0 for sizes 1 or 2;SR.4, SR.12, SR.20, SR.28Item[4:7] for size 8, gated to 0 for sizes 1, 2, or 4.All eight Item bits are gated to 0 if the channel is off. It is useful to think at this point that,regardless of a channel's item size, an 8-bit wide item is produced, whose bits contain non-zerodata only in those positions dictated by the item size; i.e., for size 1 only the most significant bitmay be non-zero; size 2 allows data in the topmost two bits, etc.The SR loads on the item clock after its last item has been used; the item clock rate is the pixelclock rate divided by the resolution (1, 2, or 4 for full, half, or quarter, respectively). Hence, for8, 4, 2, or 1-bit items, SR will be shifted 3, 7, 15, or 31 times, repectively, and be reloaded fromSIB on the following item clock.The 8-bit items from the two channels are then presented to either the Mixer section on theDispM board or the MiniMixer or LF video interface on the DispY board.MixerNote: A8B2 means A Channel 8 bits and B Channel 2 bits.A6B4 means A Channel 6 bits and B Channel 4 bits.The Mixer is controlled by the A8B2, BBypass, and 24Bit mode controls. It is a 1024-word x 24-bit RAM for which the 10 bits of address required may be obtained from two possible sourcedistributions, depending upon the A8B2 mode. When A8B2 is true, the address consists ofAItem[0:7] and BItem[0:1]; when false (called A6B4), the address is AItem[0:5] and BItem[0:3].Another mode, the BBypass mode, can be enabled independently for the B channel. If B isbypassed, none of its bits contribute to the Mixer address. Instead, they bypass the mixer andaddress a 256 x 8 RAM, the BMap, whose outputs are ORed with the mixer outputs for the blueDAC. For example, with ASize=8, BSize=4, BBypass true, and A8B2 true, and with appropriatevalues in the Mixer RAM, the controller may be thought of as three 4/bits pixel channels drivingthree color guns. One channel is bypassed data from B, while the other two are mapped throughthe Mixer. fp" q3fpG?f b+8 `Sc ^A ZCq Vp= U#qpqpqp S<.. Qq=% O* L5yH"s%yF"s4yE- "s/yCc"s- ?); >&2. <\V :A 7q p2 5U ] 3L 1 .MB ,F (=q $p+$t$!/$t$ )+$t$1$t$ # "#"# $"#,"# kqpqpqp I ,,  P D <# A :[ oD L  | <\xlDorado Hardware ManualDisplay ControllerAugust 1, 19858224Bit mode, used in conjunction with BBypass mode, is used to run a three-channel color displaydirectly from memory. In this mode, items from the A channel alternately address the Mixer(called the AMap in this mode) and another 256 x 8 RAM called the CMap. Meanwhile, the Bchannel runs at half the A channel rate and addresses the BMap as described above. (That is, theB channel must be set to one-half the resolution of the A channel.) With suitable values in thecolor maps, the AMap, BMap, and CMap independently generate outputs for the red, blue, andgreen DACs respectively.After routing as dictated by the mixer modes, chosen items are loaded into the map addressregisters, causing the color maps to produce a new video value every pixel clock (every two pixelclocks in 24Bit mode), and these values are latched in the three 8-bit mixer output registers.Three very fast DAC modules then produce a Red-Green-Blue triple of analog signals for a colormonitor, or up to three grey-level video signals. In conjunction with the sync, blank, andcomposite waveforms produced by the monitor control circuitry, these signals can drive a widevariety of monitors attached to the Dorado.Alto Video InterfaceA small circuit on the DispY board produces video for an Alto monitor. This circuit ORsCursorData, AItem[0], and BItem[0], then XORs by the polarity, and finally ORs with the verticaland horizontal blanking signals.This interface was originally designed and used for the small Alto type of display on the firstDorados. There is a ECO out to wire the LF display data from the MiniMixer to the old Altodata because of a slow path in the MiniMixer.Date: Tue, 2 Jul 85 11:01 PDTFrom: Vest.PASubject: DispY ECOTo: DoradoCore^.paReply-To: Vest.PAThere is a problem with the DispY board when running a black and white display only. The MiniMixer on page 20 of the DispY board will sometimes pick bits when the Dorado is first turnedon. It usually goes away in a couple of minutes, but not always.The problem is best seen when running the CRT test from the net with the alternate pixel on andoff pattern. If you cool the MB 7071 chip at location f04 the display will usually go fuzzy andsometimes completly black.Here is the change:Cut and lift C05.6Add wire from C05.6 to e03.15Remove MB 7071 chip at location f04.Mark the board Revision DDMiniMixer fp" q3fpG?f bD `S= ^0) \I ZK Y)P W^ SZ R".3 PWH N^ L[ JV I-+ Dq @p1' >>" =  9w*5 7'3 5- 2L 0 . , +" '] %\ #@ b2- J  8111 $ x q d =]oDorado Hardware ManualDisplay ControllerAugust 1, 198583A small video mixer on the DispY board, not to be confused with the large Mixer on the DispMboard, can drive either a DAC or the seven-wire interface discussed later. The MiniMixer is a 256word x 4-bit RAM addressed by a combination of AItem, BItem, and state bits, as shown inFigure 14. On every pixel clock, dDAC[0:3] are loaded from MiniMixer output, while dDAC[4:7]are loaded directly from AItem[4:7]. The MiniMixer aims at experiments with mixing channelsand driving grey level monitors.Horizontal and Vertical ControlEvery monitor requires horizontal synchronizing and blanking waveforms. Interlaced monitorsmust be able to distinguish fractions of a scan line to implement interlacing. In general, theduration and phasing of sync/blank waveforms is unique to a given monitor. The DDC uses the1024-word x 3-bit HRam (Horizontal RAM) to control horizontal sync/blank.The DDC has a set of registers called the CLCB (Current Line Control Block) which controlsvideo generation for the current scan line. The DHT sets up parameters for the next scan line inNLCB (Next Line Control Block), a 16-word x 12-bit RAM. The first 32 pixel clocks ofhorizontal blanking are called the HWindow; during HWindow parameters for the next line arecopied from NLCB into CLCB. Vertical control is also handled through the NLCB.The interpretation of fields in NLCB and HRam are shown in Figure 15 and loading will bediscussed in the "Slow IO Interface" section; the use of the different information is discussed here.The top part of Figure 14 shows how horizontal timing is controlled.Line Control BlocksThe fields in NLCB/CLCB are interpreted as follows, where a denotes that the item is channel-specific (i.e., copies exist for both A and B channels):aPolarity. A single bit, used only for binary monitors, that inverts black and white(APolarity and BPolarity are or'ed by the hardware).aResolution. A 2-bit field that controls item clock generation; values of 0, 2, and 3cause quarter, half, and full resolution, respectively.aItemSize. A 4-bit field unary encoded as aSize1, aSize2, aSize4, or aSize8, denotingbits/pixel for the channel; setting multiple bits is illegal.aLeftMargin. A 12-bit field in units of pixel clocks specifying 31 less than the numberof pixel clocks to wait after HWindow completes before turning the channel on. Thisvalue is not a straightforward constant, but depends upon monitor-specific horizontalblanking time. If the horizontal blanking time is B pixel clocks and the desiredbeginning of data is L pixel clocks after the end of horizontal blanking, thenaLeftMargin should be loaded with B+L3231 = B+L63, independent ofresolution. Since L may be 0, this implies that the horizontal blanking time for themonitor must be greater than 63 pixel clocks. Since high-speed monitors typically havegreater than 4 ms horizontal blanking times, and are this fast only with high speed pixelclocks, this restriction is not expected to be significant. fp" q3fpG?f b+1 `S\ ^F \ S ZG Y) Ts Pp O N_ M": K>qp3 G#qp, F<% D7qp%, Bl"qp1 @O =/P ;e50 9D 5Uq 1p:up 08y,O,uj,O,p Ay*4y''iuj'g'ip #(y%7y!"-uj!("-p"upupupupy b=yujp 3y&%/y[,)yQy#+yup/y1Myf4#yup.y ; =[lDorado Hardware ManualDisplay ControllerAugust 1, 198584Note: For a monitor connected via the 7-wire interface, aLeftMargin must be B+L68, ratherthan B+L63, because video signals are delayed from horizontal control waveforms by 5 pixelclocks.Note: The value loaded into aLeftMargin must actually be the negative of the left margin countcomputed above.aWidth. A 12-bit counter that counts at the pixel clock rate as soon as the channel turnson; when the counter runs out (or when horizontal retrace starts, whichever is earliest),the channel is turned off. Precisely, if the channel is to run for W pixel clocks, the widthcounter must be loaded with (W+255).aFifoAddr. An 8-bit quantity pointing to the munch and word within the munch for thefirst FIFO read for the next scan line; this must be an even number becausedoublewords are fetched from the FIFO. Firmware must keep track of the number ofused munches for any given line and advance aFifoAddr by exactly the right amount,adjusting for munch boundaries, interlacing, and data breakage. The CLCB register foraFifoAddr is the channel read pointer itself.MixerModes. A set of bits that control the mixer; these are not channel-specific. Thesewill normally be changed infrequently, maybe at the field rate or during displayinitialization. However, they are in the NLCB to allow modes to change on the fly.Vertical Control Word (VCW). A word controlling the vertical retrace operation of themonitor; it contains the vertical blank bit, vertical sync bit, and interlace field bitdiscussed in the "Vertical Waveform Generator" section below.Cursor and CursorX. The 12-bit CursorX value is loaded into a counter which startscounting at the end of HWindow. When the counter runs out, the 16-bit Cursor value isshifted out onto the CursorVideo line. This is used by the Alto video interface and inthe MiniMixer address. Precisely, if horizontal blanking is B pixels in duration, and theleftmost bit of the cursor is to appear X pixels beyond the end of horizontal blanking,then the CursorX register must be loaded with (B+X+226), or (B+X+221) whenusing the 7-wire interface.Horizontal Waveform GeneratorThe 1024-word x 3-bit HRam contains control information for these waveforms. Under normaloperation, HRam is addressed by a 12-bit counter (HRamAddr[0:11]) which is reset at the leadingedge of horizontal sync and then increments every pixel clock until the next leading edge ofhorizontal sync; HRamAddr[1:10] address the RAM, and the output is loaded into the HRamOutregister every other pixel clock. The three bits in HRamOut control horizontal sync, horizontalblank, and half-line; these three bits are combined and level shifted by a logic networkappropriate for the monitor being driven.The 1024-word HRam imposes the uninteresting restriction that there be fewer than 2048 pixels/scan line.As shown in the diagram at the top of Figure 14, horizontal blanking (HBlank) is true from theend of one scan line to the beginning of the next. During horizontal blanking, HSync is turnedon to initiate the horizontal retrace and turned off again when horizontal retrace is finished.HBlank then continues for a monitor-specific interval. Note that if a channel's visible left margin fp" q3fpG?f;bvtut!;` O;_9;\wvtutvt ;ZyWNWujWNWpPyUYyT;"yRE%yN|NujN|Np.yM4yK>QyIs,upyG5!yEup,yBBl (qpy@9y>G y;;e4y9Sy7=y4 4^:y2Cy0Ty.Ey-3 Ky+i.y) %Xq !p#7 _ Q1+ 8" D  N ')yetF" p S LY )6 ] p=\pDorado Hardware ManualDisplay ControllerAugust 1, 198585is non-zero, then the horizontal scan will begin before that channel is producing any data; in thiscase, the video channel outputs zero items to the mixing stages until the channel is turned on.Due to an implementation error, when the 7-wire interface is being driven from DispY, the value ofHBlank[i] may differ from HBlank[i1] only when i is even, where i is HRamAddr[1:10].Vertical Waveform GeneratorOnly 2:1 interlaced monitors are supported in this design, but more complicated vertical controlcould be provided, if desired. To support 2:1 interlace, HRam contains a waveform calledHalfLine, which is a pulse at the horizontal line frequency, 180o out of phase with HSync.Vertical control is handled by DHT through the NVCW word in the NLCB, which specifieswhether or not vertical blank or retrace should begin or end during the next scan line. The DHTmicrocode must keep track of scan lines to enable vertical signals at the appropriate times.The three VCW bits are called VBlank, VSync, and OddField. VSync enables vertical sync tobegin on the next line, and the OddField bit chooses either HSync or HalfLine on which to dovertical syncing (OddField=1 implies HalfLine phasing for vertical sync). This phase willalternate from the start of the line to the middle of the line and back for successive fields. Theblanking signal for the monitor is VBlank ORed with HBlank.Pixel Clock SystemThe programmable pixel clock on the DispM board, if present, determines the fundamental videodata rate for a given monitor. The pixel clock is controlled by loading the PixelClk register viathe slow I/O system. Seven-Wire Video InterfaceSo that a number of different controller and terminal types may be freely interconnected inDolphin and Dorado-based systems, a common interface between terminals and controllers hasbeen defined. This interface assumes that a terminal contains a raster-scanned bitmap display andone or more low bandwidth input devices (keyboard, pointing device, etc.) The DDC transmitsdigital video and sync to the terminal over six pairs of a seven-pair cable. The input data isencoded by a microcomputer in the terminal and sent back serially over the seventh pair (the"back channel"). Video and control (sync) are time-multiplexed, and four bits are transmitted inparallel to reduce the cable bandwidth required.While the description in the following sections assumes a display having one bit/pixel, the basicsignalling mechanism may be extended to support gray-level or color displays.Video OutputThe four output lines are interpreted as either a 4-bit nibble of video or four control signalsaccording to the phases of the two clock signals; the DDC places data on the data lines at thefalling edge of ClkA, and the terminal samples this data on the rising edge of ClkA. If ClkB is 1at this time, the nibble is interpreted as four bits of video, else as sync and control information. fp" q3fpG?f b7, `S1.y]tBy\1vtvt vtvt Xq TpX RG P!QqP Mr"3 K8( II Fkqpqpqp! DA BU A K ?A; :'s 6p] 4H 3  .s *p> ( O ' T %5;! #jW !A a  0 E M q p_ LH I ] p=\ Dorado Hardware ManualDisplay ControllerAugust 1, 198586ClkA and ClkB are transmitted in quadrature so that the terminal can reconstitute a clock at thevideo bit rate.When a nibble is interpreted as control information, bit 2 is reserved for horizontal sync and bit 3for vertical sync, while 0:1 are undefined; different types of terminals may use 0:1 for anypurpose.A circuit on the DispY board drives the seven-wire interface from the MiniMixer/Alto data.MinMixer[0]/Alto data is serial-to-parallel converted into four-bit nibbles, which are held in aregister for transmission. Sync, blank, and clock phases are generated in accordance with theseven-wire interface specification.Back Channel (Keyboard data)Data from low bandwidth input devices (keyboards and mouse) at the terminal are transmittedserially over the back channel. Data are clocked by the terminal on the rising edge of thehorizontal blank pulse and are sampled by DHT during the subsequent scan line after HWindow.The terminal microcomputer perpetually cycles through all possible keys on the keyboard (as wellas mouse buttons and keyset paddles), detecting changes in state of the keys; the state of thekeyboard then exists in seven 16-bit words, and a back channel message is defined for each.Whenever one of these words changes value, it is sent to the Dorado in a message. Table 24: Terminal Microcomputer MessagesMessageTypeComments00BIllegalignored01BKeyboard word 0 (corresponds to Alto memory location 1077034B)02BKeyboard word 1 (Alto 177035B)03BKeyboard word 2 (Alto 177036B)04BKeyboard word 3 (Alto 177037B)05BMouse buttons and keyset (Alto 177033B)06B8-bit changes in X-coordinate (0:7 of the message body) and Y-coordinate (8:15 of themessage body), represented in excess-200B notation07BIllegalignored10BKeyboard word 4 (Star keyboards only; no Alto analogue)11BKeyboard word 5 (Star)12B16BIllegalignored17BBoot message. Actually, depressing the boot button jams the data to one continuously, ratherthan generating a valid terminal message. Furthermore, when the boot button is let up, theremay be as many as 8 bits of garbage following the last consecutive one bit; these must beignored by the firmware. The firmware should also ignore boot button pushes less than 10 msin duration, as these may be caused by noise or contact bounce. fp" q3fpG?f b\ `S \^ [J YL UA TV RE9% Pz# L5q Hp0+ FW E-M A` ?J >&D <\S8]wF)y5vy4^1Ut/>-+*+(`'&;%52#j!7 @DE~H2*?  =Qq Dorado Hardware ManualDisplay ControllerAugust 1, 198587Processor Task ManagementThis section outlines the implementation requirements of DHT and DWT and discusses thehardware associated with task wakeups and DWT subtask arbitration between the two channels.Since DHT must do a lot of processing, it runs at low priority and is awakened once/scan line atthe end of HWindow.DWT is a very high priority task which may run on behalf of either channel: channel A issubtask 0; channel B, subtask 2. Since it uses the subtask mechanism, DWT must always block atthe same instruction each iteration.DWT lowers its wakeup request at the onset of the DWTStart instruction, and the DDCremembers that DWT is in progress. No further DWT wakeups will be generated while the taskis running or is preempted by a higher priority task. Whenever DWT blocks, a counter isinitialized to a constant value N and counts once per Dorado cycle; when the counter runs out,DWT wakeups are allowed again. This counter has two purposes. First, within a munch loop itspaces out IOFetch references to the memory system by 8 or more cycles (depending upon N,which is adjustable through a hardware SIP component), so as not to clog the memory pipeline.Second, the decision to generate subsequent DWT wakeups is based upon the state of flags thatmay be altered by output commands; these commands take time to get from the processor to theDDC and alter the state. Other tasks may have the processor while these state changes take effect.After N cycles have elapsed, DWT will be woken whenever aWantsDWT is true for one of thechannels. Two channel-specific flags are involved in DWT wakeup control: aCurrentWCBFlag istrue when a is actively moving words into the FIFO; aNextWCBFlag is set true by DHT after ithas loaded the munch address and munch count into DWTnextaddr and DWTnextcount for a.After fetching the last munch for a scan line, DWT clears aCurrentWCBFlag and blocks unlessaNextWCBFlag is true. In other words, aWantsDWT whenIf only AWantsDWT or only BWantsDWT, no conflict arises and the requesting channel getsDWT. However, if both channels want DWT, the channel that ran least recently will run next.Note: Neither DWT nor DHT drives the IOAtten branch condition.Slow I/O InterfaceDDC manages all control functions via the slow I/O system. At this point you should studyFigure 15, which shows the format of the various output and input commands; there are sixoutput devices and one input device on the DispY board, and eight output devices and one inputdevice on the DispM board (if present). Output commands are handled uniformly: TIOA isclocked into a register at t1; the register output is decoded and identified as one of the DDCcommands; if the processor is doing an Output_B, then at t3 IOB data from the processor isclocked into a register and one of the "TIOA command" pulses occurs from t3 to t5, at whichpoint the desired action is complete.The IOB data received at t3 of an Output_B will remain in the DDC buffer register (RIOB) untilthe next output command. This is useful for debugging and for muffler readout of the NLCB(because an NLCB address can be loaded into RIOB for multiple cycles). fp" q3fpG?f bs ^p8 \-. YoM W T> RE U Pz$ L I KB IPK G<" E,1 CY B%@ @[/. >6& <.5 9T%up 7Iup 5 up"up' 37up 2):up 0_up&up ,> +"$8 'qp: "s %p!9 Z(1 &8 '1 mtp) 0:t0p e >teptep % ) t)pC ^U F | L=\\Dorado Hardware ManualDisplay ControllerAugust 1, 198588The HRam, MiniMixer, Mixer, BMap, and CMap are RAMs that will generally be loaded duringsystem initialization and not often changed while pictures are being displayed. The programmablepixel clock will also be loaded during initialization, if it is being used instead of the fixed crystaloscillator.The HRam, Mixer (AMap), BMap, and CMap addresses each have two independent sources: theDorado slow io system and the video system. Video system addressing is disabled during loadingfrom the Dorado. The output commands to each of these RAMs are interpreted as follows: TheKeep' bit is saved in a flipflop loaded by every RAM output command; as long as Keep' is true(i.e., low), video system addressing is off. If LoadAddr is true, then IOB[4:15] are loaded into theRAM address register. If Write' is true (i.e., low), the currently-addressed word of the RAM iswritten from the data field; additionally, the RAM address register increments after writing, so theRAM can be loaded sequentially at high speed. A RAM output command with Keep' false (i.e.,high) releases the RAM from Dorado control and returns it to the video system.The MiniMixer is loaded by a single output instruction that specifies both the address and data tobe loaded. During the command pulse from t3 to t5 of the Output_B instruction, the videochannel address to the MiniMixer is replaced by the address being loaded, so if the video channelis active, garbage may appear at the output during this cycle.The 16-word x 12-bit NLCB is also loaded by single output instructions that specify both theaddress and data. For the NLCB, output instructions are only effective when HWindow is notoccurringduring HWindow the RAM address is supplied by a counter that successively copiesthe NLCB words into CLCB. The format of each of the words in NLCB is shown in Figure 15.Note that any NLCB output operation will dismiss the wakeup request for DHT, and DHT mustnot block any sooner than the fourth instruction after the first NLCB output operation is issued.The Statics output command is used for debugging and initialization. Two bits in the Staticsregister called DHTShutUp and DWTShutUp. Three other fields called FakePClk, UseFakePClk,and MufAddr are used for debugging. When UseFakePClk is true, the regular pixel clock isdegated; if FakePClk is true, then a pixel clock will occur at t5 of the Statics output command;otherwise no clock occurs. Every Statics command also loads the hardware signal addressed byMufAddr into a flipflop (at t5) which can be read by the Status input command discussed below.In combination, the fake pixel clock and muffler readout features allow diagnostic firmware tocheckout most of the internal data paths in the DDCby simulating a very slow pixel clock and"stepping" the DDC through various states, the diagnostic can check nearly all of the data pathsbetween fake pixel clocks. The hardware signals selected by MufAddr[5:11] are given in the tablebelow. fp" q3fpG?f b*. `SH ^Y \ YL!6 WW U0, SO R"$A PW(8 N:* LT JN G*8 E)E.tEpE.tEp' C/2 B%> >\ <A ;tp*& 9T: 7; 5@! 2LC 05qpq p .qpN ,,,`t,p +"K )W(t)Wp? '@ %+tp) #` "-a b =G-Dorado Hardware ManualDisplay ControllerAugust 1, 198589Table 25: DDC Muffler SignalsMufAddrSignalMufAddrSignal 0ACurrentWCBFlag 70AFifoFull 01:07AReaderPtr[1:7] 71BFifoFull 10ANextWCBFlag 72ASize8 11:17AWriterPtr[1:7] 73ASize8-4 20BCurrentWCBFlag 74ASize8-4-2 21:27BReaderPtr[1:7] 75BSize8 30BNextWCBFlag 76BSize8-4 31:37BWriterPtr[1:7] 77BSize8-4-2 40:47AItem[0:7] 100AOn 50:57BItem[0:7] 101BOn 60:63AServicePtr[1:4]102:103ARes[0:1] 64:67BServicePtr[1:4]104:105BRes[0:1] 106MonitorTypeMuffler 106 (MonitorType) is the only one of interest during normal operation. It identifies thetype of monitor connected via the 7-wire interface: zero denotes an Alto-style monitor (not usedsince 1982); one denotes an LF (large format) monitor.A single input device called Status is implemented. It is used to return the currently selectedmuffler bit and the seven-wire interface received data bit.The MapInLo and MapInHi input devices read the current values output from the color maps(Mixer, BMap, and CMap, whichever are active). When the color maps are controlled by thevideo system, these outputs change too rapidly for reading them to be useful (unless the DDC isbeing single-stepped by means of UseFakePixelClk). However, when the color maps arecontrolled by the Dorado, this input device can be used to read out the color map entriesaddressed by their respective RAM address registers.MapInHi[0] is the 7-wire terminal input bit for the independent terminal interface on DispM; itsposition corresponds to Status[0] on DispY (see below). MapInHi[1] is a constant 1 if a DispMboard is installed; if DispM is not installed, an Input from the nonexistent register yields a zerovalue. This enables microcode to detect the presence or absence of a DispM board.MapInLo[0:3] are a 4-bit color monitor type jumpered on the Dorado backpanel.Note: the MapInLo and MapInHi input devices do not generate IOB parity, so they must be read by thePd_InputNoPE function to disable parity checking. fp" q3fpG?f KbsXy^q )W0y[:p )W0yYo )W0yW )W0yU )W0yT )W0 yRE )W0yPz )W0yN )W0 yL )W0yK )W0yIP )W0yG )W0)WE0 BI)8 @~G >6 ;A` 9w; 6M 4:!8 2pT 0!qp! .? -4 )U '7' & U $>&'> "sMyvtZyQ1  .=I&Dorado Hardware ManualDisplay ControllerAugust 1, 198590DispM Terminal InterfaceThe independent terminal interface on the DispM board functions much the same as a single-channel DispY board, but is specialized to driving a binary monitor via a 7-wire interface. Thedata path is one bit/pixel; the resolution is full; there is no MiniMixer; and the horizontalwaveforms are fixed by a PRom (which must be changed when a different type of 7-wire terminalis installed).Aside from these limitations, the DispM terminal interface operates almost identically to the Achannel of DispY. In particular, the I/O addresses are grouped parallel to the ones on DispY,and the data formats are identical; so a microprogram can initialize TIOA to the correct group andsubsequently use the function that changes only TIOA[5:7] to select registers within that group.This enables practically all the microcode for driving a 7-wire terminal to be shared betweenDispY and DispM.In Figure 15, the DispY io operations that are also defined for DispM are marked with anasterisk. Note that outputs to unused NLCB addresses are ignored.Note: DispM does not have a muffler system. In particular, the MonitorType muffler value is always readfrom DispY. By convention, this refers to the type of 7-wire terminal attached to the Dorado, whether thatterminal is connected to DispY or to DispM. Also by convention, the 7-wire terminal is always connectedto DispM if DispM is installed. fp" q3fpG?f bs ^pR \G [9$ YL,1 W T] RET Pz&< N*6 L8% K G? EByCvtFyA38y@[hy>  >=)415141312111098765432100123456789101112131415D1Ethernet.silFigure 16Ethernet ControllerOutput_BTIOA = 016EthCEthCPd_InputTxCmdEnbl'TxOnTxEOPTxCntDwnRxCmdEnbl'RxOnRxBOP'--TestCmdEnbl'LoopBackNoWakeupsSingleStepTestClockTestColl'TestDataReportCollsHost Address<>RxOnTxOnLoopBackTxCollNoWakeupsTxDataLateSingleStepTxFifoPETxCmdEnbl' enables setting of TxOn and TxEOPRxCmdEnbl' enables setting of RxOn and RxBOP'TestCmdEnbl' enables setting of LoopBack, SingleStep, NoWakeups, TestClock, TestColl', TestData,and ReportCollsHost Address is set by backpanel jumpersPDInputPDNewPDOldEClkEClkEClkFSMPDCarrierPDEvent[0:1]0 No event1 Collision2 Data 03 Data 1PhaseDecoderReceiverFSMRxCollisionRxEOPRxSync'RxIncTransRxCRCResetRxCRCClkRxDataRxCtrl[0:1]RxSRFull'EClkSR1EClkRxDataRxEOPReceiverFIFOefdccdfe211616-wordx 19-bitRAMT1ParityEthData.18IOAtten18EthData[0:17]T1T1IOB18RAM16-wordFIFORxFifoRdPtrRxFifoWrtPtrTxFifoRdPtrTxFifoWrtPtrx 18-bit18TransmitterT118SR1TxDataTxCRCEnblRxDataRxCRCClkRxCRCResetRxCRCErrorCRCTxCRCClkCheckTxOffT1TxFifoPECRCGenFSMTransmitterTxCRCEnblTxCRCClkTxGoneTxGoTxDataTxSRCtrl[0:1]TxEndTxAbortTxStartTxSREmptyGotTxBitwire-orPhaseEncoderTxOffXcCollisionRxCollisionTxGoPEOutputTxCollisionGotTxBitTxCollisionTxOffTxFifoPETxDataLatedcTxAbortabTxFifoEmptyTxEOPTxEnddcTxFifoFullTxEOPbaPDCarrierTxStartReceiverTransmitterRxCollisionRxDataLateRxCRCErrorRxIncTransPd_Input1514131211109876543210EthDTIOA = 015RxCollisionRxDataLateRxCRCErrorRxIncTrans------------------------8/30/81(Receiver status word following end-of-packet)=$e$$e$Kt#G#C;#?W#;t#7#3#0#,,#(H#$e# #####I$e$E$e$A$e$:$e$2I$e$.e$e$*$e$"$e$$e$+$e$6,$e$&$e$$e$H$$H$>^$M$$H(>;$O>;$L$k>^$k$$&$5$$d$",$)$-$1$9$AI$E-$d+H+++++#+'+++/+3e+7+:+>+B+F+Jt+H$=f$Bu%:r !p$9(H +&9t'sd&Wd%:&W&WV's&W%:'s&W%:#&W&&W+&W/:'s/:&W/:%:3&3%;t's:&W;-%:6t&6%>&>%Bf&Bf%F&F%I&Jt%d ] $!] 9$|,.et2I6,6,d9>>;>BBBEFdJ-IJ-,-!`r (I$b5$bX c$`$ `$ `$2b5d$`$2`$`$c$sc$`$s`$s`$2bXb5r$b5+$bX udJdJdJ`g$`C +$c$^@$^$$!t_&Wb &W` %:`$%:a$%:_$&_ &] &\ &[ bX :`.cd$4W$ .W_$.W_$ /:^.0W]4cQ +$5cu 4` r$5[5`4_' +$4] r$4\_ r$4Y r$4X5 r$5_J 5] 5\5b5Y 5XX uZ W$2 W$W<$ Z&$ tX 9X$ Y.X|$ VuS P&$2 P&$PJ$ S4$X$Q$Z&$PJ$ P&$P&$ $4a +$4Z r$X|$9tXQ$9QWVf|FYFYHFYHFYH$SSSSdUJ$UVC9$U$dShQ$dNUtTSRUmr$Q$P&$2P&$ :PJ$S4$uStS :Q$!Q (uQ!T $2!T $#T-$!W$sU$|R$tU #Um $!uW\$ZJ$Z$ BB$2 BB$rBf$ EP$C$ EtC C;$ r|AH;$G$I{$t?BC9>$9>$?$9G$\ [f \9$[C9$ J- H H9$ J 9$ArC$C;$|AtFVDC$EP$Bf$BB$BB$2duEsC;$+|AtC;C;$|AtCAI$? H?d$A&$0T $0R$0QC$1,T-1,R1,Qf 9Um$=P$9O$9O$=R :WSH>^d$>BB$#<$d;$;$#?$9Q=R9$H<d$=C$dHd$sJ$G$sG$sG$2HuKH$ tIGd$J $I$I{$I4$H$H_$H$dW_d$dW$dV$dV$dVC$dU$dU$dUm$ ? >6 +$2l r$3 +$53 r$7 +$4;d1$d1$d:4d$658 65W392 1$9865W 39^$7$6$53$3$$9$ G9^$#HuDX3=$-IDd$-I<$-I<$.tAI.e?C9$&BB$&Bf&@$&A &?{$&? &>$&>;3C$4C;3A$4A 3@P$4@t(H: (H9;(H7(H6t (6P$(7$(H9G$(H:{d$.9$.9$.6P$.7%$-8$G-89$-7$k-79$/:|5/:528$2t8/|0g/0g(3$(2%$(Ht3 (H2I12$23,|+,+/$Vt/: -l$V-/|,/,.A$ t0 :/$&W1 $(/:$&W/$&W/$(/$)1 $*/:$)/$)/$*/$1/$2I/: pM * d_'9$\_$Z$dt_J d] d\ d[ ]$ _$rZJ$I$9p=f$H$JttFB>:73e/+'#+HdE-$AI$9$)$",$d$$5$&$$A$A>^$Ld$$>;$p99 /:t-9 -$1$7I66?>=JJtIFB:3+W's#DXu9t V.9Kmc 6Dorado Hardware ManualEthernet ControllerAugust 1, 198591Ethernet ControllerAn Ethernet is the principal means of communication between a Dorado and the outside world.An Ethernet is a broadcast multi-access packet switched network which can connect up to 256stations separated by as much as 1 kilometer with a 3 mHz channel. The 'Ether' is a passivecoaxial cable to which each station is connected through a transceiver that is high-impedance whenreceiving, low impedance when driving.Read this chapter with Figure 16 in view.Ethernet PacketsEthernet data are encoded in packets. Packets are preceded by a low signal (i.e., silence) on theEther; they begin with a one-bit prefixed by the transmitter, called the start bit. Bits in the packetare phase encoded, where the bit cell time is nominally 340 ns; phase encoded signals have onedata transition per bit cell and its direction (low-to-high = 1) is the value of the bit. Midwaybetween these there may be a setup transition, so that the next data transition can be in the correctdirection.Packets end when no transitions are detected for more than 1.5 bit times and the Ether is low.Collisions are transmissions that overlap in time and cause malformed and undecodable bits.Transmitters jam the Ether with a continuous high for several bit times after participating in acollision. Collisions are of four types: too many transitions, in which two transitions occur within.25 bit times; too few transitions, in which a transition occurs between 1.25 and 1.5 bit times afterthe last one; end-of-packet (EOP), in which no transitions occur for more than 1.5 bit times andthe Ether is low; and jam, which is the same as EOP except that the Ether is high.In a well-formed packet that does not experience a collision, the start bit is immediately followedby an 8-bit destination host number, then an 8-bit source host number. This is followed by anindefinite number of 16-bit data words, a 16-bit checksum, and finally silence.Even when transmitted without a source-detected collision, a packet may fail to reach itsdestination; packets are delivered only with high probability. Stations requiring a lower residualerror rate must follow mutually agreed upon communication protocols.When the sender of a packet detects a collision, some method is needed to arbitrate (withoutcommunication) its use of the Ether with other stations contending for it. The algorithm used onthe Ethernet, called the 'binary exponential backoff collision algorithm,' is discussed in the abovereferences. It involves waiting a random interval and then reattempting transmission. The (ideal)distribution of the random intervals depends upon many factors. fp",q3pG?f ar ^ep P \A ZO Y02 W;& SqX) Ns K>pqp$ Is0qp GqpM Eqp E Dqp, BI >^ = q p; ;A qpL 9w*qp 7qp, 5 q pE 4qp8 021 .9% -O )< ' q1p$ & D "0, Y J 7"A l? ~ %=LDorado Hardware ManualEthernet ControllerAugust 1, 198592Controller OverviewThe Ethernet controller is a slow I/O device packaged with the disk controller on the DskEthlogic board. These two devices require more edge pins than are available in an MSA-I/O slot, sothe board must be mounted in a Fast I/O slot (see Figure 2).A cable connects the controller to a red transceiver outside the Dorado enclosure; this transceiveris almost identical to the ones used for Altos and other computers, the difference being that it uses+12 volts rather than +15. Dorado transceivers are painted bright red and have large blocklettering saying "Dorado only". Plugging in the wrong type of transceiver will not damageanything; it just won't work. The cable between the controller and the transceiver containstwisted-pair signals for receiver data, transmitter data, collision, +5 v, and +12 v.The controller has independent transmitter and receiver sections. Because these two sections arecompletely independent, the Dorado can receive its own transmissions. This is an important aid inhardware and software debugging and simplifies the device driver, which need not check forsending to itself. Furthermore, the receiver can receive consecutive packets separated by theminimum inter-packet spacing (510 ns). This means that the Dorado can receive, without loss,streams of packets directed to it by mulitple hosts and packets that immediately follow broadcasts.This capability is important for servers and other high-performance applications.The controller uses two tasks, one for the transmitter (EOT for Ethernet Output Task) and one forthe receiver (EIT for Ethernet Input Task). The receiver task is higher priority. To permit twoinstruction/wakeup loops, a wakeup request is removed whenever the Next bus says the task isabout to run. This simple strategy can be fooled into removing a request when NextLies occurs,but this is harmless since the required service rate is low. To avoid a spurious wakeup, a wakeupis not requested again until after the task has blocked. A debugging control bit can be set whichprevents wakeups even when all other conditions are satisfied.The transmitter and receiver each have 16-word x 20-bit Fifos. The bits are 16 data + 2 parity +2 spare (the receiver uses one of the spare bits). Each Fifo has read and write pointers,multiplexed into the address inputs of the storage chips, to select the next location to be read orwritten; these pointers are zeroed by IOReset. A Fifo is empty when the pointers are equal andfull when (WritePtr+1) mod 16 equals ReadPtr. There are bus registers between the Fifos andIOB. Service requests from the Ether side of a Fifo are given priority. The Fifos are synchronousto t1.The basic clock for transmitting and receiving data from the Ether, called EtherClk, originatesfrom a 23.5 MHz crystal oscillator. The memory system's Pendulum clock (period 16 ms) is alsoused to time retransmissions after a collision, as discussed later.The receiver runs continually; its phase decoder (PD) samples the Ether every EtherClk; a finitestate machine (FSM) driven by the samples detects the presence or absence of packets on theEther, zero/one transitions, and collisions. Another FSM accumulates the status of the packet andcontrols a shift register that assembles 16-bit words from the incoming data. Words in the shiftregister are written into the receiver's Fifo together with odd parity on each byte; the status iswritten into the Fifo after the last word of each packet and marked to distinguish it from datawords. This allows the receiver to handle back-to-back packets; microcode decides what to dowith each packet as it is read from the Fifo. EtherClk is used for receiver stages through the shiftregister; data in the shift register is synchronized to the Dorado system clock as it is written into fp",q3pG?f bs ^p> \L [< W%qp # U23 T/, RE: Pz> NU K>q pqp IsF G2( EK DW BI30 @~Q = ?2c<= 8<= <<=  ;A.:;A:;A":;A; 9w-/ 71. 5[ 4\ 2L> .!@ -J +E` ){H '$q p %D $#t$p 3qp 9qp 7C #qp )2 0,6 e(9 ?# J J ;7. p$A& )=\Dorado Hardware ManualEthernet ControllerAugust 1, 198593the Fifo.When the transmitter is turned on, it attempts to send one packet and then must be restarted bymicrocode. The EOT fills the Fifo; the transmitter FSM loads the shift register from the Fifo andsupplies a serial bit stream to the phase encoder (PE). Transmitter status is read directly from thecontroller status registers (unlike receiver status, which travels through the data path). Data issynchronized to EtherClk between the output of the shift register and the input of the PE. Acollision may be detected by either the transceiver or the PD. The occurrence of a collision iscaptured, synchronized, and used to abort the outgoing packet after jamming the Ether briefly.The controller has a number of features to help debugging. All of the interesting internal state isavailable via the IOB and the muffler system. The transceiver can be disconnected and PE outputinternally connected to PD input under firmware control. Task wakeups can be disabledpermitting the controller to be driven entirely from emulator-level software. The internal clockcan be single-stepped. These features permit the construction of a simulation program whichcompares its predictions with what the controller is actually doing.ReceiverMost of the receiver runs continuously, tracking traffic on the Ether. The PD reports what it seesto the receiver FSM, which assembles packets in the shift register and buffers them in the Fifo.As words emerge from the Fifo into the bus register, they are either discarded or generate awakeup request under control of the wakeup logic. Following the last data word of each packet asit travels through the Fifo are the CRC word and a status word. IOAtten branches when a statusword is present in the receiver bus register. Data and status are synchronized to the Dorado clockbetween the output of the shift register and the input of the Fifo.The peculiar placement of status bits in Figure 16 eases emulation of the Alto Ethernet controller.The PD is a FSM which takes in raw phase-encoded serial data and produces phase decoderevents and carrier. Phase decoder events are 'saw a zero bit', 'saw a one bit', and 'saw amalformed bit'. Carrier indicates that the PD is seeing transitions on the Ether (i.e. the Ether is inuse). Since the PD is completely digital, it can be single-stepped for debugging. Receivercollision detection, a by-product of this decoding technique, works as well as transceiver collisiondetection.The receiver control is another FSM that takes in PD output and produces control and statussignals. RxSRCtrl controls the shift register and the bit counter. The bit counter decrementswhen a data bit is shifted into the shift register and resets to -1 when the status is parallel loadedinto the shift register. RxSRFull' is low when the next shift will make the register full. RxEOPtravels in parallel with each Fifo word and is true if the word is an ending status word. This bit iscalled EthData.18 when it is in the bus register where it can be tested with IOAtten.Writing data or status from the shift register into the Fifo has priority over loading the busregister from the Fifo. Byte parity is computed at the shift register output and travels with thedata through the Fifo and the bus register, down IOB and into the processor where it is checked.The optimum point at which to synchronize received data with the Dorado clock system would beat the input to the PD, where there is only one signal to synchronize, except that this would makeproper operation of the PD depend upon the Dorado clock period. The next best sync point is fp",q3pG?f b ^6) \Y [$q p/ YLR WZ Ua S#; PzP N.2 LV KE IPA GD Bls >p X =/B ;e= 9M 7X 6B! 4:Cy1yt31 .*pO ,_"9 *'@ (V 'Z %5 ![ @ .L c#?  \ U \ R Y 8( U@ ] N N y=]ADorado Hardware ManualEthernet ControllerAugust 1, 198594the PD output where the number of signals has only grown to three. The problem here is thatthe PD can produce events faster than they can be synchronized to the Dorado clock withoutbuffering. Consequently, synchronization takes place after the shift register where the number ofsignals exceeds 20. This is not as unfortunate as it seems because status and data use the samepaths and can share a single synchronizer, RxSRDump, which produces RxFifoWE' each timeRxFSM pulses RxSync'. This leaves only RxCollision and PDCarrier which must be synchronizedfor the transmitter. RxCollision shares a synchronizer with XcCollision, and PDCarrier's is asimple level synchronizer.A receiver data-late occurs when the receiver FSM requests a Fifo write and the Fifo is full. Inthis case the write does not happen and the data is lost. RxDataLate is cleared after an end-of-packet status word is successfully written into the Fifo. This status has the data late error bit setso that the EIT is notified that the preceding packet was bad.EIT wakeup requests occur when the bus register contains an interesting word (provided that theEIT is currently blocked, as discussed earlier). Words are interesting if they emerge from the Fifointo the bus register while RxOn and RxBOP are true and NoWakeups is false. RxBOP is setafter the status word for a packet is discarded, so that the next word out of the Fifo (presumablythe first word of the next packet) can generate a wakeup. It is reset by the EIT to discard theremaining words of a rejected packet (usually because the address didn't match). The receivermay be reset at any time by clearing RxOn. No more wakeups are generated and every word isdiscarded as it emerges from the Fifo. When RxOn is next set, the receiver will continue todiscard words until it has discarded a status word. It will then set RxBOP, and the next word(first word of the first packet after turning on the receiver) will cause a wakeup.TransmitterWhen the transmitter is turned on, it attempts to send one packet and then must be restarted bymicrocode. At the request of the wakeup logic, the EOT fills the Fifo using Output_B to the busregister. The transmitter FSM loads the shift register from the Fifo and supplies a serial bitstream to the PE. Transmitter status is read directly from the controller status registers (unlikereceiver status, which travels through the data path). Data is synchronized to the Ether clockbetween shift register output and PE input.EOT wakeups occur when the bus register is empty, TxOn is true, and TxEOP, TxCntDwn, andNoWakeups are false (provided that EOT is blocked, as discussed earlier). After delivering thelast word of a packet, EOT wakeups are disabled by setting TxEOP. While counting down acollision retransmission interval, firmware can disable wakeups until the next tick of Pendulum bysetting TxCntDwn. The transmitter may be reset at any time by clearing TxOn, which stopswakeup requests and shuts down the PE within 2 bit times.The binary exponential backoff collision algorithm must be implemented in microcode. Thecontroller merely provides a way to generate a wakeup on the next rising edge of Pendulum,making the grain size of countdown intervals 16 ms for the Dorado (compared to 38 ms for Altosand Novas). Note that setting TxCntDwn prevents a wakeup; for one to actually occur whenPendulum clears it, the bus register must be empty and TxEOP must be false. Pendulum isconsidered to be a foreign signal so it is synchronized before being applied to the reset input ofTxCntDwn. fp",q3pG?f bE `ST ^_ \J ZB Y) P W^7' U R"<% PWV NS L> IP U GV E9 CQ B%T @[H >.- <Y :L 90S 4s 0p6) .U -$; +EQ ){A '+ $>: "s? B ?# G I9 Y  I B0up!up w qp) U  U , <[;MDorado Hardware ManualEthernet ControllerAugust 1, 198595Loading the shift register from the Fifo has priority over writing into the Fifo from the busregister. Byte parity is computed in the processor and travels with the data down IOB into thebus register, and through the Fifo to the shift register where it is checked.The transmitter control is a FSM which takes in start, end, and abort signals and produces controlsignals. TxSRCtrl controls the shift register and bit counter. The bit counter decrements when adata bit is shifted into the shift register and resets to -1 when the next word is parallel loaded intothe shift register. TxSREmpty' is low when the next shift will make the register empty. TxDatawire-or's the start bit at the beginning of each packet. TxGone clears TxEOP to cause a wakeupat the end of each packet. The transmitter starts when the Fifo is full or, if the packet is less than15 words long, when TxEOP is true. The transmitter ends normally when the Fifo is empty andTxEOP is true. The transmitter aborts when a collision, Fifo parity error or data late occurs.TxAbort can be tested with IOAtten.A transmitter data late occurs when the TxFSM requests a Fifo read and the Fifo is empty butTxEOP is false. The PE sends one random bit and then stops. The resulting packet has an illegallength and probably a bad CRC.The PE inverts and latches TxData at the start of each bit cell and inverts the latched value 1/2bit time later. TxGo, synchronized to the beginning of a bit cell, enables the PE. The PEassumes that a data bit is available long before it is needed and acknowledges each bit afterlatching it by generating TxGotBit.A collision may be detected by either the transceiver or PD. The occurrence of a collision iscaptured, synchronized, and used to abort the outgoing packet. The output of the first stage ofthe TxCollision synchronizer is wire-or'ed with PD output to jam the Ether after a collision. Thejam lasts for one or two bit times, being the delay through the TxCollision synchronizer, TxFSM,and TxGo synchronizer.ClocksThe controller needs a clock with a nominal frequency of eight times the Ether bit rate. TheSingleStep control bit selects either the 23.53 mHz crystal oscillator or single Dorado clocksinjected under program control. The clocks for the Ether-synchronous parts of the controller areconstructed from this basic clock.The slowest Dorado clock period at which the transmitter works is 42.5 ns. Disabling the Doradosystem clocks while TxOn is true causes a transmitter data late. If TxGo is true, the packet ischopped off, causing an incomplete transmission and probably a runt bit. When the clock isreenabled, the PE sends a few fragmentary bits and then the data late aborts the packet.The slowest Dorado clock period at which the receiver works is 85 ns. Disabling the Doradosystem clocks causes a receiver data late. The next packet that arrives after the clock is reenabledreports the data late. fp",q3pG?f bU `SV ^M [M YL20 WA& UM S R R"] PWT N Q L# IP> GR E BIO @~O >3* <# 9wL 7#= 5*8 4` 2L -3s )pH 'P &,a $a" N %] ZI ; F S/6  A=SDorado Hardware ManualEthernet ControllerAugust 1, 198596Task WakeupsThe controller is designed for two completely independent tasks, with the receiver higher priority.Two IOAs select data and status/control registers. IOAtten may be tested to decide whether awakeup request is just for another word or something special (ending status for the receiver, or PEaborted for the transmitter).Task wakeups must, on the average, be serviced within 5.44 ms. The transmitter and receiver eachhave 17 words of buffering (bus register + 15 Fifo + shift register) so the variance can be quitelargeaccumulated delay of up to about 90 ms is tolerable, while longer delay will cause a datalate error. fp",q3pG?f bs ^pc \? [D YL U;up TX RE up4 Pz  Ni=ZDorado Hardware ManualEthernet ControllerAugust 1, 198597Muffler InputAll muffled signals on the DskEth board are accessible to Dorado firmware. The method bywhich a particular signal is selected and read out is discussed in the "Muffler Input" section of the"Disk Controller" chapter. Signal addresses 1208 to 1778 for the Ethernet controller areenumerated below. Unless it is obvious, signals which are specific to the receiver or transmitterhave Rx or Tx respectively somewhere in their names.Table 26: Ethernet Muffler SignalsWord BitNameMeaningERX0 120PDNew1/8 bit time sample of PD input signal 121PDOldPDNew delayed one sample time122:125PDCnt[0:3]Number of samples since last data transition 126PDCntCtrlIncrements or clears PDCnt 127ReportCollisionsControl register bit that enables PD collision reporting 130RxBOP"Beginning Of Packet" enables receiver data wakeups 131EthData.18Marks status word terminating a packet 132 133RxCRCErrorOutput of receiver CRC checker 134RxDataLateReceiver Fifo overflowed 135RxBusRegFullWord in BusReg can be read with Pd_Input 136RxFifoFullReceiver Fifo is full 137RxFifoEmptyReceiver Fifo is emptyETX140:142TxState[0:2]State of transmitter FSM 143TxEOPTransmitter data wakeups are disabled 144TxBusRegFull'Word is waiting to be written into the transmitter Fifo 145TxGoneTransmitter FSM is shut down 146TxSREmpty'Transmitter shift register is empty 147TxCntDwn'Transmitter wakeups disabled until next pendulum clock 150TxCRCEnblShift/compute control for transmitter CRC 151TxGoEnable PE 152TxDataSerial data input to PE153:154TxSRCtrl[0:1]Transmitter shift register control 155PEOutputPhase Encoder (PE) output 156TxFifoFullTransmitter Fifo is full 157TxFifoEmptyTransmitter Fifo is emptyERX1160:162RxState[0:2]State of receiver FSM 163RxCollisionReceiver-detected collision 164PDCarrierThe Ether is in use165:166PDEvent[0:1]PD output (no event, collision, 0, and 1) 167RxSRFull'Receiver shift register is full 170RxEOPMarks status word terminating a packet 171RxSync'True for one cycle triggering write of SR into Fifo 172RxIncTransReceiver incomplete transmission 173RxCRCResetResets receiver CRC chip 174RxCRCClkClocks receiver CRC ship 175RxDataSerial data output from RxFSM176:177RxSRCtrl[0:1]Receiver shift register control fp",q3pG?f bs ^p N \I [0Zt[pZt[p YLJ W4!_S_vF#yPwyO`n"tyLtyKan"t&yJn"tyHn "t,yG?n"t yEn"t1yD}n"t )yCn "t!yAny@[n "ty>n "ty=n "t$y<8n "t y:n "t y89y6n "ty5xn"t y4n "t3y2n"t y1Un "t y/n"t +y.n"t y-3n"ty+n"ty*rn "t"y)n"ty'n "t  y&On "t  y#y"Pn "ty n "t yn"ty.n "t)yn"tyln"t!y n"t/yn "tyJn "tyn"tyn"ty(n "t   \F [Y YLxV!t @V@TxR @9xPW @!xN# @+ I-s Ep E.tEpP C/5 B%O @[I > x;et @)x90@E@7x5@S@4:4@2x0@Q@/D<@- ut(@,< x* @&x'@E @&sx$>@X@"1!@!}xH @!x@%+@x~ @$xJ@5x@&-@n'x:@&: @,x ^@K@ P@  y<][Dorado Hardware ManualEthernet ControllerAugust 1, 198599ReportCollisionsallows the PD to report malformed bits as collisions. Cleared by IOReset.Status RegisterTIOA of 168 also selects the (read-only) status register. The bits in this register are the mostinteresting to the microcode. Less interesting state is available from the mufflers.Host Addrthe host address set by pullups on the backplane.RxOnthe receiver is enabled.TxOnthe transmitter is enabled.LoopBackthe interface is looped back.TxCollthe current output packet was aborted by a collision.NoWakeupsall wakeups are disabled.TxDataLatethe current output packet was aborted by a data late.SingleStepthe 23.53 mHz oscillator is disabled.TxFifoPEthe current output packet was aborted by a parity error. fp",q3pG?fxbAt@J ]Ks YpYLtYpV XUxTt@.xR@xPz@xNF@xL@5xI@xG @5xEt @%xC@@8 C<$qDorado Hardware ManualOther IO and Event CountersAugust 1, 1985100Other IO and Event Counters In addition to the disk, ethernet, and display controllers discussed in earlier chapters, Doradocontains a general input/output interface and a junk task wakeup located on the IFU board; thetwo registers used in this interface may alternatively be used as event counters in performancemonitoring, and that use is also discussed here.Since the IFU board is not interfaced to the IOB, it cannot use the slow io system to control thesefeatures, so functions are used instead.Junk Task WakeupThe IFU board contains a circuit which wakes up the junk task (task 1) every 32 ms. The wakeupis dismissed by the AckJunkTW_B function; this function interprets B[15] as follows: a 1 enableswakeups; a 0 disables them; B[0:14] are ignored. The junk task can dismiss the wakeup by doingIFUTest_B with any value on B (but B[15] must be 0 to reenable the wakeup at the next 32 mstick).Junk task microcode will, among other things, maintain a Real Time clock.General IOThe General IO is not normally used except by the Event counters microdiagnostic. There is aturn-around jumper on the right side of the IFU board to run the diagnostic.A 16-bit register called GenIn (synonym EventCntA) is used for general input; it can be read withthe B_GenIn (synonym B_EventCntA) function but cannot be written by firmware. When usedfor general input, GenIn is written with information that is TTL-to-ECL converted from thebackpanel.A 16-bit register called GenOut (synonym EventCntB) is used for general output; it can be eitherread with the B_GenOut (synonym B_EventCntB) function or written with the GenOut_B(synonym EventCntB_B) function. GenOut is connected to the backpanel through ECL-to-TTLconverters.The choice of using one of these registers for general I/O or for event counting is determined bythe InsSetOrEvent_B function.Event CountersThe GenIn and GenOut registers can alternatively be used as event counters. They cannot, ofcourse, be used simultaneously for general I/O. The registers are setup for either I/O or eventcounting by the InsSetOrEvent_B function, where B[0:15] are interpreted as follows: fpQq2pEf arp ^e U \ qpqp Z>q p Y0 Uc S( Ns K>p,$tp Isa GJ E5$tp D @I ;s 8p#9 6KL 2a 0X /!Z -V )` (R &OM $ ! W H /s pA Z (S  I H| G E DZ* B%V >pY = &8 ;A!: 9w` 90<.Dorado Hardware ManualError HandlingAugust 1, 1985102Error HandlingIn addition to single-error correction and double-error detection on data from storage, Dorado alsogenerates, stores, and checks parity for a number of internal memories and data paths. Thegeneral concepts on handling various kinds of detected failures are as follows:(1) Failures of the processor or control sections should generally halt Dorado because thesesections must be operational before any kind of error analysis or recovery firmware can beeffective.(2) Failures arising from memory and I/O sections should generally result in a fault task wakeupand be handled by microcode. In some situations, such as map parity errors, it is especiallyimportant to report errors this way rather than immediately halting because firmware/softwaremay be able to bypass the hardware affected by the failure and continue normal operation until aconvenient time for repair occurs. In other situations, the firmware may be able to diagnose thefailure and leave more information for the hardware maintainers before halting.(3) IFU section failures and memory section failures detected by the IFU should generally bebuffered through to the affected IFUJump, then reported via a trap; in this way, if it is possible torecover from the failure, then it will be possible to restart the IFU at the next opcode andcontinue.(4) Memories and data paths involving many parts should generally be parity checked. It is notobvious that this is always a good idea because extra parts in the parity logic will be an additionalsource of failures, but instantly detecting and localizing a failure seems preferable to continuingcomputation to an erroneous and undetected result.(5) When Dorado halts due to a failure, information available on mufflers and in the 16-bits ofpassively available error status (ESTAT) should localize the cause of the error as precisely aspossible.Since the MECL-10K logic family has a fast 9-input parity ladder component, the hardware usesparity on 8-bit bytes in most places; there is usually insufficient time to compute parity over largerunits. IM and MIR, two exceptions, compute parity over the 17-bits of data in each half of aninstruction; and the cache address section computes parity over the 15 address bits and WP bit.Odd parity is used throughout the machine, except that the cache address section and IFUM useeven parity. Odd parity means that the number of ones in the data unit, including the parity bit,should be odd, if the data is ok.The control processor (Midas or the baseboard microcomputer) independently enables variouskinds of error-halt conditions by executing a manifold operation discussed in the "DoradoDebugging Interface" document. It also has to initialize RM, T, the cache address and datasections, the Map, and IFUM to have valid parity before trying to run programs. Reasons for thiswill be apparent from the discussion below.When Dorado halts, error indicators in ESTAT indicate the primary reason for the halt, andmuffler signals available to the control processor further define the halt condition; ESTAT alsoshows the halt-enables. Midas will automatically prettyprint a message describing the reasons foran error halt. The exact conditions that cause error halts are detailed in the sections below; the fp#q 2pFf ar ^epI \J ZO W^ P U'3 S PWa N6' LK J` I-<% GbO CZ B%e @[= > ;L 9T Y 7c 52 2LJ 0O . +ET ){I '#; %K "sT 11 ! l O F [  7* B+ #7 [ ;J p$? )<\)Dorado Hardware ManualError HandlingAugust 1, 1985103table here shows the ESTAT and muffler information which is relevant.Table 27: Error-Related SignalsESTATESTAT Task ErrorEnableExperiencingRelated Muffler Signals Bit Bit Haltand MeaningRAMPERAMPEenTask2BkSTK, RM, or T parity failure.RmPerr and TmPerr mufflers on each processorboard indicate which byte of RM/STK or T had aparity failure. StkSelSaved indicates that RmPerr appliesto STK rather than RM.MdPEMdPEenprocessor-detected Md parity failureTask2Bkif immediate _Md (_MDSaved false)Task3Bkif deferred _Md (_MDSaved true)MdPerr muffler on each processor boardshows which byte of Md failed.IMrhPEIMrhPEenCTDparity failure of IM[17:33]IMlhPEIMlhPEenCTDparity failure of IM[0:16]IOBPEIOBPEenTask2BkPd_Input parity failure if IOBoutSaved falseTask2BkOutput_B parity failure if IOBoutSaved trueIOPerr mufflers on each processor board showwhich byte failed.MemoryPEMemoryPEencache address section parity failure,cache data parity failure on write ofdirty victim or dirty Flush_ hit, orfast input bus parity failure.Processor ErrorsThe processor has parity ladders on each byte of the following:input to RM/STKgenerate parity for write of RM/STKinput to Tgenerate parity for write of TBgenerate parity for DBuf_B, MapBuf_B, Output_B, IM_BIOBcheck parity for Pd_Input and Output_BMdcheck parity for _MdRcheck parity for _RM/STK (unless bypassed from Pd orMd or replaced by _Id)Tcheck parity for _T (unless bypassed from Pd or Md orreplaced by _Id)Input ladders to RM/STK and T generate parity stored with data in the RAM; these ladders arenot used for detecting errors.The processor computes parity on its internal B bus (alub). The generated parity may betransmitted onto IOB when an Output_B function is executed; Store_ references write B data andparity in the cache; parity for IM writes and map writes is computed from B parity. None of theother B destinations either check or store B parity. External B sources do not generate parity.Parity on R/T is checked only when the R/T data path is sourced from the RAM, not whenbypassing from Md or Pd is occurring, and not when R/T is sourced from Id. A detected failure fp#q 2pFf bE 5]sXyZt yYL  (yW (yUMu ((Stutu(R.(Q+t utu(OyM ($L(!K>((Itu(H|yF (yD (yC (t uA(t u(@[tu&(>y=/ (%(;%(:n$(9  4s 0p?:-3R:+i R:)R4:'R&:& R:$>R4R"s: R5R l9#  0J e1- ;% L ^M V L<\FDorado Hardware ManualError HandlingAugust 1, 1985104causes the RAMPE error halt, which indicates that some byte of RM, STK, or T had bad parity. Md parity is checked whenever _Md is done; a failure causes the MdPE error-halt when enabled.I/O devices (optionally) compute and send odd parity with each byte of data; the processor checksparity when the Pd_Input function is executed, but not when the Pd_InputNoPE function isexecuted. When enabled, an IOBPE error halts the processor at t4 of the instruction that sufferedthe error; Task2Bk shows the task that executed the instruction. The processor also checks IOBparity on Output_B, and an error halts at t4 as for Pd_Input.The processor does not generate or check parity on the A, Mar, or Pd data paths. Any failures ofthe A, Mar, B, Pd, or shifter multiplexing or of the ALU go undetected; failures of Q, Cnt,RBase, MemBase, ALUFM, or branch conditions go undetected.Control Section ErrorsThe control section stores parity with each 17-bit half of data in IM. When IM is written, the twobyte-parity bits on B are xor'ed with the 17th data bit to compute the odd parity bit written intoIM. It is possible to specify that bad (even) parity be written into IM, and this artifice is used tocreate breakpoints; bad parity from both halves of IM is assumed to be a deliberately setbreakpoint by Midas.IM RAM output is loaded into MIR and parity ladders on each 17-bit half give rise to errorindicators that, when enabled, will halt the processor after t2 of the instruction suffering an error.For testing purposes, halt-on-error can be independently enabled for each half of MIR. Both theunbuffered output of the MIR parity ladders and values buffered at t2 appear in ESTAT. Thebuffered values show the cause of an error halt, and the unbuffered signals allow Midas to detectparity errors in MIR before executing instructions or when displaying the contents of IM.The special MIRDebug feature discussed in the "Dorado Debugging Interface" document preventsMIR from being loaded at t2 when MIR parity is bad. In other words, when the MIRDebugfeature is being used, all of the t2 clocks in the machine will occur except the ones to MIR. Thisfeature prevents the instruction that suffered an error from being overwritten at the expense ofbeing unable to continue execution after the error. MIRDebug can be enabled/disabled by thecontrol processor.IFU ErrorsThe IFU never halts the processor; any errors it detects are buffered until an IFUJump transferscontrol to a trap location. The errors it detects, discussed in "IFU Section", are parity failures onbytes from the cache, IFUM parity failures, and map parity failures on IFU fetches.Memory System ErrorsThere is no parity checking on Mar or on data in BR, so any failure in the address computationfor a reference goes undetected. However, valid parity is stored with VA in the cache, and anyfailure detected will cause the MemoryPE error to occur, halting the system (if MemoryPE isenabled). fp#q 2pFf b qp< _9#qp [A ZCX XqpXuXp V qp> U*+TuU*p Q2/ PS NF: I-s Ep:) CQ B%f @[@ > ;T 9T7qp8u9Tp 7K 5D51u5p 34- 2)5$ .H ,,`u,p. +"#*u+"p) )W7) 'M % s 7p S l Z S s pL LP K  p=\@Dorado Hardware ManualError HandlingAugust 1, 1985105Parity is also stored in the Map (computed from B parity) and an error causes a fault task wakeupin most situations (Exceptions: IFU references and Map_ references do not wakeup the fault taskwhen a map parity error occurs).The cache data section stores valid parity with each byte of data. When a munch is loaded fromstorage, the error corrector carries out single-error correction and double error detection using thesyndrome and recomputes parity on each 8-bit byte of data stored in the cache. When a wordfrom B is Store_'d in the cache, byte parity on B is stored with the data.A MemoryPE error occurs if, when storing a dirty victim back into storage, the memory systemdetects bad parity on data from the cache.The IFU and processor also check parity of data from the cache, as discussed previously.Sources of FailuresIn a full 4-module storage configuration, Dorado will have 1173 MOS storage, about 700 Schottky-TTL, 3000 MECL-10K, and 60 MECL-3 DIPs, and about 1500 SIPs (7-resistor packages). Thislogic is connected with over 100,000 stitch-welded, multiwire, or PC connections on each logicboard connect to sidepanels through about 2500 edge pins. Sockets are used for all the memorychips except for 256k chips in the machine; other parts are soldered in. Given all these potentialsources of failure, reliable operation has been a surprising achievement.Initial debugging of new machines has been slow and difficult, requiring expertise not easilyavailable in a production environment. In addition to mechanical assembly, board stuffing, andtesting for shorts and opens both before and after stuffing, each machine has averaged about oneman month of expert technician time to repair other malfunctions before it could be released tousers.Once released, the Dorados have been pretty reliable. During a 100-day period (6 October 1980to 14 January 1981) the CSL technicians kept records of service calls made for approximately 15Dorados in service at that time. The following summarizes the 43 service calls that were made.37 daysmean time between service calls per machine.45 days mean time between failures (some service calls were for microcode or softwareproblems).2.5 hours per machine per month average service time.13% of failures and 5% of time reseating logic boards in the chasis (connectors notmaking contact).11% of failures and 17% of time on open nets.13% of failures and 12% of time repairing 16k MOS RAM failures (standardconfiguration was 2 modules).37% of failures and 28% of time replacing other DIPs and SIPs.5% of failures and 10% of time on T80 problems. fp#q 2pFf b S `S/1 ^ [P YL Y W&5 UJ REU Pz* M'1 Gs D}pW B+- @X ?:$ =SH ;I 8V 6K Q 4M 2V 0 -z^ +,3 ):%y&s(y$>6y"s y ?5yDyy-y\.5/yy]>y / V &hO <\Y : G 8M 6.2 51N 1G /Q .*O ,_ (P '#A %XN #H !T Q;! $= 4* N '    V K.2 Is FqpP Bqp? ?qp4 ;qpIq 9p=q p 8' 4qp.# 2)0 1F -qp!; +1 (`qp: & #$qpL !Y8qp W qpC R q p*) ] K> J  Dqp!5 y3) 4 2<]+Dorado Hardware ManualGlossaryAugust 1, 1985109task - one of the 16 priority scheduled tasks. Special tasks are the emulator (task 0, lowestpriority) and the fault task (task 15, highest priority). Other tasks are paired with io controllers.VA - virtual address.Vacant - a cache entry or map entry which does not contain valid data.Victim (Vic) memory - stores 4 bits for each cache row. Two of the bits specify the victim whichwill be chosen if a reference to that row results in a miss, and the other two are the next victim.victim - on a processor reference that causes a cache miss, the cache entry chosen to be replacedby the referenced data.WP - write protected. Map entries and cache entries have bits with this name. fp%q5pEf bqpH `Sf \qp Yoqp@ Uq pqp2qp T3J Pqp/, N KqpL K=<_R oddJCNFFBLOCKASELLCBSELALUFRSTKALU carryALU[15]{BSEL, FF}Md *Md *Md *QTFF[4:7]FF[4:7]>>TRSHIFTER161616>>{LC}16ALUFM>>{xxx} Source of ControlTask-Specific**{LC}{BSEL}ControlBAALUAddress LogicFF[4:7]0,,FFFF,,0FF,-1-1,,FF{ASEL}{ALUF}Q16R'T'Programmer's View>>>>ALU=0ALU<0SubTaskALU rsh 1ALU lsh 1To devices16R < 0>IOBALUFMShCTIOA, StkPAMuxAMuxBMuxFFRF_WF_ShC_SubTaskShiftControlsRMSTKRSTK[0:3]{FF}RSTK[1:3]StkpSaved StkpRQFF[4:7]Md*T{FF}>>>>>>>>>>>>>>>>>>>ShC16168B+RBaseCnt>>>>>>>>B>Stkp>>>>>>>>>>T*MemBase*TIOA*CntOverflowCnt=0&-1oPipe0Pipe1Pipe2'Pipe3'Pipe4'ConfigDBufooFaultInfo'gh>hgLinkRWCPRegoMemCMemDIFUControlBMuxghoPointers16IOBIOAB>>>>>>>>>>ALUBrLo_BrHi_CFlags_ghMarMuxLoadMcrAB>Mar+>>>>>>>>>>>>>>>>>>>>>>>MapBuf_>>DBuf_MemX>>Store_Map_LoadMcrLoadTestSyndromeFetch_Store_Map_PreFetch_IOFetch_IOStore_MemoryIFU>>To ProcessorTo ControlMd*Fout>>>>>Fin>IFUFetch>10161681681616F/GF/G>16{FF}{FF,ASEL}{ASEL}MultiplyDivideCDivideQ lsh 1Q rsh 1{BSEL}DoradoFigure 1From devices{JCN,FF}>>>>>RdTPC_LdTPC_IM_Link_{FF}MOS_GenOut_BrkIns_>{ASEL}MemX{FF}{shift mask}Md*/0Carry'IOAtten'>>>>{FF}o>IFUTest_{FF}{FF}MemBX>FF[6:7]BR{ASEL}IdPdPipe5'PdA_IdRisIdA_IdTisIdPdId{ASEL}{FF}ProcSRN_B[12:15]IFaddr>B[3:7]MemBIFUMRH_IFUMLH_Id0 or 1by IFU256 x 16256 x 16PCX'Junk'IFUMLH'IFUMRH'BMux>D1ProgView.sil87/28/85012345677654321021001221001233210tKDX 3 (%:  V    $UG d$Et d$C; d$A d$> d$< d$:W d$8 d$5 d$3 d$1s d$/: d$- d$* d$( d$&W d$$ d$! d$ d$s d$: d$ d$ d$V d$ d$ d$ d$ d$ r d$ d$9 d$T dZJ GVf #H6tG)e4<$#H3#H4d\$%:`;t\$7\_$7\_$]Xd_U$\$d\y$]5$]$ |[/ Y#tBf#H823$9$=f=f =f; ;u&W 87$9t8eJ|J= $U $U: $U! $U( $U* $< $UI d$L d$ K$NX $U$K$=ft?<@9$=f@=fE=fD r3Br$r3er1r$r1r/r$r01$/$0 1G$1 $u3e107$+W_$-b5$*:te 2@r$u2I1,rpIKV$sH$UH_y$H_$yGBV$sD$UCy$C$yrEt VJ $ VE$r VE$ G$R$VO-$tS A$sJ$E$sE$B$?$U?{$?{$yA$"sBB$-]$r(+W$ V(E$'sJ-> @-@ 9$V@9$ =$V=]$V=$ ?{$ V>$ VA&$B 7=f$U5+zr$#7$H_$E$#Gf#D#E#I)A G$(H$*HIK$|FYA rD rCK'sE='sC'sA's@='s>'s4K's2's0's/J's-'s+'s*J's(%'<(AI$1 $.$ 3U$ /$r /^y$ /^$ p0r1,$t1=fC$.$>^9$^.@ GX +>dpP]%:`$*:|[/*:\+\L=vrB$9B@=BABC=ft8e 7G6tS|U$7Q7PJ7LD7I$9:W$+:4G$>^H$+W;P9$5&$3$$3$$+|Lv+Lv0WpO7tN:&$-p;t-5's|:(=f$7tS>;^Q$A[$U>;Z$>;Z$y?W\<5W|K2$2]$2$2$dd$utt,,X,,,,,,X1s??7X777XHHtV|sd$"stdr$sd$,ur%| J/: JuV::V::@tY$GfM$ 9@tM$@tM$ ]ASARAQAP AOtANXApW7_'$\d$T$T$2 WW$^ $.|T*RL2_9$9_J$/uZJ /W H;tUH;Qf=|W=ZLQ/LOM;M;-tV?W|S!AuU.|W+WtXX*:ZJ$*W$JR$*BBd$,sA*-d$,,-I?W($d@-(?W#$@-$eKSXKJP$KQfJTt$KJUGfTdGGfSGH;SXGfQGXG:X!\G9!^ G$Z GG$X GG$U GG r,9GGrG:Gr:9G0GG-dGC;GH*GF+GFrG)rGs|U=V$d=tV%: :G%:#G0W :G/:#G#6,G$T$ rMG ,G,s, &9$GuZJGY.GXGVGU9t-#r#9;ub DXtVI|JIIIJDE-$EtE-$EEsEE-$E-O$E-$AVG23,32]$37I|:( +G&t<uBt5@4 =f:8e5<+W6tN{$6tLd$6tP&d$6tQd$<|N!<LvPanelWiringPanelWiringFive 240 CFM (free air) fans estimated to produce375 CFM airflow in the enclosure.Estimated temperature rise of the exiting air is about8 degrees C.Power consumption on each logic board averagesabout 85 watts, on each storage board about 55watts.On each board -5 V power is distributed byfingers reaching across the board on the topside from the back, -2 V power by fingersreaching across the board on the bottom fromthe back. +5 V and +12 V reach across the boardfrom the front on top and bottom. The powerfingers on the bottom feed through to thecomponent side on the top.1600SIP'sThe +5 V supply is used for TTL/ECL conversions andD1CardCage.silFigure 2Card CageSideSideNormal MECL-10000 DIP's are connected to the groundplane and -5V supply. Logic nets are terminatedthrough 100-ohm resistors at one or both ends to the-2V supply. The resistors are in low-profile SIPs thatmount between the DIPs (144 8-pin SIPs per board).ContB (microstore)ContA (branching and tasking)+12 V x 10 A64k x 1 MOS Ram's64k x 1 MOS Ram's(100 ohm terminator resistors)7/11/85is halted. In the event some temperature exceeds 44 degreees C thehave temperature sensors that can be monitored when the Doradoare controlled by the baseboard microcomputer (Located on the BaseBoard)ProcH (Processor bits 0-7)ProcL (processor bits 8-15)DispM (Display color controller)MemX (Map and control)for TTL components. The +12 volts is used for the Ethernet box which is red the Dorado computer.-2 V x 150 A-5 V 300 A+5 V300 A+ 3)#t.%:1$&W0$%:0z@$%:0z$@%:P&$&WO-$%:O @$%:O $@FP&$GO-$FO @$FO $@F1$G0$F0z@$F0z$@#PJEtPJD.-O$3N$-M@$-M$8O$>N$8M$8M$/:O:WO-|I/:I0I9;I:I;I{$?WI{$@tI{$AI{$BI{$CI{$DI{$FI{$Et5{$DX5{$C;5{$B5{$A5{$?5{$>5{$=5{$<5{$;t5{$:W5{$9;5{$85{$75{$55{$45{$35{$25{$1s5{$0W5{$/:5{$.5{$-5{$+5{$*5{$)5{$(5{$'s5{$&W5{$(KJ1(J-!.Lf$/Lf$1sLf$9Lf$;tLf$=Lf$(G6(F (E-.(D.(B(AI*(@-,(?)(=,(<0(;,(:)(993?Wu$r#r !tAICAI30d4H7+2 : <:3e .8 +g5d$ +gd,-d!9 V@tu#t^C#_>#cuH @t > ] FI 8 :1 3e 2I32 4+G1,G 0rG 0G+0G+0rGH1,G4+Gd4Gs1,Gd0VGd0G+ PmeTo devices>SubTaskALU carryALU[15]FF[4:7]ALUFM8Task-Specific**ControlAddress Logic{ALUF}Q16Hardware ViewRSTK[0:3]oQAlua8X2XConstantFF0/-1AlubALUTIOA&StkPAluaAluaAlub16FFFF[5:7]2FF[6:7]IFUMemBAlubShifter16{ASEL}(FF}{BSEL}{FF}IOBALU lsh 1ALU rsh 1ALUFM{FF}{Shift mask}{LC}{LC}RF_ShC_WF_Cnt_BCnt_SCMemBX_SCMemBase_SCIFUJumpIFUJumpRBase_SCRSTK[1:3]StkpAlubShCo{FF}Md*RinTinMd*FF[4:7]16>>RTRTShCRTRT>>>>>>>>>dMd*dMd*AlubMd*>>>>>>>>>>>>>>>>>>>>CntStkpRBase>>>>>>>>>>>>MemBXMemRMSTKTIOA*A_SCB_const+>>>>>>>>16T*Base*FF[3:7]dMd*>>>Shift controlsMd*SHASHB{BSEL}{FF}Cnt'Pointers'RinTinT>>>>>>>>>>{FF}gh>>>>>>TQRQhgoProcessor16{BSEL}{Shift mask}MultiplyDivideCDivideQ lsh 1Q rsh 1A_Md1616Figure 35>To memory>16To memoryIOBIOABMux16>SubTaskTo/from Memory, Control, and IFU8>>denotes multiplexor latch>>denotes multiplexor>denotes register or memory>>odenotes multiplexor with inverted outputshgooQRTIdRisIdA_IdTisIdA_IdIddPddPddPd>>>>FF[4:7]2{FF}>B[12:15]RBase_BPointers_B>B[3:7]Pointers_BMemBase_BCarry20XorCarryXorSavedCarry0 or 1Mar'256 x 16256 x 16D1Processor.sil8/31/79Bfu" |* rtN*: 05W?$Y.Y $:Y$8$8$8$9<%$QC$3?$U3C$3Cr$3?r$3AE-$DX$e$ p9"$N9"$9&r$VP7?$U3t@tO-$9O$O$$O$S|$+L$M M_$M_ $M$O $9I{$3C;/^U$r,,$U, y$, $y9p--I$:t-!Vr =r$L$I$H$H$H_$D$D{$D{$T 9$VO-$tT- Br$>$r>^$>^$F$F$J$K&$F$rF$+WG$9)C9$*:E $+WC$9+WD+WK$&Lf/=(?*As4^r$s2r$+W3e$9s342/:3>r$79$39^$3p;9;tFI 7<%V$9b5r$bX9`r$9^r$`_b|$^$^$^$:` $V``$b5$bX1%7#$7$$8$$/_$0W`g.e`C$#`g/:bZ(u=DX?$Dt@-)O-*:PJ)1*:09;?9;A&$9;AI 9;B$9;B 9;D{$9;D<:{U$?9$ ?W7=6 D 7I8edn$=_$8e_n$8e_n$$ `r$ubX_`ZY. X$ ^u)c )bQ$P&$ Q+$QfO9BBr$t? >$@@d$VA$ G>$UV>^$V>^$y A&r$Bf/:=$ /:=$)AI$/::{$D$A$@P$#EP$#Am$&LBr$9;F&$9;?{$9;=$9;=7I1$7I3e6,0&Hr$&9^r$&7r$ :5W H ;-HQHPJZJ?@ $1$ |W UZ :tF :D :B :@tFm$#C$#?W$ ]$p_&t9&7&J&I ?$r*:|J=*:H*:F*:E=*:5*:4*:2Y*:0"s/tGf: d- 3e2|62: >6>8u>: >;>=v>? >@>Bv6,\6,^>6,_"sB"sA"s>K"s<0/e53+$"s1pYu@-Qf5| J5!6,/6,0:0 7I3r$8e5{U$:1 ^ \ [/\^(_n@$#H`CG$'s\)p_9bKF:W$e;t""suT!V1,p?W G@ d$ |9<9;= C E N! Lv:$Vt;-p:9`:_2Itc93e |6< 8u /Vuc8et5$eEt$eA] \1,41,2 2Ic$7Ia$39^r$ =G$ 8$ 8k$ 8$ ; +$ JG$ FI$r F&k$ F&$ H_$#RG$#O-$#O k$#O $Hd$,G$Gk$G$,Id$K#LG$#H$#Hk$#H$#J$; $=G$,:$9k$9$,;d$:W#:$%::|7Y9;6G$<2$;2k$;2$"s8.E=cQG$_$_nk$_n$a`$KmG$FP&$Q$"sF"sG"sLv"sN!:4$"s6+D{U$ tV 4G$ 2$ 1k$ 1$2 3B$(a$(_$._$3a$#<G$#9;$#9k$#9$:|:2 $U2 V$FFI!))X) )!&t",&#+$&%^+$+e$9&"r$& ]r$r-$&6 r$&6,#4^$#6PG$#2$#2lk$#2l$& &#&%$+"dG,sVG'N$, G.e|.e0Wp :0 $"rV Dt DX :$< GG:0W81s 3G99rG9GrGVJ-GHu'H&H%H$eH#H"sS rMG.Gd$0WtGf..$0W./:aG4;egG:dG"r =aG?a<$dAtbE|^>Bu_ F|R5UGd6tVBuTt AIp AI$,sdG?VC$DtVE|<4$<4$4te.u B$rtBVz$Vzk$$V3G$9|9$r$ dtH9|9V$V$r$Ar$ tH $,$$$$| tH9| 9 tVtV+$r$$r$VA$ )$9$>;"$+8(l$:|%J:%J=(l9$?W$$>;$G'T $'Um$'W$'Y $+WV$+WSX$+WtX+WTt-VfHG+XXG-UG+TG(HU(HY.(HWsJtuFEt8e7It<H<GA@->>>>>>>>>>>>>between R and T. When shift control istaken from ShC, ShC[2] = 1 selects T for SHAand ShC[3] = 1 selects T for SHB. When the>>The 32-bit quantity SHA..SHB is then left-shiftedshift 4, and shift 2 controls.through an 8-in multiplexor controlled by the shift 8,shift is FF-controlled, SHA and SHB are takenfrom BSEL as shown in the table below.BSEL.0=1BSEL.1BSEL.2when BSEL.0 is 1, and thesource for B is changed to Q.RF_ and WF_ are intended for use with "reasonable" values of P and S.undefinedPdthe Pd multiplexor when shifting. One ofexcept when BSEL.0 is 1 inD1Shifter.silFigure 4Shifter9/5/79stZJ 0WP0WR 0WK 9;S|$:R_$$VX p=)tY+[f$)Gf0WJ-0WT #Y.#PJ0WN)X:W|PZ:WPZ*:pS0WK$0WM$0WR_$7|P7P/:T$"sY @$#P&$(M_$(M_$/:M$ ([C$ :Vv :Vv7J=7J=W$Z& r$)tO#H5",.)FI(a`$/:^.$U(^ $(^ $y)p_0t`.0_+0^$0b,2C(2AI%2@-(2?'2=!2<\_U$ZU$[C$ [fWU$VCU$W_$ W9[C$9Z$9Z&$9Y$9Y $9X|$9W$9W_$VVf$Z$:X$U:YVY$TSRVB6A*Y$UJ$O-/4s44$5+W4346 ($$33B($91 11$1+1311($#030/^($#-*:-4--%($s++$++W+3+V0V-V+*($*^($3($$(+W((%($3(9;1$:W+$9;*@$:W.A$;t.9;*^$:W(H$99;(%@$;t(r1@$r+$r*$ .A$.e9-I;t, D@:Vp_ $t_ \ZXVf=R$=T $=U&$=VC$=W_$=X|$=Y$=Z$?Q$ 9;L$9L$9R_$?Vr$s-s00-|XWT=R'sUZ'sLv>O=>PZ>Qv>R>S>T>U>WtN'L,K+|VveT=tGf1E-FI6J-I&9((s((H$ (H$ V(H$ !(H$ )(H$ 0(H$ 8(H$ :W)A$;t';t&E*:0 AV2Bf);t-=u+ #r#r>uH_`TNIACIALinkJCNFFIFUAdQ[14]MIRTPCITPCOBNPCCIACIAIncLinkBLinkBMuxIMFFReadyBNTWakeupNextCTaskCTDTLinkAd>>>>rrCPStrbStartCycleStartCycleStartCycleSwitchT0T0T0T2T0SwitchT0T1T0TPCBypassPh3%4PErT0T2T3T2RSTK[2:3]rCBrRIMIMOutTPCAdT0T1T2T3T4T4T3T2T1T0T0T1T2T3T4T4T3T2T1T0T0T1T2T3T4T4T3T2T1T0T0T1T2T3T4CPRegUseCPRegRAPEncTLink*TPC*+1rrProcessorControlTPIMOutWriteT3WriteT3D1Control.silFigure 5Control Section9/5/796ttWAI^.=f^.:^.7I^.3^./:^.0[f$94;[f$97[f$9:[f$9>;[f$9A[f$98ed7aU$6tS7T-$6PJ-7Qr$<Gf$ 8eC9@$97VC$>;@$<9$;P8e:{0<7%$C7%$*3.9$9,$96",7 V$D $BB.M_ $.&$'s*:&$90+WsG."s $+,$9*,$9),$9(,$9.d<;U$A^.[f$9a'$$WrP& $yLrN$HWTtG :O 9$FIB$AV;-4/:$92$,s#H$7#H$*:*$9<>$99E-$9:_$97_$9>;_$UA_$9_$9X$rS$V6,$97Y.$9 V[Gs9$9$$M9$[C$]]|$@$@$J $K$G$9r[C$] 9]|]$ 9K$ 9K9$ 98e$r0z| 5  5 2;?D:FFJOQvQvUZVX!X! X!\0WX!3X!7X!:WX!=X!AX!A\=\:W\7\8b7U7P7M7H7D ;tD ==v9;=v;t;=;t6<;t.u;t"9;)u4)u2"7"7 71sX1st+t++ .")")'<()u))u*:)u+W)u.;.. WLvJ=&WKZ4KZ0)A$4%>G>$"s$-:;9s Q rI9AL W3S3J-4@-88e805Wd0WF %", T-7er$;td$7d$7d$@rW_$@9Mr$L$9L$9L$@Br$VA$A$A$@:<%r$;-$:; $:; $@)#%$.",$)"$$)"$@*:zr$.$*:]$*:]$@/zr$4;$/]$/]$@5W#%r$9",$5W"$5W"$@91r$>;0$90z$90z$@99^r$>;8e$98B$98B$@5WK&r$9J-$5WJ $5WJ $@5WN{$@5WT r$9S$5WR$5WR$@W$rX|r$:T$T$rJ-$7|'</: $9# y"s$6tGG8@tG9N$7KJ$U7Gf$?$s8e$2% G9.9$4;,sG,se$7e$2$5WOr$9;b$9;e$+W VG#.V$)%G 8rG,s$.9$0W$9.]$.$]-$0z$-$-$/:$97&$5W)r$9($5W($5W($5WN{$rW_$ :LGr@$uW5)$k5*$5*:$G:W)A$@5*^$5O$k5Or$:N$@9Nk$5O$k5P&$:WO $@:O k$7P&$7*^$]VIG;-4:W",$,$+9(k$:($@:)Ak$'s,sG0$?W$*-[C$]-|X!,t^.,s[:GAa9$>;c $W_$&u%(t((N+O $r   V  :   :   V :   # ( 0 ,s ( #  (,s05W9B>;95W09d>;dBdGdKd y$ G y$ y$+ y$+ ]$ ]$ ]$ @$ @$ ]$ @$ $$$ $$$ @$)e $$)e $- $- $$2I $2I$6$6 $;-$;-$?$?$D$H$F $[# $!V*%u+;tt<VQf6 (6tNV0$<&$ ;-30)e$"s1 $<5$;t|2|,sz$+X % $t, :H9;h $sW$W$X|r$5W,$93&$ *^",<1$8uM;8L8's8&W@t $rr"AurH_g110001000BRANCH CONDITIONALU = 0ALU < 0FUNCTIONSubroutine ReturnunusedRead TPCWriteTPCunusedunusedGlobal CallLong Jump/CallR is resultTNIA:01234567JCNADDRESS BITSADDRESS BITSADDRESS BITS01111Return001111BRANCHCONDITIONADDRESS BITSRETURNFUNCTIONNUMBERNEXTRead Instruction MemoryWrite Instruction MemoryIFU JumpLocal Jump/CallNext Address FormationJCN[5:7]0123456JCN[2:4]0123456Conditional BranchReturnRSTK[2:3]0123RSTK.0RSTK.1RSTK.2RSTK.3ALUF.0ALUF.1ALUF.2ALUF.3BSEL.0Par.16BSEL.1BSEL.2LC.0LC.1LC.2ASEL.0ASEL.1ASEL.2BLOCKFF.0FF.1FF.2FF.3FF.4FF.5FF.6FF.7Par.17JCN.0JCN.1JCN.2JCN.3JCN.4JCN.5JCN.6JCN.77when B_Link executed infollowing microinstruction.ConditionalJump/Callotherwise, it is a jump.before any modification of TNIA by branchA long, local, or conditional branch is a call iff,write the right half.Good (odd) parity is writtenif RSTK.1 is 0, else bad (even)parity is written.The most significant bit ofdata is RSTK.2 and the leastsignificant 16 bits are B[0:15].JCN.7JCN.6JCN.5JCN.4JCN.3JCN.2JCN.1JCN.0FF.0FF.1FF.2FF.3FF.4FF.5FF.6FF.7BLOCKRSTK.0RSTK.1RSTK.2RSTK.3ALUF.0ALUF.1ALUF.2ALUF.3BSEL.0BSEL.1BSEL.2LC.0LC.1LC.2ASEL.0ASEL.1ASEL.2RSTK.2B.0B.1B.2B.3B.4B.5B.6B.7B.8B.9B.10B.11B.12B.13B.14B.15Data appears on B[7:15]Cnt=0&-1 (decrement Cnt after testing)R < 0R odd-or-FF6061626364656667--Address is in Link.Address is in Link.Figure 6Carry'IOAtten' (non-emulator) -or- Reschedule (emulator)RSTK.3 is 1 to writethe left half of IM, 0 to0001x111undefined234567891011121314151514131211109876543223456789101112131415151413121110987654322345678910111213141515141312111098765432CIA[2:3]CIA[2:3]CIA[2:3]Link[2:15]CIA[2:9]JCN[2:7]JCN[2:7]000000FF[0:7]JCN[4:7]CIA[2:9]RJCN[3:4]0JCN[1:2]JCN[3:4]InstrAddr[4:13]15141312111098765432CIA[10:15] + 1CIA[2:9]Loaded into Link by Call, Return, or IFUJumpconditions or dispatches, TNIA[12:15] is 0;# 000xD1Branching.sil# 1116/26/80Overflow_ZUP_ZUVU Uu=ft;:u.rt-Ir,,r(r'r+r)pZ UFuPJ *pabXbXVbX bX bXbX9bXrbXaG d_ Z uUJ pKKK9KrKKFFVFrF9FFuPJO- PJ VKVJ FI Gfrt&rpF_rVu=f t; : 9 8e 7I 6, 5Vu. t-I ,, + ) ( ' &u?1,', :t$ :", :e :'s#$+#$0W#$4#$9;#$=#$B#$F#$#&z($K$e$9#$A(%$#$A$]#$($,s$0$5W$9$>;$B$G$#!z$]#!z(%$K!$9##($F!$B!$=!$9;!$4!$0W!$+!$'s!$'sH$+H$0WH$4H$9;H$=H$BH$FH$# ($K$9#(%$#$]#$]#(%$K$9#%($F$B$=$9;$4$0W$#",(",,s",1s",5",:W",>;",B",G",#e(e-e1se5e:We>eC;eH;e#(-1s5:W>C;G ! pP N *t?*A)*B3!H!+!5H5+5  $  $ $ $s $ $!V $% $9 $]Jt F A = 8 4; / * . $3 $7 $< $@t $D $IX $M $9*: $9$K$9 K$9K$9$K$*:$M$9IX$D$@t$<$7$3$.$9$]%$!V$$s$$$ $$  9     "s &  9 s!&W*/:4;8=AEtI 9#'s+0W4;8=AFJt#'s$+$8e&7I6, u=f9=f9t;9:9998e97I96,9593 r3$d$rt952H+pBBB B VBB9BrBB %:`$DX^$9%:^A$%:^$]'s^$+^$.^$0W^$2^$4^$DX^$B^$?^$=^$;t^$9;^$&Wt](]*]-]/:]1s]3]5]7]9]<]>;]@t]B]BX@tX>;X<X9X7X5X3X1sX/:X-X*X(X&WX9;Y$;tY$=Y$?Y$BY$DXY$4Y$2Y$0WY$.Y$+Y$'sY$%:Y$]%:YA$DXY$9%:[$%:V$DXT$9%:TA$%:T$]'sT$+T$.T$0WT$2T$4T$DXT$BT$?T$=T$9;T$7T$&WS(S*S-S/:S1sS3S5S7S9S<S>;S@tSBSBN@tN>;N<N9N7N5N3N1sN/:N-N*N(N&WN9;PJ$?PJ$DXPJ$4PJ$2PJ$0WPJ$.PJ$+PJ$'sPJ$%:P&$]%:P&A$DXPJ$9%:R_$%:M_$DXKJ$9%:K&A$%:K&$]'sKJ$)KJ$+KJ$.KJ$0WKJ$2KJ$4KJ$DXKJ$BKJ$?KJ$=KJ$;tKJ$9;KJ$7KJ$&WI(I*I-I/:I1sI3I5I7I9I<I>;I@tIBIBE-@tE->;E-<E-9E-7E-5E-3E-1sE-/:E--E-*E-(E-&WE-7F$9;F$;tF$=F$BF$DXF$4F$2F$0WF$.F$+F$'sF$%:F$]%:FA$DXF$9%:H$)Y$9)T$9)F$9%ZJ%UJ%Gf2IK )^$7^$9,s_J;t_J7Y$9.ZJ7ZJ:ZJZJ@ZJBZJ;tT$90UJ=fUJ)PJ$7PJ$9-P;tP&9$BPJ$9;tPJ$9=PJ$9BP=P+$@+$B+$E-+$5+$3e+$1,+$.+$,+$*+$(H+$&+$]&+A$E-+$9&-$7+$97+$:,s,,s&p.,*t@+9uO-9N:9t3X99Kc. %t2t1dt1ct1bt1at1t0t2t1dt1ct1bt1at1t0t4t3t2t1t0t4t3t2t1t0Phase 0Phase 0Phase 4Phase 3Phase 2Phase 1Phase 0Phase 4Phase 3Phase 2Phase 1Phase 0CTD_CTASKWRITE TLINKMIR LoadedqqqqMIR LoadedCTD_CTASKCTD_CTASKMIR LoadedMIR LoadedMIR LoadedqqqReturn:qMIR LoadedMIR LoadedqqMIR LoadedMIR LoadedqqqqqqqNormal:StartCyclePhase 0StartCycleStartCyclePhase 0StartCycleCIAInc_CIA+1CTD_CTASKCIAInc_CIA+1StartCycleLINK_CIAIncStartCycleCIAInc_CIA+1LINK_CIAIncLINK_CIAIncCTD_CTASKLink clobbered.LINK_CIAIncCIAInc_CIA+1StartCycleqqMIR LoadedqqqMIR LoadedWRITE TLINKCTD_CTASKPhase 0Phase 1Phase 2Phase 3Phase 4t0t1t1at1bt1ct1dt2CTD_BMux[12:15]qt2t1dt1ct1bt1at1t0Phase 4Phase 3Phase 2Phase 1Phase 0CTD_CTASKWRITE TLINKMIR LoadedqqqMIR LoadedqqStartCycleCIAInc_CIA+1LINK_CIAIncTPCI_TNIA (Link)Write TPCClear TLinkXqqRSTK[1]=0->odd1->evenparityTPIMO_IMTPIM Mux _ IMTPIM Mux _ TPCRSTK[3]=0->right half1->left halfD1InstTiming.silFigure 7Instruction Timing10/8/79Read RMALU operaionWrite RM<><><>Calculate next address<>Fetch next instructiont-1t-2qMIR LoadedFetch Instructionq<>Write IM:Read IM:Read TPC:Write TPC:B[12:15] = address (task number). Data from Link. Link clobberedB[12:15] = address (task number). Data to BLink. Data available on B next cycle ONLYLink = address, RSTK[2:3] = 9-bit byte, data to BLink. Data available on B next cycle ONLY. Link clobbered.Link = address, RSTK[2],,B[0:15] = data,Fetch next instructionLink _ CIAIncWrite TLinkFetch next instructionWrite strobeFetch next instructionFetch next instructionFetch next instructionLink_CIAIncTPIMO_TPCWrite TLinkLink_CIAIncCTD_CTASKCTD_CTASKModify address by b.c.Link_CIAIncCTD_B[12:15]?t575.5%:5V5r5 5?E-7E-.E-%:E-VE-rE- E-.UJ%:UJVUJrUJ UJ?c.7c..c.%:c.Vc.`R@$R $ S/C&CCC C/3&333 3.1$.,,$U..A$B,, @t1,$9@t.$@t.e$IX.e$A. B+ @t+z$?|)u@t+$9?/3;t$@t3$?>@t;-$9?9@t; $Bt: IX=$@t=$@t>^$@t@$9B; @tC$C_?W$KJ `$%`$.`$7`$@t`$X 0X BX 7]$7^d$#^$^$%^.$@tY $@tY $]?|W.WY $VWY.$9.Y.$9.Y $.S$%S$S$S$ S$R5W$ C$C$C$%C$.C$7C$73$.3$%3$3$3$ 3$rpUPJ$9PJ$9M$M$%M$ N$9 |K M$ VtM V; <%$ |:  r/ :@-$ :@ $+@ $.;=.=f$9.=$9WIX$9IIX$9:4IX$(lIX$ K$93IX$9WIX$9J IX$9:{IX$9(IX$9zIX$./%, $%,$ KJ$rpb&t` 0W`8` S S&S VO- 0Y @t]$V? 8C -; 83 V0 +/ ?W0 BY ?Gf?WH V 8", .|<r<$ Vtd $ | $9 ",$",$",$%",$.",$7",$@t",$";t$?<@t$9?@t$BtH A, IX$@t$@t$@te$9Bd .z$.$ ",",",&",/", #r#V#%:#.#7#?#!V.]$7$7|<7$7 d$. @$?Wt+6t+-+$+++ +/:&Ws 9. $B ? $? +$rH +$A B ?@$?W|;?d$9?W V];t$?$7$.$%:$V$r$ $ G$9  $$ t rH$| - 8t + >;+ *:+.$r1s d 0 $| %:H$%$%:<.$r.H$?H$2tGf8G8F:WE+0%+ /:#Gf)eFG98eFG9)G )F <u#rr =ut^.+W^. 9^.|Z$Z%Z%^G$2^r$6tZ>^$7Z?WZt\\$,s\9$|X-Xt[f`$ `$ r`9;$rc. c. Y.$9 |W Y $ VtX [$.[$9 [$+^.r|Y ^$s^r$\$d ZZrpG r7r%  tB %V 7m 9Gf( 9KO- N /="s@- /.e// ++ 6t A> ?W? Y VY [*:  !+ h9IbXMemBase *Md *Time from0Time fromAddressingCache dataMain storage16<1582Ad><<SINSOUTFIN77 rows x 4 col6..2121..27Real page Flags64K x 19282816816187tb !Vua< KtaHueg 5pe e 9e Gc.G*dVG*bGd 9GbG.et_J-Z&$7I\9$7|Y>0WD$VCO$DtOt5N$/F&$4S$/U&$3>^$4;/$+=$'s=r$(% $ Ve$ V ]$ d* +3$<=-I_$!V$y$"sH_$;->^$+W>^$_$"s_$)1$#GB$+W/-|+ rt $$r$ H$]$ |; 8eO's5 's: $u!Vt'<9&Wu(.u/@t9t.u.u"sAY :AY"sH#Km$#D{$!H$!tb!|]V1$ $$9(tVV $D{r$ y$($"V$$%y$( -%$$%$&"$7 !$!!>$ r rs V,- b!J-)e ! *$9*$9! )e V& : :;V&%:&W/'s8k$;8$=?{$:A/@-*?{$5W?{$/:ABA$UAI?{$]AI?{y$D?$9AIAU$;D$9?{$9?{$9Cr$A@-:@-^ $'s5$5{ $5{$  D$GB$!J $$J-$d!Km$ rH$r $ ]$+$ 9$$ e$9A$$U@$$y9!z$ !$9, $y9, @$ V,,$U9/^$ /$ 0z$1$/:1r$]5t>;.&$&z$1s0$-0z$.>^$0>^$*?{ $-|,"&W)A$'s<%]$'s:{ $$'s6's8ut_J#_#G"sH-/^d$Gf/^$)>Y $>V$9=|S!V4^$"st3+W"$*|u*)A$+t($r$*^V$ ]$! G$9*: G$9 G$9|tst!Vt%t)ttV9;]$8_$:W_J7[$9!V&V4=f2I>2I=f/:>/:=f,s>,s=f4>K\JCJt4;I&F@?W  +  +3Iu,sC,sCtHIXHu` dGsbGbG(bG! $0t[ HudJ !J $B #r+&V3B $3B$]V4^$Bu9'st(! $8 # $V|t3 8;tQ3L3Q$* **&.1sE1sT$-k$V$ $ V,,,$3]KdFigure 945678910111213141516171819202122232425262728293031VAxxxStored in address section<>Row><4k-wordCacheMunchWord in256-wordPagexxxxxxxxC2C3C4C5C6C7C8R2R3R4R5R6R7R8Word in pageC1R1C0R0xxCache, Map, and Storage Addressing<><>Map Addressing101112131415RPRPRPRPRPRP24252627VAVAVAVA00010203040506070809RPRPRPRPRPRPRPRPRPRPReal page from Map>ColStorage Addressing3130292827262524232221201918171615141312111098765445678910111213141516171819202122232425262728293031VABRMar4567891011121314150123Mar + BR = VAStorage size3210151413121110987654MarBRVA3130292827262524232221201918171615141312111098765445678910111213141516171819202122232425262728293031Virtual AddressingBmux,,Mar + BR = VA456789101112131415Bmux,,MarBmux(long Fetch)(Normal Fetch)765423VNVsAd.0-sAd.7CacheA AddressingCache4k-wordVA31302928272625242322212019181716151413121110987654CacheD Addressing4567891011121323Dad.0-Dad.13 (Bits 2 and 3 not used)Dad.0 and Dad.1 are made up from Hit or Victim.Dad.0-Dad.13103287654104567823xxMapAd.0-MapAd.8#r@?$@->;$>?4$>$%:>;$'s>;$)>;$+>;$4>;$2>;$0W>;$.>;$=>;$;>;$9>;$7I>;$r>;$>;$>;$>;$#>;$ >;$>;$V>;$ G>;$ >;$>;$>;$>;$>;$>;$t>r>>> > V>H>>>>s>>>>!V>#>%>(>*:>,s>.e>0>2>5>7>:>>>Bp>8B?$+8e$48e$28e$0W8e$.8e$=8e$;8e$98e$8e$8e$8e$97I8e$9t8r88's8e$%:8e$r8e$8e$8e$8e$#8e$ 8e$8e$V8e$ G8e$ 8e$8e$8e$8e$9)8e$99V9 +$|6< 9$$6<-ts-,$,$ #%:'s)+,$+,$rV2  ss,$9,$ r,$ ,$+r" r 9$ r|f,sf,sVp(@-8e$9r2$(Ht*-I/2I4(H*-I/2I47I97I9HHHH #H%HHHH #H% $',H$5W|XrXC;pC;t ! & # ( + - 0 5 2 ? < : 7 7 : < ? 2 5 0 - + ( # & !   H H        H    + 9r$r$:r$r$r$$r$'sr$)r$.r$1sr$3r$8r$;tr$=r$$-$ r$sr$s+$"s+$,s+$rH  $6,$Bfp$=t%:;%:9%:7I%:4%:2I%:0%:-%:+%:)%:'s%:%:%:#%: %:%:%:%:%:d%:r%:%:%: %: %:V%:%:%:d%:$$G$$$$d$$+$$ $$ $$$$$$ :$$"s$$$$V$$$$$$6$$8$$;-$$=f$$-$$/$$2$$4;$$+W$$)$$&$$$$$$$$?4$?$$'?$r2$r$@t$rV$6tV$6tr$AuG 0t 0W 0WpR $$Au+%:|6<(6<%:9$(H9d$&t9%:9$p>tFIJtNX$ NX$#NX$7INX$9NX$;NX$=NX$.NX$0WNX$2NX$4NX$+NX$)NX$'sNX$%:NX$@-NX$ApFAIAIN%tN(HN*N,N.N1,N3N5WN7N9NNsNeN!N#NVNX$VN4#$VP#$pR t  Va#$V^#$V^$#_J!_Je_Js_J>_JtZV pdda]$^$^$^$r^$^$^$^$V^$ G^$ ^$^$^$^$^$^$t_Jr_J_J_J _J V_JH_J_J_J_Js_J_JAIp_J Ga%:9$%:9$2e 0R5t83e81,8.8*:8,s8&W;,s: pA@--$9B,B.%:-$'s-$7I-$9-$;-$=-$.-$0W-$2-$4-$+-$B1>t2;.&W.(..$%:,:$%:-$%:-$-I/./ #%-$- $ -%$$ $& $) $+W $- $ $ $V $ $"s $ : $ $ $ $ $+ $d $ $G $ $ $ !V! !!,,!)!'!%!#! !!r!!+!d!!!9!!!!V$.!+K&bX(BusyRefMapTestSyndrome is xor'ed with the checkbits on storage writes>VA[4:15]EmuProcSRN[0:3]<><><>B_Pipe5(B_PRef)Trouble'MemError'ECFault'Bit in word<>Word code'>dVA_VicFDMissUseMcrVDisHoldReportSE'NoWakedVA_Vic = put contents of cache address memory addressed by row of last reference and columnof Victim into Pipe0 and Pipe1>1514131211109876543210VA[16:31]<1514131211109876543210<>>><<1514131211109876543210Real page no. (RP)<>15141312111098765432101514131211109876543210WP15141312111098765432101514131211109876543210--------------WP------1514131211109876543210LoadTestSyndrome1514131211109876543210LoadMcr--1514131211109876543210Emu><<>MapTroubleMemErrorEcFaulttruefalsexPage faulttruetruexMap parity errorfalsefalsefalseNo errorfalsetruexUncorrectable error (DE)falsefalsetrueCorrectable error (SE)ReportSE' = when true, wakeup fault task on correctable errors (SE's), provided NoWake is falseWord CodeDisHold = prevent hold from occurringNoRef = prevent storage references011101110111Meaningword 0word 1word 2word 3otheruncorrectableChip SizeMapDirtybMapParityM0, M1, M2, or M3 indicates that a storage boardpair is plugged into slot 0, 1, 2, or 3.Chip Size0 = 4kx1 ic's1 = 16kx1 ic's2 = 64kx1 ic's3 = 256kx1 ic'sTaskD1MemReg.silFigure 10The Pipe and Other Memory RegistersReverseda1111Pipe5[0:7] are in the Pipe, Pipe5[8:15] are values read from cache address section during last ref.CFlags_A'ProcTag6/26/80t;tH+I";,,|" " &3 $t% HdH;t<H 'A:5W6,5W25W.5WA%=%:%6,%2%!<;t<X-I d? Et+H+8*8+0+-+Q+b-)[Y eC>;$Lc.$9 c >^$ c $]b$%:b$4b$b$b$!Vb$)b$-b$0b$8b$@tb$DXb$H;b$araVa:aa#a&a*a.a2a6,a:a=aAaEaIaV#R?WX-XE%I%XUVU VR<+<VTtA&< ';t<p_J]dbrLf VtSX29]=< -<1,<9;<8;tF<5"s&3 $-%2"s5W s5r$(5r$( ]$s ]r$"s -Jt$LJt$rpOWrIr5 U 9 rG rN&WtH 2Y.3 3X 3 d s|`wK`wd'r$2tc7Id'$-Y.5W +5U$H5$ |2V2s2+2 H ]$+ ]U$Vst +|rp<r:tGHIG"I!G1G -H+$7Hr$-|E=;tE=?WtH ^$L^u$9 `>;$*_ _n$0_n$ |[^$ Z&>;$LX$9sY $&WY d$s|UZ+UZ0Y $:WY $^$LNX$9 Pm>;$'sN OQH$2OQ$ |KKK^$LG$ J >;$<:$s:$I:E:A:=:::6,:2:.:*:&:#::::V:r::H;:$DX:$@t:$8:$0:$-:$):$!V:$:$:$4:$%::$:$ ;P$] ;P>^$L;t$9 =>;$6,<<4;$s4;$I3eE3eA3e=3e:3e6,3e23e.3e*3e&3e#3e3e:3eV3er3e3eH;4;$DX4;$@t4;$84;$04;$-4;$)4;$!V4;$4;$4;$44;$%:4;$4;$ 4$] 4>^$L4$9 6>;$<)$s)$I)E)A)=):)6,)2).)*)&)#)):)V)r))H;)$DX)$@t)$8)$d0)$-)$))$!V)$)$)$4)$%:)$)$ *^$] *^>^$L*$9 ,>;$+++++"+&+*:+5+IX+AI+=+<$$s$$I#E#A#=#:#6,#2#.#*#&####:#V#r##H;$$DX$$@t$$8$$0$$-$$)$$!V$$$$$$4$$%:$$$$ %$] %>^$L%:$9 'O>;$rp&r$e<$s$It,E,A,=,:,6,,2,.,*,&,#,,:,V,r,,H;$DX$@t$8$0$-$)$!V$$$4$%:$$ l$] l>^$L$9 >;$+p=t< $s $I E A = : 6, 2 . * & #  : V r  H; $DX $@t $8 $0 $- $) $!V $ $ $4 $%: $ $ @$] @>^$L d$9 y>;$- 0 ]9$: ]$;|0< ]$I ]9$<KuEt Et :Et+tDD!D%D +BB!B%B+AA A%A+@@!@%@+?? ?%?d_8uE- t%"9C9B9A9@t?uE-?tC?B?A?@t9;?W??W =5W E-5D4I5H4200(1s2 7I2 7I07I/7I.#XBu "sr H+#2tIhcrcVc:c8cp+W t<;tDXu JLfg 00010203040506070809101112131415WORD0DROW1514131211100908070605040302010000010203040506070809101112131415WORDDROW1514131211100908070605040302010012301234567xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx007206106307046247147346026227127326067266166367013212112313052253153352032233133332073272172373015214114315054255155354034235135334075474174375016217117316057256156357037136236337076277177376Check bits are EXOR ofdata bits marked xand number ofones inSyndrome isandfurthermoreTHEN0ALWAYSALWAYSNO ERRORNot 0ODDsyndrome bitsSINGLE ERROR (data bit)Bits 4,5,6 give bad word:4 5 6word0 1 11 0 11 1 01 1 101230 0 0 00 0 0 11 1 1 01 1 1 1...Bits 3,2,1,0 give bad bit:3 2 1 0bit00011415...Bad bit will be corrected iferror correction is enabledNot 0ODDin SyndromeSINGLE ERROR (check bit)Syndromebad check bit20010004002001000400200176543210Not 0ODDsyndrome bits4,5,6 have 0or 1 ones onTRIPLE ERROR!!(but no data bits will be changed)Not 0EVENALWAYSDOUBLE ERRORNo data bits will be changed.Syndrome is nonsense.Syndrome is nonsense.No data bits will be changed.4,5,6 have 2or 3 ones onexactly 1 oneInterpretation of SYNDROMEcomputed check bitsTestSyndromemessy EXORnetwork>Quad-wordin Cache>>r(usually zero)>>Quad-wordin storagecheck bitsnetworkEXORmessy >computed check bitsr>>>SYNDROME>qin CacheQuad-word>EnableqPipe 4rrin storage/4x1688other stuffErrorCorrectorcdeffedcSYNDROMEfor errorin bitIfSYNDROMEisD1ErrCorr.sil9/5/79Figure 11Error CorrectiontQPONMLfKJJ-IGFEDCBfAIpNXLKIXFrSXGr@Gr@tGr,,Gr,sGr?G568e:t-./:0W1s2345789;:W;t<=)e(H',&$#"! eH,p%$"s r*Gr+GrGrGrGrG +tr   9 Vrp1s +RV$r$NQV$PV$OV$N{V$M_V$LBV$K&V$J V$HV$GV$FV$EV$D{V$C_V$BBV$A&V$,V$-V$/V$03V$1PV$2lV$3V$4V$5V$6V$7V$9V$:4V$;PV$V$*^V$)AV$(%V$'V$%V$$V$#V$"V$!zV$ ]V$AV$%V$V$V$V$V$V$NV$kV$V$V$V$ V$ V$ V$ 2V$OV$kV$V$V$V$V$V$V$ SX SX VSXSXSXVSXSXSX tP N Lf J- G E C AI - /: 1s 3 5 8 :W < (H & # ! e ,   r    V    O N KJ J- F E Bf AI - . 1s 2 5 7 :W ;t ', & " ! H ,   r    V r   r$P VLf VM VKJ VJ- VAI VBf VD VC V/: V0W V. V- V5 V7 V9; V8 V# V$ V" V! V V V V V V V Vr V V Vr V VGIFEAIBfDC/:0W.-1s243e H,r  9 3421s-.0W/:89;75:W;t=<(H)e',&!"$#,H e  9 rr VVeV VHV,VVVVV#V$V"V!V&V',V)eV(HVVVVV VVrVVVVVVrVV V 9V VGVIVFVEVAIVBfVDVCVLfVMVKJVJ-VNVOVQVPr$PPQONJ-KJMLfCDBfAIEFIG3421s-.0W/:89;75:W;t=< Vrr  9 QNLfKJGFDAI-0W2378:W=)e&#"eH V 9 rr$Pr$PQPONMLfKJJ-IGFEDCBfAI=<;t:W9;8754321s0W/:.-)e(H',&$#"! eH,r V 9  r rU& V$ S$9rS$9S$9rS$9S$9 V U!?-G(Bf (AI(@- 0AI0@- B@-$=)=2=:=!=B-$#;-*;-0;- :;-:9=7A7=6,=5=3=2B6,B5B3B2A2$=7$=-=,=)e=(H?Wp+?W+W?W*B(H$V:t1,=/B/B-B,B)eB(HC;p+C;+WC;*=/^$!$-$:t&:%#"*"0! :"=!DX! C$ >e>H>,>>>>>GGGGGG,GHGe!A-$#+*+1s+ 1s 1s :+:"!A-$#+*+3+:+ : : :'s d$80W d$89 dG8! d$8! @-$N @$8B!C_-$:0: 08 0" +pDXrZJ$rVZ&$9]| $V[$9[ @$9[$t[9^ $9^ @$V^.$9_ $^. r] r[ rZ|Y>Vd'$r`$UV`@$V`$ytb aV^$VZ&$r\$|Y>[v ^$9 [vVu_&[$&[$-[$ &d$rc s$%|ZZ%_Z&_'$'stb 's` 's] 2`C$2d$3`3b3c.2`C$8`g$r-c r$0|_Z0t\0W\_$0W\_ @$;t\$0W^ $4^.$94;|Z4Y.$U4Y $-^ $/:V$9/:VV$6,UZ6,S!=d9$DXa$U=a`]$=a`$y/:c $/:e $9c.$9c U$<_Z=Y $GW$=W_ $$=W_$@ttWBY $y<|T=?W]!H;tbH;c. Ga`$yGa`]$NXa$UGd9$F|_Z?^.$U>;t]B|]!9P $GN$99N{$9N{$]>tO-BP$B|M;c.>;b = V$ :|[v :[v[v[v7UZ7UZ7UZ7UZ#^ $$]$:WWU$;W$tUTt SX$Bf!AI$@->u @t!rG LBe ~Instruction Fetch Unit OrganizationBMux.0..15Jump displacementPcJpAdder>>>>>>baiiWantIfuRef'pTo memory>>>Jump displacement H if LengthK=2; SignK extends H.0=BMux.0..15ToProcessor=SignK supplies top 11 bitsTwoAlphaK..NK if LengthK=1;PC PipelineTypeJumpMSignMLengthMIfuRBaseSel'MemBMTypePauseK'TypeJumpK'TwoAlphaMTwoAlphaKMemBKRBaseSelK'LengthK'SignKNKNMSignXLengthXNXTwoAlphaXJHIfuAddr'InstrAddrK'FGpp918{GDv'}{PcFG.15}FGefcdFGParityErrBrkInsTestH8>>>>>>>>>>t1t0t0,t1t0t0t0t1t3t1t0,t1efcddcfeefcdRamParityErrMemoryTo IFUFGAlphaMCache>InsSet28igh>To control section>>To processor sectionTo processor section2311418SectionPCX'Junk'IFUMRH'IFUMLH'M-LevelX-LevelK-LevelTrapAddr'101TrapConditionTrapAddressF>RamParity.0other bitsother bitsother bitsRamParity.1RamParity.2IFUM1024 wordsRamParityErrInsSet..74Not ReadyInsSet..34RescheduleInsSet..14FGParityErrInsSet..04K FaultInsSet..00Lowest priorityHighest prioritypIfuFaultTo IFUhgId.signghId.0..3Alpha/Betat0AlphaX.0..3AlphaX.4..7t0Id.4..7pppToProcessorSection15Mar.1..15'16PcFPcFGPcJPcMPcX>>>>>>>>>>>>>>>>>>>>>>>x 27 bitsD1IFU.silFigure 129/5/79rr#t] +\+Z\ $Z 9$Et|U]|+$ZJ$UZ&N$Z&$ydt[f[$[$U\$`C+$#]$]|N$]|$YQ$YQN$#Yu$\+$Z$+^$Z$|[/WX!YXW+]!+]!+[/#^9$+\$`$$et` -_$5|\9u_J %|W&\+$*Yu$&YQN$&YQ$#Z$-IYQ$-IYQN$1sYu$-I\+$,,W*Z$2W3\+$8Yu$3YQN$3YQ$1sZ$+tc.a!G`8Zd$>U$?WX >X$AuW<?WV Gta_`8e;P$?9$8e9$8e9$8e6$8e6$?7$8e8$ pU .t,s 01s07I.& 0W)"/ "- /:4; "4 "*:"'s "7"2I":1s::W1s:7I;t:9;4; .e2$51,$.e1 $.e1 $.e6$.e6$57$.e8$.e(%$5&$.e&z$.e)A$.e)A$5)e$.e*$.e$$5#H$.e#%$.e5{$53$.e9$.e9$59$.e;P$.e-$5,,$.e, $.e, $8e1 $8e1 $?1,$8e2$?3$8e5{$7%+$5$94N$4$]<%$]<%N$^+$VL$ L$Hp5WH< N9$ L9$ E9$ G9$ E$]VE$9M;$GM$GNX$GG$GF$GF$G0t#"$ dL$dK$ K$ J$dG$dH$ G$ I$dG$ pM; FdJQG$|FG2I$tKO-$+PuFD t6 G/$ G03$ G0z$ G0$ G1 $ G1P$ G1$ G1$ G2%$ |.u .u .u .u G0$t1, 6$ +:{r$ +3 :X(HX.X5X!`g=fM;HF*3$*z$*$*$*O$*$*$*%$*l$,|,-I-I-I-I,,*$*A$*$*$*k$*$$*$*$*O$*k$*$*$*A$*$*$*$*]$*$,,-I-I0O$0k$0$1,$1,kV$2It UT-:GBGUBGUBG 9pQuItJt 5$.e$0W<8e>$8eA>$A>$?=Br$?:{$A:{$A;$?7$B7$B:{$DX9$DX<$Et<IX|<IX9IX..Fu8D7 D5%:^u$$t_J._ $ZJ$$e[f p^. :Z'Z.Z5Z9YQ$9W$9V$=|W=U=T==R-I9-I6-I4-I0-I..-I).-I&g-I#-I JC;9C;:C;8.C;67I47I67I07I..;t +G7I97I<]|$1 9$:t' ?Wu !r ?WudC9dJ b MEMORYSYSTEM//ISJ-LEVEL2 BITSM LEVELX LEVELPCFGPCMPCXPCJIFU DATATO BYTEPOINTSTO WORDOP AT JOP AT MOP AT XNKH181+1+1+1PCFPOINTSTO BMUX16 BITSHDVMDVBRKINSTESTIFUBMUXIFUBMUX16 BITS8 BITS + SIGN EXTENDNXILXINSTRUCTION SETIS.0ADDERBMUXBMUXENABLE16 BITS16 BITS16 BITSINSTRADDR10 BITSRAMPARITY3 BITSM LEVELILNMEMB01342MXSIGNRBASESELTYPATYJMPM LEVELK LEVELMEM FAULTTO IFUMAR16 BITSVALID RAM = JDV + NO PROBLEMSKREADY = FOR AN _IFU DATA THE FOLLOWING THINGS WILL COME OUT OF THE IFU ON IFU DATA:DURING A JUMP YOU WILL ONLY GET INSTRUCTION LENGTH FOR AN _ ID.JDV + LENGTH = 1JDV + HDV + LENGTH = 2JDV + HDV + FGDV + LENGTH = 3KREADY = KREADY = JDVEXECPTIONADDRESSPROCESSORRAM OUTPUT27 BIT/1K RAMFDVFGDVKREADY0:30:1ALPHA 0:7ALPHA 0:3F-BYTE 0:7G-BYTE 0:7F-BYTE 8:15G-BYTE 8:15TO CONTROLPageDateRevDesignerProjectFileXEROX1CSLVESTDORADOIFU BLOCK DIAGRAMIFUBLOCKDIAGRAM.SIL1. ENCODED CONSTANT (N)2. 3. BETA4. INSTRUCTION LENGTH0:30:10:9N= 17 MEANS THAT THERE IS NO CONSTANTIF YOU DO SEVERAL _IFU DATA'S YOU WILL EVEUTALLY ONLY GET THE INSTRUCTION LENGTH(COULD BE TWO FOUR BIT QUANTITIES IF 2ALPHA BIT SET)FG 0:7 + PARITYPCFG.15GDV'S1S28 BITS + PARITY"H" LOADSAT T1X0X1X2X3GDVIFU DATA GOES TO THE PROCESSOR AND ALSO TO THE MEMORY SYSTEMPCFG.15IS.0XOR WITHPCFG.15"J" LOADS AT T0D5-14-82tZYsM_LBI V$$G$9G y$G$]G$9VH_ J sJ $HKJG$A$A$$7H$$A4$U4^k$4^$y5]-%$y]-% r$$-I$U]0z r$%.e $$(%0z9$/^-I$U(%-%]$(%-%$y(%4^$y(%4^]$/^4$U(%79$ 0$+z0$(G9$/:D{$U(DX]$(DX$ysOt $+WH$+W7$ &C;$&C;$]K&$8Yu$y8Yu $BY$U8\ $BP$U8P$y8eDX$y8eDX k$BD{$U8eG G$8B7 $B4$U8B4^ $8B4^$y8B-%$y8B-% $B-I$U8B0z $9;Q9^59^.e9;E+z',$"' $"$e$=QC<[C$$B>^B@GC;JAd$LA$CR< +$LR<$ B[ $;_$>;]5$9;ZCI$C;V$BSX$=R_:{&:$&R_$$&R$$&R$$&S4$$&S$$&R$$&zR$$F&BB$$FIBf$$FmB$$FB$$FmB$$FIB$$F&C$$"s#$$"O"$$","$$""$$!"s$$!"O$$!",$$+1 $$+0$$+0$$+z0$$+W0$$+30$$+1 $$+8B$$+8$$+z7$$+W7$$+37$$+8$$*8B$$+H;$$+H$$+zG$$+WG$$+3G$$+H$$*H;$$+WG$G&Z$$&Z$$&Z$$&[$$&[f$$&[C$$&z[$$C;Q$$CQ$$BR$$C;R$$CR$$BR_$$BR<$$C;Z$$CZ$$BZ$$C;[$$C[f$$B[C$$B[$$=1 $$<0$$<0$$<0$$<0$$Tt$$>]X$$>]5$$>^]$$>;\$$>]$$=]5$$=]X$$!V1 $$!30$$!0$$ 0$$ 0$$ 0$$ 1 $$Jt$$JQ$$J-$$sJ $$OJ-$$+JQ$$Jt$$Km$$KJ$$K&$$sK$$OK&$$,KJ$$Km$$Km$$KJ$$K&$$K$$eK&$$AKJ$$Km$$>^_G$=(l$$<(H$$<(%$$<($$<(%$$;/^$@ $@ $@ $@ $&WXU$/^X|$$/X$$/X$$/X$$/Y $$/Y.$$/^YQ$$)X$0WX| 0WW_,s`-l[C$-[$$-[$$-[f$$-l[C$$-I[f$$-%[$$-[$$.e]-^$$-^u$$-^Q$$-l^.$$-I^ $$-%]$$-]$$rer, rK @ ,  r r 2K$2K$5L$d2M_$/A&2$03?<% ; 9;$" $ . k0$0$$0$$0$$k0z$$H0$$$0$$0$$V0$$20$$0$$0z$$0$$0$$0$$0$O8B$$+8$$7$$7$$7$$8$$y8B$$k8B$$H8$$$7$$7$$7$$8$$8B$$9^$$9;$$9$$8$$k9$$G9;$$$9^$$29^$$9;$$9$$8$$9$$9;$$]9^$$9$$!V$$$!3$$$!$$$ $e$$ $$$ $$$ $$$e$$$A$$$$$$$e$$$$$$$$$$$? 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V\ - OOt$$sK&$kOO$$O$$OQ$$OOQ$$Jt$$JQ$$J-$$lJ $$HJ-$$%JQ$$Jt$$GrNXGGrrGr!VGr:Gr>;GrGGrG>;t390Gr!pUNXGH;3t%:p9!tNXGrrrH$$]$$$$$$A$$d$$k$$$$k$$k$$9$$9A$$d$$d$$d$$dG$d$$d$$A$$k$$2k$$k$$$$$$]$$$$$$$Gr rV)!V)U19=$r%7$G$A$$ dP H5S&WQC$P$rP$&WP$@:\_V$:Y V$:ZV$:^ V$:UJ$ rU&]$rU&$ r_$VUVUU&$:V$:U$\_$S$ rR $_'$sO$UM(E+WFI+WE-^.\ZY./?$@/?$2?$$4^Ay$4^?$@4?U$5?{$G1,?{$G2?$$2>;$$3?9$3?4$3A$2IBBd$2IA$2A$$2A$$2lAm$$2IAI$$2%Am$$2A$$1A$$2IAm$$2?$d2A&$$2?G$1,A$37$3eC_$r2LB$A$VV9$ +<)SX)Q)R<2IR5A$]8$N7$$8$$7$$r7$$N7$$+7$$7$$8$$N7$N8$$9$@7$$H;tp>tNh.Disk ControllerTagRegisterControlRegister16-wordFIFOFormatRAMSubsectorSequencePROM4ReadPROMSequenceWrite884OtherControls>IOB12>DriveTagCylinderTagHeadTagControlTag12TagBusWordCounter>1216-word>>>16TagTW6Divider4>>SubsectorCounterSectorTWiiiselectedbabaIndexTWqqcdeffedc18>NotOnLineNotReadyNotSelectedHeadOvflSeekIncDevCheckcdeffedcReadOnlyFIFOControlFifoUnderflowFifoOverflowRdFifoTWWrFifoTWShiftRegister>iSelectErrorsFromDiskDrivesTo DiskDrives>DriveErrorsFromController<Radial cable iSelected.0Selected.1Selected.2Selected.3Selected.iBitClock.iData.iSubsecIndex.i16>>16Subsec.iIndex.iSubsec.iIndex.i>>&StatusCylinderOffsetNoTerminator<>MuffRegister168MufflerMultiplexorsDMuxAddress84fedcMultiplexor controls11<<>DMuxData>DMuxDataDMuxClockBoardSelectBoardSelectabFigure 139/5/79 rUHT G$HJk$I4$I4$HIX$M$H6 $H2%$rT$rT$HU$rX$%Gd$+D$%C$%C$ dZ$ dZ@$Z$ d^$tONKHI42VfdUJ&FI \< ZZ ]X _ a< dc$_$ d_@$ d_$ bXZn$a$`g$d\$\$^ $`C$]$U^$:X$+`$b+[$]_9$_$`_^V|S!tVW:|\HTk$#U$HXG$#O r$#N4 r$#L r$#Km r$&tO&NX &L&K #R $%R(R<&WQ$W<UHV$,|S!Vf$tWWP$N$#J$ rP$O$ 9N$|KM,L/.N$d.etOt"sI$@I!F$!E$#HEt$#F&E-+E$-Et$,F$e|B/-B/.C$.C$5WD$.Gd$/tFI 0E-@D ,, G1uD(HD7D7tD6Cd$5WE$=|B/=B/0BB$3@$y ; ;AtA/|?3e?51515151253U$24$24$24^$24$23$23$23B$22U$8e4$2/U$2/$203$20z$20$21 $21P$21$21U$5..5..5..5..9;0$U 4$3$Ht4+|0g8$V$8V$8V$8]V$8V$8V$9t 9H:e 9998e0$5|&5&5&5&2*U$2*^$2*$2)$2)$2)A$2($2($2(lU$8e,$2+U$2, $2,P$2,$2,$2-%$2-l$2-$2-U$5*J5*J5*J5*J9t:H6$kH6$7$GH<%$898 97 @=@?4+$6 G$#H2I$2%k$2%$e43|0g1!39$19$1l9$19$8$87It"sBuBBB-NG@-N@-M>;|K*$)$s(% d$6,$7t#9;)$U8e)$H2%$2I$Bu2IB1,B0 |0g0g9t2 9+W +5G+5W.e4$-5+W-G+..-$.e.e=u -IKJG92O-+Wr G,s7I|9A$?!39$? y]$u,s2t!V 2 2 2, ) / .(H 8',$7l's$8's$?'O$B's$?*$B $;B$;Bd$ |%"$u(t+ |'<t,s|*J9t: 9K&$|GvJ$tK1/G1(HG#)$$e&$U#&z$#&z$y$e(V$&)$e'OV$&'s(Bf(@+|%J+#Bu+BH V$9VGG(BB9$(@H$8:{$8V$9t8OV$9s 8erG G#H4$#H|0gs(G,P$s/V$- $ /$$.$ #%$+uH$G$!$UH!zk$H!z$ydt#!"$d!V"$#$d$d$d$d$d$kd$$d$d$d$Od$d$d$yd$2d$Ad$]d$d$udH H$yHk$$UH G$t,Ar$#%r$e$d $!$!$d :$9$,$|ees$",z$ :u!Vk G$$dst$V$r2@$2$ k$$ 9HGB | l$+$H$!3 $+H$$$$d $ $r $ $u #| u  +$$@+ rt  "s =|>=>?WAm$?WD$"sI{$e$"sr =ud~9dAbXFigure 14Display ControllerD1Display.sil18Fout>>T0T1ROdd1616REvenFIFO256 x 32RAM>>T1pAReaderPtrBReaderPtrAWriterPtrBWriterPtrFIFO is written during FH andis read during the SH; readsalternate between channelA and channel B (irrespectiveof whether or not the channelwants the FIFO).>>>>7ACanReadFIFOAWritingFIFO>>1HWindowChannelOnChannelOffCursor video1st FIFORead2nd FIFORead<><><><><>32LeftMargin15><>16CursorX><18128 words ofFIFO used by A,128 by B.NLCB16 x 12RAM12CLCB<>RAMHRamHRamAddrHRamOut1024 x 33>>32FIB>>32SIB32>SR8A or B channel timing (in pixel clocks, not to scale)3>10Permuter>32>8SR>32SIB32>FIBT0DblCursorDataAItem.0AItem.1AItem.3BItem.0AOnBOndcAItem.2PolarityMiniMixer256 x 4 RAM48>4AItem[4:7]8dcCursorDataAItem.0BItem.0PolarityefcddcVBlankHBlankdc1AltoVideoPClkPClkVariousregisters>of NLCB and CLCB registersNLCBAddr412ItemClk'sPClk/2hg18IOBp16RIOBRIOBT3See Figure 15 for layoutHorizontal Blanking<>Visibleleft margin8/30/81RIOB>>RIOBMiniMix7-WireInterfacepTo TerminalHSyncHBlankVSyncVBlank6VCWSyncGenerator3pVisible data>Visibleright margin>>>>>>>Video$r !d<u 6$3$ 2$ 2$ -$y -$-$U 1 $4$ 4;$ Gt5W4 |0/$G/^+$ + u6 1,4 +$t4d4;$5W.$0/+6 $-$V+-$+-$y/^ +$p2t0/|+0u6,9|0 V(% $ t(H V& $ & V%^ $ % V# $ $ V#H$V&3$%$-,s+W*:)(:|$u:#:!: Jt& , $+,, * $+* V)$V+z$+z$]:|(X:&+$st,,V` (])[>\?[_F$2ZJ$UHZ$V3e\ :Z$U,a`g^.$9$e^.$9"sa#`g*^.$|b :b*_Jtb[/+[/H[/[/HW1W rt^u^+$ ^r$^u H^+$^G$!^u^$"s^$#H|[/[/$e^9$(H^9$)e[/$e[/3t^u*^$*|[/?[/6,tZeZH[C$#[C$2[C$7[CU$9|W2W&t^u,s +W*: -$ )$ )$ F$dBf$ BB$ BB$ pEt tC BdD$DX$EtdpEt `9$|\+\`$ t: 9$ 9$d9$ p< @$d?$ >$ >$ t?Wd<%U$=B$d;t$;P$;P$H; ;-;$9<d;+$ >^$ r|8.8ue1s$t2+3$.0$+0z2$+0z$2,1s |..1s...1$20z$220z2$50$23$/t20W1s$3e1s71s$6t29;3$$pXX5;t$t<?$ r| 8C$@t<$981s=-A& $-? $->^ $-< $AAp@-#H?$e?$%?W%= $A$$XSyncEnableFakePixelClockUseFake------DWTShutupDHTShutupNLCBAddr[0:3]<>NLCB data<>KeepHRam'WriteHRam'LoadHRamAddr------------------------>Data[0:7]><--------<>KeepMixer'WriteMixer'LoadMixerAddr--<>--><--AddrLoadWriteKeep1514131211109876543210--------Address[0:7] OR Data[0:7]<>377 (Y)367 (M)DDC**Addr[1:10]375 (Y)HRam374 (Y)373 (Y)DWTFlag*8/29/81372 (Y)MiniMixer360 (M)PixelClk361 (M)Mixer362 (M)CMap365 (M)BMapRed[4:7]Blue[0:7]<>Green[0:7]Red[0:3]<<>>01370 (Y)----1514131211109876543210MapInLo1>><TIOAOutputTIOAInput376 (Y)366 (M)364 (M)363 (M)361 (M)360 (M)TIOAInputNoPEData*Data** Parallel registers DispY/DispM0VCW*VBlankVSyncOddFld111BMargin10--AMargin*Left margin count (negative)<>2AWidth*12BWidthWidth count (negative)<>3AFifoAddr*13BFifoAddrFifo Address (even)<>414BScanPolarity*ResolutionSize8Size4Size2Size15MixerMode24BitBBypassA8B215Cursor position (negative)<>CursorX*6--16CursorLo*7--17CursorHi*Cursor data [8:15]Cursor data [0:7]<<>>TerminalTerminalMufflerMultiplierDivisor<<** Only starred bits or fields are usedon DispM; all others are ignoredStatics**NLCB**Status**MapInHi**AScan**DHTFlag**WCB*0*Map'Map'Map#r V9Cu =Lf$Lf$J-tKJFIKJBfKJ>KJ:KJ6KJ3KJ/:KJ+WKJ'sKJ#KJKJKJKJKJKJHLf$DLf$ALf$9;Lf$1sLf$-Lf$)Lf$!Lf$Lf$VLf$5WLf$%Lf$:Lf$rL$]rL>^$LL$9r^ >;$re>;$L`$rr`>^$ra$:` $d%` $d5W` $dV` $d` $d!` $d)` $d-` $d9;` $dA` $d_J_J_J_J_J#_J's_J*_J/:_J3_J6_J:_J>_JBf_JFI_JJ-_J` $d=` $drJ>;$LG$rF>^$rF$:F$%F$5WF$VF$F$!F$)F$-F$1sF$9;F$AF$DF$HF$EEEEE#E'sE+WE/:E3E6E:E>EBfEFIEJ-E=F$=@$@$J-?FI?Bf?>?:?6?3?/:?+W?'s?#??????H@$D@$A@$9;@$1s@$-@$)@$!@$@$V@$5W@$%@$:@$rA&$rA&>^$LAI$rE >;$r>>;$L;-$r; >^$r; $::$%:$5W:$V:$:$!:$):$-:$1s:$9;:$A:$D:$H:$99999#9's9+W9/:93969:9>9Bf9FI9J-9:$=:$=4$4$J-3FI3Bf3>3:36333/:3+W3's3#333333H4$D4$A4$9;4$1s4$-4$)4$!4$4$V4$5W4$%4$:4$r4$r4>^$L5$r8>;$r>;$L$Urz>^$rz$y:$%$5W$V$$!$)$-$1s$9;$A$D$H$:::::#:'s:+W:/::3:6:::>:Bf:FI:J-:$=$= $ $J-eFIeBfe>e:e6e3e/:e+We'se#eeeeeeH $D $A $9; $1s $- $) $! $ $V $5W $% $: $r $yr >^$L!$Ur$A>;$r,>;$L&$r&z>^$r&z$@:&$%&$5W&$V&$&$!&$1s&$9;&$A&$D&$H&$%:%:%:%:%:#%:'s%:+W%:/:%:3%:6%::%:>%:Bf%:FI%:J-%:=&$bVb Vc r$$c $V|_Z,s_Z.tc..b2c2b2a5d5cu:WbX>;bXBbXFcEtbIdIcu\ r\+$\U$r|Y>Y>2t\ \H$8\$|Y>KY>G$H.$tIXH;+IX+H;IHGf:HeIXeGf#HGf',Gf*Gf.Gf2Gf6Gf:Gf>Gf#HIX%I+$9I$K|F%FAItGfE-GfIGfBBBBeB#HB',B*B.B2B6B:B>BBfCABAAFCEBICJ-B<<<<e<#H<',<+<.<2<6<9=9<==><>;tBf;tB<A=Et=F<FI;tI=I;td6t r6 $!6 $r|3.,s3.:Wt6t -6 $?6 $K|3.-3.t",",",",|<&$*.$Ht)H(+)+(V*V)eV(H)e|&K&t+!+z$9;+z$G|'!'2t+ I+IX+e#H',+.26:>BfFI5bX5a<D` $dH` $dIXbX1s` $dH<="$G"$K|=t0W/:1s00=.e$J--FI-Bf->-:-6-3-/:-+W-'s-#------H.e$D.e$A.e$9;.e$1s.e$-.e$).e$!.e$.e$V.e$5W.e$%.e$:.e$r.$r.>^$L.$r2>;$.e$e0W#0W's0W+0W70W-0$D0$-|-K-pdbXIta<Fpa<4;tIX pH;H;C=<Dup55 !!((/:/:00$t)e7)e )$()r$-) $<)$-|&-&(.$)t', C;',' $/:' $='$G'$|#=#<#K#)&$-&$Mt)eM',L+z$M*$pt  =$$J-FIBf>:63/:+W's#H$D$A$9;$1s$-$)$!$$V$5W$%$:$r $yr >^$L +$Ur ]>;$pt GK|<=G $= $/: $ $C;t G) G r>;$L$Ur>^$r$y%+$5W+$+$!+$)+$-+$1s+$9;+$A+$D+$H+$ V V V V V# V's V+W V/: V3 V6 V: V> VBf VFI VJ- V+$=+$-| - <A$-A $(Ar$A$7t $K|  tV rA$A$r| s pffUSXB;t  t+ G MGMGL$9r[>;$ZZAZEtZHZrZ&>;$X:XsX:ZsZrX|>;$X-XYQr$:YQ$|UKUtW<W<:W<sW<-W<rV>;$WH$8eWH$|SKStUU :UsU 7IU-UV$@tU 9$-U +$-|RLKRLrU&>;$tS:SsS1S 7S =SASESIXSrS|>;$R<R< =R<E-R<IR<rQ>;$:P-PPH$9P+$|MKKMKrP&>;$stPNN:NsN rN{>;$M;M;:M;sM; 8N8M;|KIKKKI=S$AS$DS$HS$5WS$1sS$-S$tH :+$V+$IH+", C;"," 9$/" V$-|K-I-OQ $-M $AOQ $AM $t'9 pb 9S tSpB EtAJtA//0WN{f`s15141312111098765432100123456789101112131415D1Ethernet.silFigure 16Ethernet ControllerOutput_BTIOA = 016EthCEthCPd_InputTxCmdEnbl'TxOnTxEOPTxCntDwnRxCmdEnbl'RxOnRxBOP'--TestCmdEnbl'LoopBackNoWakeupsSingleStepTestClockTestColl'TestDataReportCollsHost Address<>RxOnTxOnLoopBackTxCollNoWakeupsTxDataLateSingleStepTxFifoPETxCmdEnbl' enables setting of TxOn and TxEOPRxCmdEnbl' enables setting of RxOn and RxBOP'TestCmdEnbl' enables setting of LoopBack, SingleStep, NoWakeups, TestClock, TestColl', TestData,and ReportCollsHost Address is set by backpanel jumpersPDInputPDNewPDOldEClkEClkEClkFSMPDCarrierPDEvent[0:1]0 No event1 Collision2 Data 03 Data 1PhaseDecoderReceiverFSMRxCollisionRxEOPRxSync'RxIncTransRxCRCResetRxCRCClkRxDataRxCtrl[0:1]RxSRFull'EClkSR1EClkRxDataRxEOPReceiverFIFOefdccdfe211616-wordx 19-bitRAMT1ParityEthData.18IOAtten18EthData[0:17]T1T1IOB18RAM16-wordFIFORxFifoRdPtrRxFifoWrtPtrTxFifoRdPtrTxFifoWrtPtrx 18-bit18TransmitterT118SR1TxDataTxCRCEnblRxDataRxCRCClkRxCRCResetRxCRCErrorCRCTxCRCClkCheckTxOffT1TxFifoPECRCGenFSMTransmitterTxCRCEnblTxCRCClkTxGoneTxGoTxDataTxSRCtrl[0:1]TxEndTxAbortTxStartTxSREmptyGotTxBitwire-orPhaseEncoderTxOffXcCollisionRxCollisionTxGoPEOutputTxCollisionGotTxBitTxCollisionTxOffTxFifoPETxDataLatedcTxAbortabTxFifoEmptyTxEOPTxEnddcTxFifoFullTxEOPbaPDCarrierTxStartReceiverTransmitterRxCollisionRxDataLateRxCRCErrorRxIncTransPd_Input1514131211109876543210EthDTIOA = 015RxCollisionRxDataLateRxCRCErrorRxIncTrans------------------------8/30/81(Receiver status word following end-of-packet)=$e$$e$Kt#G#C;#?W#;t#7#3#0#,,#(H#$e# #####I$e$E$e$A$e$:$e$2I$e$.e$e$*$e$"$e$$e$+$e$6,$e$&$e$$e$H$$H$>^$M$$H(>;$O>;$L$k>^$k$$&$5$$d$",$)$-$1$9$AI$E-$d+H+++++#+'+++/+3e+7+:+>+B+F+Jt+H$=f$Bu%:r !p$9(H +&9t'sd&Wd%:&W&WV's&W%:'s&W%:#&W&&W+&W/:'s/:&W/:%:3&3%;t's:&W;-%:6t&6%>&>%Bf&Bf%F&F%I&Jt%d ] $!] 9$|,.et2I6,6,d9>>;>BBBEFdJ-IJ-,-!`r (I$b5$bX c$`$ `$ `$2b5d$`$2`$`$c$sc$`$s`$s`$2bXb5r$b5+$bX udJdJdJ`g$`C +$c$^@$^$$!t_&Wb &W` %:`$%:a$%:_$&_ &] &\ &[ bX :`.cd$4W$ .W_$.W_$ /:^.0W]4cQ +$5cu 4` r$5[5`4_' +$4] r$4\_ r$4Y r$4X5 r$5_J 5] 5\5b5Y 5XX uZ W$2 W$W<$ Z&$ tX 9X$ Y.X|$ VuS P&$2 P&$PJ$ S4$X$Q$Z&$PJ$ P&$P&$ $4a +$4Z r$X|$9tXQ$9QWVf|FYFYHFYHFYH$SSSSdUJ$UVC9$U$dShQ$dNUtTSRUmr$Q$P&$2P&$ :PJ$S4$uStS :Q$!Q (uQ!T $2!T $#T-$!W$sU$|R$tU #Um $!uW\$ZJ$Z$ BB$2 BB$rBf$ EP$C$ EtC C;$ r|AH;$G$I{$t?BC9>$9>$?$9G$\ [f \9$[C9$ J- H H9$ J 9$ArC$C;$|AtFVDC$EP$Bf$BB$BB$2duEsC;$+|AtC;C;$|AtCAI$? H?d$A&$0T $0R$0QC$1,T-1,R1,Qf 9Um$=P$9O$9O$=R :WSH>^d$>BB$#<$d;$;$#?$9Q=R9$H<d$=C$dHd$sJ$G$sG$sG$2HuKH$ tIGd$J $I$I{$I4$H$H_$H$dW_d$dW$dV$dV$dVC$dU$dU$dUm$ ? >6 +$2l r$3 +$53 r$7 +$4;d1$d1$d:4d$658 65W392 1$9865W 39^$7$6$53$3$$9$ G9^$#HuDX3=$-IDd$-I<$-I<$.tAI.e?C9$&BB$&Bf&@$&A &?{$&? &>$&>;3C$4C;3A$4A 3@P$4@t(H: (H9;(H7(H6t (6P$(7$(H9G$(H:{d$.9$.9$.6P$.7%$-8$G-89$-7$k-79$/:|5/:528$2t8/|0g/0g(3$(2%$(Ht3 (H2I12$23,|+,+/$Vt/: -l$V-/|,/,.A$ t0 :/$&W1 $(/:$&W/$&W/$(/$)1 $*/:$)/$)/$*/$1/$2I/: pM * d_'9$\_$Z$dt_J d] d\ d[ ]$ _$rZJ$I$9p=f$H$JttFB>:73e/+'#+HdE-$AI$9$)$",$d$$5$&$$A$A>^$Ld$$>;$p99 /:t-9 -$1$7I66?>=JJtIFB:3+W's#DXu9t V.9Kmc 6RSTK[0]RSTK[1:3]Meaning01234567No StkP changeStkP_ StkP+2StkP_ StkP+3StkP_ StkP+1ASELFF[0:1]Meaning0123012301230123--------01234567PreFetch_ RM/STKLongFetch_ RM/STKStore_ RM/STKDummyRef_ RM/STKIFetch_ RM/STKFetch_ RM/STKStore_ MdStore_ IdStore_ QStore_ TFetch_ MdFetch_ IdFetch_ QFetch_ TA_ RM/STKA_ IdA_ TShift operationASELMeaning01234567Store_ RM/STKFetch_ RM/STKStore_ TFetch_ TShift operationA_ TA_ IdA_ RM/STKBSELPrimaryExternal01234567MdRM/STKTQ0,,FF377,,FFFF,,0FF,,377----Q_ BLCMeaning01234567No actionT_ PdT_ Md, RM/STK_ PdT_ MdRM/STK_ MdT_ Pd, RM/STK_ MdRM/STK_ PdT_ Pd, RM/STK_ PdLogical357111517213337NOT ANOT A OR NOT BNOT A OR BNOT A AND NOT BNOT BA XNOR B, A EQV B, A=BA OR NOT BNOT A AND BA XOR B, A#BBA OR BA AND NOT BA AND BAA1 (all ones)A0 (all zeroes)6Arithmetic (no carry)Arithmetic (with carry)206236A2*AA+BA+12*A+1A+B+1AALUF[0:2]01234567MeaningShiftNoMaskShiftLMaskShiftRMaskShiftBothMasksShMdNoMaskShMdLMaskShMdRMaskShMdBothMasksSHASHBRMaskLMaskShC bits:234:78:1112:15RF_ AWF_ AShC_ BA[2]A[2]B[2]A[3]A[3]B[3]P+S+116-P-S-1B[4:7]undefined16-P-S-1B[8:11]15-SPB[12:15]CountFF[4:7]FF[4:7]FF[0:3]Shift controls come fromShc when BSEL[0]=0 in themicroinstruction that shiftsShift controls come from FFwhen BSEL[0]=1, and thesource for B is changed to QP=A[8:11]=number of bits to the left of the fieldS=A[12:15]=number of bits in the field - 1020021022023024025026027030031032033034035036037070071072073074075076077A[12:15]_ FF[4:7]A_ RM/STKA_ TA_ MdA_ QXorCarryXorSavedCarryCarry20ModStkPBeforeW--ReadMapPd_ InputPd_ InputNoPERisIdTisIdOutput_ BFlipMemBaseBranch conditionsBigBDispatch_ BBDispatch_ BMultiplyQ_ B--TgetsMdFreezeBCReplace RSTK byNoop100101102105106107122123124125126127PCF_ BIFUTest_ BIFUTick--MemBase_ B[3:7]RBase_ B[12:15]Pointers_ B----CFlags_ A'BrLo_ ABrHi_ ALoadTestSyndromeProcSRN_ B[12:15]130131132133134135136137140141142143144145146147RescheduleNoRescheduleIFUMRH_ BIFUMLH_ BIFUResetBrkIns_ BUseDMDMidasStrobe_ BTaskingOffTaskingOnStkP_ B[8:15]RestoreStkPCnt_ BLink_ B150151152153154155156157Q lsh 1Q rsh 1TIOA[0:7]_ B[0:7]--Hold&TaskSim_ BWF_ ARF_ AShC_ A160161162163164165166167170171172173174175176177B_ FaultInfo'B_ Pipe0 (VaHi)B_ Pipe1 (VaLo)B_ Pipe2'B_ Pipe3' (Map')B_ Pipe4' (Errors')B_ Config'B_ Pipe5B_ PCX'B_ IFUMRH'B_ IFUMLH'B_ DBufB_ RWCPRegB_ Link262263264265266267270271272273274275276277000-17040-57060-67200-17220-37240-47250-53254-57260-61RBase_ FF[4:7]Replace RBase byFF[4:7] for writeTIOA[5:7]_ FF[5:7]MemBaseX_ FF[6:7]MemBX_ FF[6:7]--Pd_ ALUFMRWPd_ ALUFMEMPd_ CntPd_ PointersPd_ TIOA&StkPPd_ ShCPd_ ALU rsh 1Pd_ ALU rcy 1Pd_ ALU brsh 1Pd_ ALU arsh 1Pd_ ALU lsh 1Pd_ ALU lcy 1DivideCDivide300-37340-57FF[4:7] for writeMemBase_ FF[3:7]Cnt_ FF[4:7]Wakeup[FF[4:7]]StkP_ StkP - 4StkP_ StkP - 3StkP_ StkP - 2StkP_ StkP - 1Field:110-17120-21LoadMcr[A,B]103104RescheduleNow113232527313501422362002142221614100711156125131234A - B - 1A - 1A - BValueAddrMeaningMeaningAddrValueALUFM addresses for operationsin standard system microcodeqqD1CribSheet.sil--0 = No ovfl/undfl check1 = Ovfl/undfl checkIOFetch_RM (io)Flush_RM/STK (emu/flt)Map_RM/STK (emu/flt)IOStore_RM (io)BSEL.1BSEL.2Programmers' Crib SheetDerivation of Shift ControlsALUFM Control ValuesALUF Shift DecodesRSTK Decodes for STK OperationsASEL Decodes (FF not ok)ASEL Decodes (FF is ok)BSEL DecodesLC DecodesFF DecodesFigure 17InsSetorEvent_BEventCntB_BB_EventCntA'B_EventCntB'360-77(Notify)7/23/85,,tV,,S 2S.eQ.eP.eO.eN.eM.eLf.eKJ.eJ-2Q2O 2N 2P c.+c.c.HaH`gH^.H]H[HZHXHWHVfHUJHT-HSHQHPHOHNHMHLfHKJHJ-a[VfQMLfKJJ-a^.] [XW Vf UJ T-SQ P ONM LfKJJ-+b2b-a-`g-_J-^.-]-[-Z-Y2a 2`g 2_J2^.2Y2Z2[2] c.c. c.a`g_J^.][ZYa`g_J^.][ZY a `g ^.UJUJSRQfPJO-NLKS RQfPJO- NL K:E:A:@:?:>:V=fV<=f< @-=f @-;=<:9876t5W0/.-,s+W*:)GF DCBA@t ?W>;=<: 9 876t 5W 20/ .-,s+W*:4;)&%$!V :sV:&% $"s!V :  s:r V 9  s    r V  9     sV:V:r V 9  &&&&&s&V&:&&&&r  V 9   ++ +++V +: ++ +8888s8V8:8888888r8 VG4;2&&r& 9& & 8++r+ V+ 9+ + << < <<s <V <:< < <<< < <r< V8 8 3< < <2M2Lf2KJ2J-+V #"s# :B:=f:8:7:6:5:3e*B*@*?*>*:*7*6B=f8H7H654H3e.eB.e@.e?.>.:.e7.e60? 0>06DDVD0D-D)DV0V/H0$H0$,s09$|/./Bu t_J2V2U_JZ`gY+Y.HG8/GXGdKG +$HIX5WG/:5WGHe5Gd#H#HHrdp-IGf9Gf,,W+ddd V I +IGVeGF.0$"rU t +s + 7$d&$d8GCu TJegb TIMESROMAN  HELVETICA  HELVETICA TIMESROMAN  TIMESROMANLOGO TIMESROMAN  TIMESROMAN  TIMESROMAN  TIMESROMAN  HELVETICA  HELVETICA  HELVETICA HELVETICA Gates  TIMESROMAN  TIMESROMAN  TIMESROMAN HIPPO  TIMESROMAN  TIMESROMAN  TIMESROMAN  TIMESROMAN  TIMESROMAN TIMESROMAN TIMESROMAN  TIMESROMAN  TIMESROMAN  TIMESROMAN  TIMESROMAN TIMESROMAN TIMESROMANHIPPO  TIMESROMAN  TIMESROMAN  TIMESROMAN  TIMESROMAN TIMESROMAN  TIMESROMAN TIMESROMAN TIMESROMAN  TIMESROMAN  TIMESROMAN  TIMESROMAN  TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN  TIMESROMAN  TIMESROMAN  TIMESROMAN TIMESROMANHIPPO  TIMESROMAN   TIMESROMAN   TIMESROMAN   TIMESROMAN  HIPPO   TIMESROMAN  TIMESROMAN  TIMESROMAN TIMESROMAN   TIMESROMAN   TIMESROMAN   TIMESROMAN HIPPO  TIMESROMAN   TIMESROMAN   TIMESROMAN   TIMESROMAN  TIMESROMAN  HIPPO  TIMESROMAN   TIMESROMAN   TIMESROMAN   TIMESROMAN  TIMESROMAN  TIMESROMAN   TIMESROMAN HIPPO  TIMESROMAN   TIMESROMAN   TIMESROMAN   TIMESROMAN   TIMESROMAN HIPPO   TIMESROMAN  TIMESROMAN TIMESROMAN  TIMESROMAN  TIMESROMAN  TIMESROMAN  TIMESROMANHIPPO  TIMESROMAN TIMESROMAN TIMESROMAN  TIMESROMAN  TIMESROMAN  TIMESROMAN HIPPO  TIMESROMAN TIMESROMAN  TIMESROMAN  TIMESROMAN  TIMESROMAN  TIMESROMAN TIMESROMANz h7} !):B L TV bi ZsyF7"Q% . 8`'2+'0 5;BJL U\h'y-       Q4:UA J?QYawemu} C %Fe ;# ,4 :B KSZ ckqgu i   #^   &4F< E.S 8] f\y'- Q ; cccB"""?cc Z e=-:~eieddpt%*oleddpt~dddd݉dH~d1manpresseditA.cm..djhNshXhXmmYsmdo􌽨dyumfddd~ddf]d|mj/cDoradoHardwareManual.pressvest.pa10-Nov-86 9:25:30 PST: