Date: Mon, 30 Jan 84 13:45 PST
From: Taft.PA
Subject: Note on Dorado disk format and timing
In contemplating a change to the Dorado's disk format from 28 to 30 sectors, I have found that the documentation on how the format sequencer works is incomplete. In particular, it is unclear precisely when certain events happen (e.g., at the beginning or end of a control pulse) and what is happening to the disk in certain places (e.g., in the gap between records of a sector). The proposed disk format change requires understanding these things very precisely, since the new format will operate very close to the limits recommended by Century Data for the T-80.
1. Format requirements
The table below shows the minimum format requirements for the T-80 and the AMS-315. Note that in all cases the AMS-315 operates with shorter minimum preambles and delays, so it suffices to consider the T-80 alone. (The T-300's format requirements are identical to the T-80's.) Also shown are the present Dorado 28-sector format (which is actually 29-1/3 sectors) and the Dandelion 30-sector format. The Dorado cannot adopt the Dandelion format directly because using that format requires issuing Head Select before the sector pulse, which the Dorado controller is not designed to do.
All intervals are in bytes.
CDS spec Present
T-80 AMS315 Dorado Dandelion
Initial tag -- -- 2 --
Head select -- -- 6 --
Preamble+VFO 51 27 56 32
Sync 1 1 2 2
Header -- -- 4 4
ECC -- -- 4 4
Postamble+tag -- -- 6 --
VFO 15 12 14 24
Sync 1 1 2 2
Label -- -- 20 20
ECC -- -- 4 4
Postamble+tag -- -- 6 --
VFO 15 12 14 24
Sync 1 1 2 2
Data -- -- 512 512
ECC -- -- 4 4
Postamble 18 8 6 38
Totals 650 610 664 672
Minimum recovery times:
Head select/read 24 ?
Head select/write 6 ?
Head switch/read 24 12
Head switch/write ? 5
Other information:
20160 bytes/track
672 bytes/sector for 30-sector format
Data rate: 9.67*10↑6 bits/sec = 1.21*10↑6 bytes/sec
= 1.83 microseconds/byte
2. Basic timing
All timing is derived from the disk itself. Except during reading, the bit clock comes from a clock track permanently recorded on the disk. Sector pulses are derived from the same clock track. This means that disk format tolerances are insensitive to such things as rotational velocity and microcode wakeup latency. (On the other hand, wakeup latency is a critical factor in determining the minimum size of gaps between records and at the end of a sector.) The minimum lengths of preambles and postambles recommended by Century Data are intended to cover all reasonable variations in angular head position from one drive to another. These are smaller on the AMS-315 than the T-80 because the AMS-315's disk is non-removable, so interchangeability is not an issue.
When the controller is idle, Active is low and Idle is high. This forces the sequencer into state zero [page 9 of the DskEth drawings]. Nothing interesting happens when the command register is loaded; the command doesn't actually begin until the Active flipflop is set by the leading edge of the next Sector pulse [page 8]. (Interestingly, the Sector task wakeup is generated by the trailing edge of Sector rather than the leading edge. The duration of Sector is 4.5 microseconds for the Index pulse and 1.2 microseconds otherwise.)
The sequencer is entirely driven from WordClocks. The clock generator endlessly produces WordClocks every 16 BitClocks except when reading the preamble of a record. The WordClocks are not synchronized to Sector, so there is an uncertainty of up to 15 bits in the time at which a sector actually begins [page 19].
At the first WordClock after the leading edge of Sector, instruction zero of the selected sequence PROM (read or write) is loaded into the output register (the F16 at b20) [page 9]. There are two kinds of instructions: Tag and Count.
A Tag instruction causes Tag←Ram to be generated on the same WordClock. This causes the Tag register to be loaded from the Format RAM location addressed by the instruction [page 10]. Tag timing is thereafter handled independently by the sequencer at the top of page 10; the Tag strobe lasts for 13 BitClocks. A Tag instruction lasts for only one WordClock, because the delay counter [page 9, lower left] is configured to stick at zero, thereby forcing CntDone' low and enabling the PE' of the sequencer output register and various clocks [page 9, upper right]. Meanwhile, PromA4, which was forced low while Idle was asserted, becomes high when the first WordClock occurs, because PromA4' is the input to the register that generates PromA4. This causes the sequencer to advance to the next instruction. (PromA4 serves as the low-order bit of the sequencer state counter at the upper left of page 9.)
A Count instruction causes LoadCnt to be generated, which loads the delay counter from the Format RAM location addressed by the instruction. The counter is counted down by WordClocks until it reaches zero and then sticks there. While it is nonzero, CntDone' is forced high, which inhibits loading of the sequencer output register and the output clocks. If the counter is loaded with some value n, the delay lasts for n+1 WordClocks. If the Count instruction is preceded and followed by Tag instructions, this means that the total duration of the preceding tag is n+2 WordClocks.
3. Write timing
Instruction 0 of both the read and write sequencers sends a Tag command that asserts ControlTag and HeadSelect. This enables the head selection mechanism in the drive. Instruction 1 is a Count for the delay required by the drive between asserting HeadSelect and asserting Read or Write.
After this, each of the four possible records in the sector is treated independently; control passes between the read and write sequencers as appropriate. A write proceeds as follows.
Instruction 2 of the write sequencer sends a Tag command that asserts ControlTag, HeadSelect, and Write, commanding the drive to begin writing bits on the disk. Because ShiftOut has not yet been asserted, the output shift register is never loaded with anything but is only shifted, so zeroes come out after at most 16 bits [page 15]. (I believe the shift register always contains zero at the beginning of every operation.) The drive continues to write zeroes during the delay given in instruction 3.
Meanwhile, the microcode sends the sync word (actually a zero byte followed by a sync byte of either 1 or 201B) followed by the data words for the record. This is buffered in the FIFO, and the first word waits in the Out Register [page 15].
When the delay in instruction 3 is finished, instruction 4 asserts ShiftOut and ComputeECC [page 9]. ShiftOut causes ShiftRegLd' to become low at the NEXT WordClock, which enables the Shift Register to be loaded from the Out Register. This means that data bits start to be sent to the disk one WordClock after the beginning of instruction 4. Instruction 4 lasts for one WordClock.
Instruction 5 continues to assert ShiftOut and ComputeECC for a length of time equal to the number of data words in the record (not including sync and ECC). At the beginning of instruction 6, the sync word and all but the last word of the data have been sent to the disk, and the last word is loaded into the Shift Register by the WordClock at the end of instruction 5.
Instruction 6 turns off ShiftOut, assuring that a ShiftRegLd' won't happen at the end of instruction 6. During instruction 6, which lasts for one WordClock, the last word of data is sent from the Shift Register to the disk.
Instruction 7 turns off ComputeECC, which switches the WriteData multiplexor [page 15, top right] from ShiftReg.00 to EccData.32, and also breaks the feedback paths in the ECC generator [page 16]. Instruction 7 lasts for 3 WordClocks; during the first two, the 32 bits of ECC data are sent to the disk, and during the last WordClock, zeroes are sent (the ECC register having been cleared out).
Instruction 8 generates NextBlockCl at the beginning of the instruction [page 9], which shifts the command register to the command for the next record [page 8]. However, since the Tag register hasn't been reloaded yet, the disk continues writing during instruction 8 (which lasts for one WordClock), so a second word of zero postamble is written on the disk. (I do not know the purpose of the two words of postamble; there is no mention in the Century Data documentation of postamble being required.)
Instruction 9 and later are for the next record, which is done the same way as instructions 2 through 8. The only difference is that the preamble is shorter in later records than in the first. The reason is that the first preamble has to be long enough to span all possible variations in angular head position, which affect the distance from the sector pulse to the first bit of preamble (it's important that reading start over valid preamble). Subsequent records are precisely referenced as so many bit clocks from the end of the first record, so their preambles only have to be long enough to allow the drive electronics to reacquire bit phase.
4. Read timing
The read sequencer begins much the same as the write sequencer; in fact, instructions 0 and 1 are identical. Instruction 2 is a Count command that introduces some additional delay to ensure that reading will not begin until the disk head is well into the preamble.
Instruction 3 sends a Tag command that asserts ControlTag, HeadSelect, and Read. This commands the drive to begin reading data from the disk. Instruction 4 is a Count instruction whose delay is the number of data words in the record. It asserts ShiftIn and ComputeECC at the beginning of the instruction [page 9]. Raising ShiftIn has an important additional side-effect: it disables further generation of WordClocks [page 19]. This freezes the sequencer and counter at the beginning of instruction 4. (Asserting Read also causes the drive to stop sending BitClocks until it has acquired bit phase on the data it is reading, and then to send BitClocks derived from that data.)
Meanwhile, bits begin arriving from the disk. So long as they are zero, they simply pour through the Shift Register and out the other end [page 15]. But when the sync byte is reached and is right-justified in the Shift Register, it is recognized by the logic on the lower left of page 19. (The hardware is prepared to recognize either of two sync patterns, 1 or 201B, according to a bit in the Tag register. The 201B recognizer will actually recognize any odd value from 201B to 377B. The sync byte recommended in the T-80 documentation is 377B, but for some reason we use 201B.) When the sync byte has been recognized, it releases the WordClock generator. 16 BitClocks later, the first word of data has been read into the Shift Register and a WordClock is generated.
The sequencer is still in instruction 4, but now the delay counter is counting again. At each WordClock, InReg←SR' is generated [page 19], causing the In Register to be loaded from the Shift Register. The data is thereafter synchronized to Dorado clocks, sent through the FIFO, and consumed by the microcode.
When the delay count is exhausted and instruction 5 is started, the last word of data is loaded from the Shift Register to the In Register. Instruction 5 is another delay command that lasts for two WordClocks and that continues to assert ShiftIn and ComputeECC. During this time, the ECC is read from the disk and is fed into the ECC checker (it is also sent through the FIFO, but the microcode throws it away). At the end of instruction 5, the ECC has been checked.
Instruction 6 sends a Tag command that turns off Read but continues to assert ControlTag and HeadSelect; consequently, sometime during this instruction (which lasts for one WordClock), the drive stops reading data and switches back to the BitClock derived from the clock track. The instruction also continues to assert ShiftIn but turns off ComputeECC. This switches the ShiftReg.in multiplexor [page 15, top right] from ReadData to EccData.32, and also breaks the feedback paths in the ECC checker. This enables the result ECC to be read out.
Instruction 7 is a Count command with a delay of 1 and with ShiftIn still asserted, at the end of which the second word of the ECC has been read into the Shift Register. The WordClock at the beginning of instruction 8 generates the last InReg←SR', which sends this word into the FIFO. Instruction 8 also generates NextBlockCl, which shifts the command register to the command for the next record just as for writing. During instruction 8, the Shift Register continues to read from the ECC checker, which is now filled with zeroes, and is thereby cleared out in preparation for the next record.