{T1Test.mc, HGM, 13-Feb-85 22:15:24} Reserve[0F5F, 0FFF]; {section used by the CP Kernel } SetTask[0]; StartAddress[Go]; RegDef[address, R, 1]; RegDef[rhAddr, RH, 1]; RegDef[length, R, 02]; RegDef[data, R, 03]; RegDef[dally, R, 04]; RegDef[key, R, 09]; RegDef[wordIncr, R, 0A]; RegDef[packetIncr, R, 0B]; RegDef[switches, R, 0C]; RegDef[temp, R, 0D]; RegDef[passCount, R, 0E]; {number of good passes} RegDef[recv00, U, 00]; RegDef[recv01, U, 01]; RegDef[recv02, U, 02]; RegDef[recv03, U, 03]; RegDef[recv04, U, 04]; RegDef[recv05, U, 05]; RegDef[recv06, U, 06]; RegDef[recv07, U, 07]; RegDef[recv08, U, 08]; RegDef[recv09, U, 09]; RegDef[recv0A, U, 0A]; RegDef[recv0B, U, 0B]; RegDef[recv0C, U, 0C]; RegDef[recv0D, U, 0D]; RegDef[recv0E, U, 0E]; RegDef[recv0F, U, 0F]; RegDef[recv10, U, 10]; RegDef[recv11, U, 11]; RegDef[recv12, U, 12]; RegDef[recv13, U, 13]; RegDef[recv14, U, 14]; RegDef[recv15, U, 15]; RegDef[recv16, U, 16]; RegDef[recv17, U, 17]; RegDef[recv18, U, 18]; RegDef[recv19, U, 19]; RegDef[recv1A, U, 1A]; RegDef[recv1B, U, 1B]; RegDef[recv20, U, 20]; RegDef[recv21, U, 21]; RegDef[recv22, U, 22]; RegDef[recv23, U, 23]; RegDef[recv24, U, 24]; RegDef[recv25, U, 25]; RegDef[recv26, U, 26]; RegDef[recv27, U, 27]; Trap: temp ¬ RRot1 ErrnIBnStkp, ClrIntErr, CANCELBR[$, 0F], c1, at[0]; Xbus ¬ temp LRot0, XwdDisp, c2; DISP2[TrapType], c3; Parity: GOTO[GoToGo], c1, at[0,4,TrapType]; Init: GOTO[GoToGo], c1, at[1,4,TrapType]; Stack: GOTO[GoToGo], c1, at[2,4,TrapType]; IB: GOTO[GoToGo], c1, at[3,4,TrapType]; GoToGo: Noop, c2; Noop, GOTO[Go], c3; Go: passCount ¬ 0, ClrIntErr, c1; ExtCtrl ¬ 5, {Init Incr, Zero, UnBlank} c2; GOTO[Start], c3; { CRC Info (by hacking with a 3MB board): CRC after n words of data Data 1 2 3 4C6F 2973 5E4E 6CC6 0 8017 807B 8113 1 12 8069 17A 2 18 805F 1C4 8000 1E 804D 1AE FFFF 1A 52 1E2 8005 0 } {------------------------------------------------------------------------------------} Start: recv00 ¬ 0, c1; recv01 ¬ 0, c2; recv02 ¬ 0, c3; recv03 ¬ 0, c1; recv04 ¬ 0, c2; recv05 ¬ 0, c3; recv06 ¬ 0, c1; recv07 ¬ 0, c2; Noop, c3; MainLoop: address ¬ 20, c1; address ¬ address LRot8 {2080} c2; rhAddr ¬ 0, c3; Noop, c1; temp ¬ 080, c2; temp ¬ temp LRot8, {8000} c3; IO ¬ [rhAddr, address + 2], {control} c1; MDR ¬ temp, {Reset} c2; Noop, c3; CheckSwitches: IO ¬ [rhAddr, address + 3], {Switches} c1; Noop, c2; Q ¬ MD, c3; [] ¬ Q xor 000, ZeroBr, c1; switches ¬ Q, BRANCH[$, SwitchesAll0s], c2; temp ¬ 0FF, c3; [] ¬ Q xor temp, ZeroBr, c1; switches ¬ Q, BRANCH[$, SwitchesAll1s], c2; Noop, c3; BoardSetup: temp ¬ 098, c1; temp ¬ temp LRot8, {9800} c2; Noop, c3; {Use the next 3 lines to test filter...} { temp ¬ 0B8, {reset, no accept, no int} c1; temp ¬ temp LRot8, {B800} c2; Noop, c3; } IO ¬ [rhAddr, address + 2], {control} c1; MDR ¬ temp, {reset, accept, no int} c2; Noop, c3; IO ¬ [rhAddr, address + 3], {Address Filter RAM} c1; MDR ¬ passCount, c2; Noop, c3; IO ¬ [rhAddr, address + 2], {control} c1; MDR ¬ 0, {go} c2; Noop, c3; SendPacket: IO ¬ [rhAddr, address + 0], {data} c1; MDR ¬ Q ¬ length, c2; data ¬ key, c3; SendAnotherWord: IO ¬ [rhAddr, address + 0], {data} c1; MDR ¬ data, c2; Noop, c3; data ¬ data + wordIncr, c1; Q ¬ Q-1, ZeroBr, c2; BRANCH[SendAnotherWord, $], c3; Noop, c1; Noop, c2; temp ¬ dally, c3; SendDally: Noop, c1; temp ¬ temp-1, ZeroBr, c2; BRANCH[SendDally, $], c3; DoneSending: IO ¬ [rhAddr, address + 2], {status} c1; Noop, c2; Q ¬ MD, c3; {Test Tran Interrupt?} GrabPacket: IO ¬ [rhAddr, address + 0], {data} c1; Noop, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv00 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv01 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv02 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv03 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv04 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv05 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv06 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv07 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv08 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv09 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv0A ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv0B ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv0C ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv0D ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv0E ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv0F ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv10 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv11 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv12 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv13 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv14 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv15 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv16 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv17 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv18 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv19 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv1A ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv1B ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv20 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv21 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv22 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv23 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv24 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv25 ¬ Q, c2; Q ¬ MD, c3; IO ¬ [rhAddr, address + 0], {data} c1; recv26 ¬ Q, c2; Q ¬ MD, c3; Noop, c1; recv27 ¬ Q, c2; Noop, c3; key ¬ key + packetIncr, c1; Noop, c2; Q ¬ length, c3; DrainLoop: IO ¬ [rhAddr, address + 0], {data} c1; Q ¬ Q - 1, ZeroBr, c2; Xbus ¬ MD, BRANCH[DrainLoop, $], c3; ExtCtrl ¬ 3, {Gets Bumped on rising edge} c1; ExtCtrl ¬ 7, c2; passCount ¬ passCount + 1, GOTO[MainLoop], c3; {------------------------------------------------------------------------------------} SwitchesAll0s: GOTO[Restart], c3; SwitchesAll1s: GOTO[Restart], c3; Restart: Q ¬ 0FF, c1; Noop, c2; RestartLoop: Noop, c3; Q ¬ Q - 1, ZeroBr, c1; BRANCH[RestartLoop, $], c2; GOTO[Go], c3; {------------------------------------------------------------------------------------}