{SccTest.mc, HGM, 12-Feb-85  0:54:50}

	Reserve[0F5F, 0FFF]; {section used by the CP Kernel }
	SetTask[0]; StartAddress[Go];

RegDef[address, R, 1];
  RegDef[rhAddr, RH, 1];
RegDef[address10, R, 2];
RegDef[expected, R, 3];
RegDef[found, R, 4];

RegDef[temp, R, 0D];
  RegDef[rhTemp, RH, 0D];
RegDef[passCount, R, 0E]; {number of good passes}


Trap:	temp ¬ RRot1 ErrnIBnStkp, ClrIntErr, CANCELBR[$, 0F],	c1, at[0];
	Xbus ¬ temp LRot0, XwdDisp,				c2;
	DISP2[TrapType],					c3;
	
Parity:	GOTO[GoToGo],						c1, at[0,4,TrapType];
Init:	GOTO[GoToGo],						c1, at[1,4,TrapType];
Stack:	GOTO[GoToGo],						c1, at[2,4,TrapType];
IB:	GOTO[GoToGo],						c1, at[3,4,TrapType];

GoToGo:
	Noop,							c2;
	Noop, GOTO[Go],						c3;

Go: 	passCount ¬ 0, ClrIntErr,				c1;
	ExtCtrl ¬ 5, {Init Incr, Zero, UnBlank}			c2;
	expected ¬ 0,						c3;

	address ¬ 90,						c1;
	address ¬ address LRot8, {9000}				c2;
	address10 ¬ address + 10, {9010}			c3;
	
MainLoop:
	Noop,							c1;
	Noop,							c2;
	Noop,							c3;

{------------------------------------------------------------------------------------}
FirstLoop:
	Noop,							c1;
	Noop,							c2;
	Noop,							c3;

FirstScc0:
	Noop,							c1;
	Noop,							c2;
	rhAddr ¬ 0, {Scc0: 09000}				c3;

	IO ¬ [rhAddr, address+00], {WR0B/A}			c1;
	MDR ¬ 2, {Shift Left (ADR0 is ignored)}			c2;
	Noop,							c3;
	
	IO ¬ [rhAddr, address+09], {WR9x}			c1;
	MDR ¬ 0C2, {Reset, NV}					c2;
	Noop,							c3;
	
Scc0IntVector:
	IO ¬ [rhAddr, address10 + 02], {Interrupt Vector}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address10 + 02], {Interrupt Vector}	c1;
	Noop,							c2;
	found ¬ MD,						c3;
	
	[] ¬ found xor expected, NZeroBr,			c1;
	BRANCH[$, Scc0IntVecFailed],				c2;
	Noop,							c3;

Scc0ChanBLSB:
	IO ¬ [rhAddr, address + 0C], {Baud Rate Gen, LSB}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address + 0C], {Baud Rate Gen, LSB}	c1;
	Noop,							c2;
	found ¬ MD,						c3;
	
	[] ¬ found xor expected, NZeroBr,			c1;
	BRANCH[$, Scc0ChanBLSBFailed],				c2;
	Noop,							c3;

Scc0ChanBMSB:
	IO ¬ [rhAddr, address + 0D], {Baud Rate Gen, MSB}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address + 0D], {Baud Rate Gen, MSB}	c1;
	Noop,							c2;
	found ¬ MD,						c3;
	
	[] ¬ found xor expected, NZeroBr,			c1;
	BRANCH[$, Scc0ChanBMSBFailed],				c2;
	Noop,							c3;

Scc0ChanALSB:
	IO ¬ [rhAddr, address10 + 0C], {Baud Rate Gen, LSB}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address10 + 0C], {Baud Rate Gen, LSB}	c1;
	Noop,							c2;
	found ¬ MD,						c3;
	
	[] ¬ found xor expected, NZeroBr,			c1;
	BRANCH[$, Scc0ChanALSBFailed],				c2;
	Noop,							c3;

Scc0ChanAMSB:
	IO ¬ [rhAddr, address10 + 0D], {Baud Rate Gen, MSB}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address10 + 0D], {Baud Rate Gen, MSB}	c1;
	Noop,							c2;
	found ¬ MD,						c3;
	
	[] ¬ found xor expected, NZeroBr,			c1;
	BRANCH[$, Scc0ChanAMSBFailed],				c2;
	Noop,							c3;

FirstScc1:
	Noop,							c1;
	Noop,							c2;
	rhAddr ¬ 1, {Scc1: 19000}				c3;

	IO ¬ [rhAddr, address+00], {WR0B/A}			c1;
	MDR ¬ 2, {Shift Left (ADR0 is ignored)}			c2;
	Noop,							c3;
	
	IO ¬ [rhAddr, address+09], {WR9x}			c1;
	MDR ¬ 0C2, {Reset, NV}					c2;
	Noop,							c3;

Scc1IntVector:
	IO ¬ [rhAddr, address10 + 02], {Interrupt Vector}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address10 + 02], {Interrupt Vector}	c1;
	Noop,							c2;
	found ¬ MD,						c3;
	
	[] ¬ found xor expected, NZeroBr,			c1;
	BRANCH[$, Scc1IntVecFailed],				c2;
	Noop,							c3;

Scc1ChanBLSB:
	IO ¬ [rhAddr, address + 0C], {Baud Rate Gen, LSB}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address + 0C], {Baud Rate Gen, LSB}	c1;
	Noop,							c2;
	found ¬ MD,						c3;
	
	[] ¬ found xor expected, NZeroBr,			c1;
	BRANCH[$, Scc1ChanBLSBFailed],				c2;
	Noop,							c3;

Scc1ChanBMSB:
	IO ¬ [rhAddr, address + 0D], {Baud Rate Gen, MSB}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address + 0D], {Baud Rate Gen, MSB}	c1;
	Noop,							c2;
	found ¬ MD,						c3;
	
	[] ¬ found xor expected, NZeroBr,			c1;
	BRANCH[$, Scc1ChanBMSBFailed],				c2;
	Noop,							c3;

Scc1ChanALSB:
	IO ¬ [rhAddr, address10 + 0C], {Baud Rate Gen, LSB}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address10 + 0C], {Baud Rate Gen, LSB}	c1;
	Noop,							c2;
	found ¬ MD,						c3;
	
	[] ¬ found xor expected, NZeroBr,			c1;
	BRANCH[$, Scc1ChanALSBFailed],				c2;
	Noop,							c3;

Scc1ChanAMSB:
	IO ¬ [rhAddr, address10 + 0D], {Baud Rate Gen, MSB}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address10 + 0D], {Baud Rate Gen, MSB}	c1;
	Noop,							c2;
	found ¬ MD,						c3;
	
	[] ¬ found xor expected, NZeroBr,			c1;
	BRANCH[$, Scc1ChanAMSBFailed],				c2;
	Noop,							c3;

FirstScc2:
	Noop,							c1;
	Noop,							c2;
	rhAddr ¬ 2, {Scc2: 29000}				c3;

	IO ¬ [rhAddr, address+00], {WR0B/A}			c1;
	MDR ¬ 2, {Shift Left (ADR0 is ignored)}			c2;
	Noop,							c3;
	
	IO ¬ [rhAddr, address+09], {WR9x}			c1;
	MDR ¬ 0C2, {Reset, NV}					c2;
	Noop,							c3;

Scc2IntVector:
	IO ¬ [rhAddr, address10 + 02], {Interrupt Vector}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address10 + 02], {Interrupt Vector}	c1;
	Noop,							c2;
	found ¬ MD,						c3;
	
	[] ¬ found xor expected, NZeroBr,			c1;
	BRANCH[$, Scc2IntVecFailed],				c2;
	Noop,							c3;

Scc2ChanBLSB:
	IO ¬ [rhAddr, address + 0C], {Baud Rate Gen, LSB}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address + 0C], {Baud Rate Gen, LSB}	c1;
	Noop,							c2;
	found ¬ MD,						c3;
	
	[] ¬ found xor expected, NZeroBr,			c1;
	BRANCH[$, Scc2ChanBLSBFailed],				c2;
	Noop,							c3;

Scc2ChanBMSB:
	IO ¬ [rhAddr, address + 0D], {Baud Rate Gen, MSB}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address + 0D], {Baud Rate Gen, MSB}	c1;
	Noop,							c2;
	found ¬ MD,						c3;
	
	[] ¬ found xor expected, NZeroBr,			c1;
	BRANCH[$, Scc2ChanBMSBFailed],				c2;
	Noop,							c3;

Scc2ChanALSB:
	IO ¬ [rhAddr, address10 + 0C], {Baud Rate Gen, LSB}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address10 + 0C], {Baud Rate Gen, LSB}	c1;
	Noop,							c2;
	found ¬ MD,						c3;
	
	[] ¬ found xor expected, NZeroBr,			c1;
	BRANCH[$, Scc2ChanALSBFailed],				c2;
	Noop,							c3;

Scc2ChanAMSB:
	IO ¬ [rhAddr, address10 + 0D], {Baud Rate Gen, MSB}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address10 + 0D], {Baud Rate Gen, MSB}	c1;
	Noop,							c2;
	found ¬ MD,						c3;
	
	[] ¬ found xor expected, NZeroBr,			c1;
	BRANCH[$, Scc2ChanAMSBFailed],				c2;
	Noop,							c3;

FirstScc3:
	Noop,							c1;
	Noop,							c2;
	rhAddr ¬ 3, {Misc/Timers: 39000}			c3;

	IO ¬ [rhAddr, address+00], {WR0B/A}			c1;
	MDR ¬ 2, {Shift Left (ADR0 is ignored)}			c2;
	Noop,							c3;
	
	IO ¬ [rhAddr, address+09], {WR9x}			c1;
	MDR ¬ 0C2, {Reset, NV}					c2;
	Noop,							c3;

Scc3IntVector:
	IO ¬ [rhAddr, address10 + 02], {Interrupt Vector}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address10 + 02], {Interrupt Vector}	c1;
	Noop,							c2;
	found ¬ MD,						c3;
	
	[] ¬ found xor expected, NZeroBr,			c1;
	BRANCH[$, Scc3IntVecFailed],				c2;
	Noop,							c3;

Scc3ChanBLSB:
	IO ¬ [rhAddr, address + 0C], {Baud Rate Gen, LSB}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address + 0C], {Baud Rate Gen, LSB}	c1;
	Noop,							c2;
	found ¬ MD,						c3;
	
	[] ¬ found xor expected, NZeroBr,			c1;
	BRANCH[$, Scc3ChanBLSBFailed],				c2;
	Noop,							c3;

Scc3ChanBMSB:
	IO ¬ [rhAddr, address + 0D], {Baud Rate Gen, MSB}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address + 0D], {Baud Rate Gen, MSB}	c1;
	Noop,							c2;
	found ¬ MD,						c3;
	
	[] ¬ found xor expected, NZeroBr,			c1;
	BRANCH[$, Scc3ChanBMSBFailed],				c2;
	Noop,							c3;

Scc3ChanALSB:
	IO ¬ [rhAddr, address10 + 0C], {Baud Rate Gen, LSB}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address10 + 0C], {Baud Rate Gen, LSB}	c1;
	Noop,							c2;
	found ¬ MD,						c3;
	
	[] ¬ found xor expected, NZeroBr,			c1;
	BRANCH[$, Scc3ChanALSBFailed],				c2;
	Noop,							c3;

Scc3ChanAMSB:
	IO ¬ [rhAddr, address10 + 0D], {Baud Rate Gen, MSB}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

	IO ¬ [rhAddr, address10 + 0D], {Baud Rate Gen, MSB}	c1;
	Noop,							c2;
	found ¬ MD,						c3;
	
	[] ¬ found xor expected, NZeroBr,			c1;
	BRANCH[$, Scc3ChanAMSBFailed],				c2;
	Noop,							c3;

FirstLoopEnd:
	Noop,							c1;
	expected ¬ expected + 1, PgCarryBr,			c2;
	expected ¬ expected and 0FF, BRANCH[FirstLoop, $],	c3;

{------------------------------------------------------------------------------------}
SecondSection:
	expected ¬ 0,						c1;
	Noop,							c2;
	Noop,							c3;

SecondScc0:
	Noop,							c1;
	Noop,							c2;
	rhAddr ¬ 0, {Scc0: 09000}				c3;

	IO ¬ [rhAddr, address10 + 02], {Interrupt Vector}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

SecondScc1:
	Noop,							c1;
	Noop,							c2;
	rhAddr ¬ 1, {Scc1: 19000}				c3;

	IO ¬ [rhAddr, address10 + 02], {Interrupt Vector}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

SecondScc2:
	Noop,							c1;
	Noop,							c2;
	rhAddr ¬ 2, {Scc2: 29000}				c3;

	IO ¬ [rhAddr, address10 + 02], {Interrupt Vector}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

SecondScc3:
	Noop,							c1;
	Noop,							c2;
	rhAddr ¬ 3, {Scc3: 39000}				c3;

	IO ¬ [rhAddr, address10 + 02], {Interrupt Vector}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

SecondLoop:
	Noop,							c1;
	Noop,							c2;
	Noop,							c3;

SecondScc0Test:
	Noop,							c1;
	Noop,							c2;
	rhAddr ¬ 0, {Scc0: 09000}				c3;

	IO ¬ [rhAddr, address10 + 02], {Interrupt Vector}	c1;
	Noop,							c2;
	found ¬ MD,						c3;
	
	[] ¬ found xor expected, NZeroBr,			c1;
	BRANCH[$, Scc0IntVecMashed],				c2;
	Noop,							c3;

	IO ¬ [rhAddr, address10 + 02], {Interrupt Vector}	c1;
	MDR ¬ expected + 1,					c2;
	Noop,							c3;

SecondScc1Test:
	Noop,							c1;
	Noop,							c2;
	rhAddr ¬ 1, {Scc1: 19000}				c3;

	IO ¬ [rhAddr, address10 + 02], {Interrupt Vector}	c1;
	Noop,							c2;
	found ¬ MD,						c3;
	
	[] ¬ found xor expected, NZeroBr,			c1;
	BRANCH[$, Scc1IntVecMashed],				c2;
	Noop,							c3;

	IO ¬ [rhAddr, address10 + 02], {Interrupt Vector}	c1;
	MDR ¬ expected + 1,					c2;
	Noop,							c3;

SecondScc2Test:
	Noop,							c1;
	Noop,							c2;
	rhAddr ¬ 2, {Scc2: 29000}				c3;

	IO ¬ [rhAddr, address10 + 02], {Interrupt Vector}	c1;
	Noop,							c2;
	found ¬ MD,						c3;
	
	[] ¬ found xor expected, NZeroBr,			c1;
	BRANCH[$, Scc2IntVecMashed],				c2;
	Noop,							c3;

	IO ¬ [rhAddr, address10 + 02], {Interrupt Vector}	c1;
	MDR ¬ expected + 1,					c2;
	Noop,							c3;

SecondScc3Test:
	Noop,							c1;
	Noop,							c2;
	rhAddr ¬ 3, {Scc3: 39000}				c3;

	IO ¬ [rhAddr, address10 + 02], {Interrupt Vector}	c1;
	Noop,							c2;
	found ¬ MD,						c3;
	
	[] ¬ found xor expected, NZeroBr,			c1;
	BRANCH[$, Scc3IntVecMashed],				c2;
	Noop,							c3;

	IO ¬ [rhAddr, address10 + 02], {Interrupt Vector}	c1;
	MDR ¬ expected + 1,					c2;
	Noop,							c3;

SecondLoopEnd:
	Noop,							c1;
	expected ¬ expected + 1, PgCarryBr,			c2;
	expected ¬ expected and 0FF, BRANCH[SecondLoop, $],	c3;

	ExtCtrl ¬ 3, {Gets Bumped on rising edge} 		c1;
	ExtCtrl ¬ 7,						c2;
	passCount ¬ passCount + 1, GOTO[MainLoop],		c3;
	
{------------------------------------------------------------------------------------}
WriteLoop:
	IO ¬ [rhAddr, address + 02], {Port A Interrupt Vector}	c1;
	MDR ¬ expected,						c2;
	Noop,							c3;

	Noop,  c1;	Noop,  c2;	Noop,  c3;
	Noop,  c1;	Noop,  c2;	Noop,  c3;
	Noop,  c1;	Noop,  c2;	Noop,  c3;
	Noop,  c1;	Noop,  c2;	Noop,  c3;
	Noop,  c1;	Noop,  c2;	Noop,  c3;

	Noop,							c1;
	Noop,							c2;
	expected ¬ expected + 1, GOTO[WriteLoop],		c3;

{------------------------------------------------------------------------------------}

	
Scc0IntVecFailed:	GOTO[Restart],				c3;
Scc0ChanBLSBFailed:	GOTO[Restart],				c3;
Scc0ChanBMSBFailed:	GOTO[Restart],				c3;
Scc0ChanALSBFailed:	GOTO[Restart],				c3;
Scc0ChanAMSBFailed:	GOTO[Restart],				c3;

Scc1IntVecFailed:	GOTO[Restart],				c3;
Scc1ChanBLSBFailed:	GOTO[Restart],				c3;
Scc1ChanBMSBFailed:	GOTO[Restart],				c3;
Scc1ChanALSBFailed:	GOTO[Restart],				c3;
Scc1ChanAMSBFailed:	GOTO[Restart],				c3;

Scc2IntVecFailed:	GOTO[Restart],				c3;
Scc2ChanBLSBFailed:	GOTO[Restart],				c3;
Scc2ChanBMSBFailed:	GOTO[Restart],				c3;
Scc2ChanALSBFailed:	GOTO[Restart],				c3;
Scc2ChanAMSBFailed:	GOTO[Restart],				c3;

Scc3IntVecFailed:	GOTO[Restart],				c3;
Scc3ChanBLSBFailed:	GOTO[Restart],				c3;
Scc3ChanBMSBFailed:	GOTO[Restart],				c3;
Scc3ChanALSBFailed:	GOTO[Restart],				c3;
Scc3ChanAMSBFailed:	GOTO[Restart],				c3;
	
Scc0IntVecMashed:	GOTO[Restart],				c3;
Scc1IntVecMashed:	GOTO[Restart],				c3;
Scc2IntVecMashed:	GOTO[Restart],				c3;
Scc3IntVecMashed:	GOTO[Restart],				c3;
	
Restart:
	Q ¬ 0FF,						c1;
	Noop,							c2;
RestartLoop:
	Noop,							c3;

	Q ¬ Q - 1, ZeroBr,					c1;
	BRANCH[RestartLoop, $],					c2;
	GOTO[Go],						c3;

{------------------------------------------------------------------------------------}