{DSRTest.mc, HGM, 21-Oct-85 22:33:55
Simple Test for DTR => DSR and RTS => CTS.
Also activates LoopBack clocks so everything flaps if you are looking with a scope.}
Reserve[0F5F, 0FFF]; {section used by the CP Kernel }
SetTask[0]; StartAddress[Go];
RegDef[address, R, 0];
RegDef[rhAddr, RH, 0];
RegDef[modem, R, 1];
RegDef[rhModem, RH, 1];
RegDef[mask, R, 0C];
RegDef[temp, R, 0D];
RegDef[line, R, 0E];
RegDef[chanA, U, 10];
RegDef[chanB, U, 11];
RegDef[chanC, U, 12];
RegDef[chanD, U, 13];
RegDef[chanE, U, 14];
RegDef[chanF, U, 15];
RegDef[chanG, U, 16];
RegDef[chanH, U, 17];
Trap: temp ← RRot1 ErrnIBnStkp, ClrIntErr, c1, at[0];
Xbus ← temp LRot0, XwdDisp, c2;
DISP2[TrapType], c3;
Parity: GOTO[GoToGo], c1, at[0,4,TrapType];
Init: GOTO[GoToGo], c1, at[1,4,TrapType];
Stack: GOTO[GoToGo], c1, at[2,4,TrapType];
IB: GOTO[GoToGo], c1, at[3,4,TrapType];
GoToGo:
Noop, c2;
GOTO[Go], c3;
{Initialize all those registers}
Go: line ← 0, c1;
Noop, c2;
ExtCtrl ← 5, {Init Incr, Zero, UnBlank} c3;
address ← 090, c1;
address ← address LRot8, {9000} c2;
Noop, c3;
Q ← address + 10, c1;
chanA ← Q, c2;
Noop, c3;
Q ← address + 00, c1;
chanB ← Q, c2;
Noop, c3;
Q ← address + 11, c1;
chanC ← Q, c2;
Noop, c3;
Q ← address + 01, c1;
chanD ← Q, c2;
Noop, c3;
Q ← address + 12, c1;
chanE ← Q, c2;
Noop, c3;
Q ← address + 02, c1;
chanF ← Q, c2;
Noop, c3;
Q ← address + 13, c1;
chanG ← Q, c2;
Noop, c3;
Q ← address + 03, c1;
chanH ← Q, c2;
Noop, c3;
InitFirstClock:
{Clock for first chip runs at 56KB. 56KB => 17.857 microseconds/bit.
A count of 00BH gives 56,846 bits/second. (measured)}
rhModem ← 2, {Modem drives LCa'} c1;
modem ← 10, c2;
modem ← modem LRot8 {21000}, c3;
IO ← [rhModem, modem + 0], {Master Interrupt Control} c1;
MDR ← 0, c2;
Noop, c3;
IO ← [rhModem, modem + 1], {Master Config Control} c1;
MDR ← 014, {Enable PortA, PortC, and Cnt3} c2;
temp ← modem + 10, c3;
IO ← [rhModem, temp + 0A], {Cnt3 MSB} c1;
MDR ← 0, c2;
Noop, c3;
IO ← [rhModem, temp + 0B], {Cnt3 LSB} c1;
MDR ← 0B, c2;
Noop, c3;
IO ← [rhModem, temp + 0E], {Cnt3 Mode} c1;
MDR ← 0C2, {Sq out} c2;
Noop, c3;
IO ← [rhModem, modem + 0C], {Cnt3 Cmd} c1;
MDR ← 06, {Go} c2;
Noop, c3;
IO ← [rhModem, modem + 06], {Port C Direction} c1;
MDR ← 0FE, {Bit 0 ← output} c2;
Q ← 23, c3;
IO ← [rhModem, modem + Q], {Port A Direction} c1;
MDR ← 0FF, {All In} c2;
Q ← 22, c3;
IO ← [rhModem, modem + Q], {Port A Polarity} c1;
MDR ← 0FF, {All Inverted} c2;
Q ← 20, c3;
IO ← [rhModem, modem + Q], {Port A Mode} c1;
MDR ← 00, {Simple Bit Port} c2;
Noop, c3;
InitSecondClock:
{Clock for second chip runs at 9600. 9600 => 104 microseconds/bit.
A count of 041H gives 9,621 bits/second. (measured)}
rhAddr ← 4, {Dialer0 drives LCb'} c1;
address ← 10, c2;
address ← address LRot8 {41000}, c3;
IO ← [rhAddr, address + 0], {Master Interrupt Control} c1;
MDR ← 0, c2;
Noop, c3;
IO ← [rhAddr, address + 1], {Master Config Control} c1;
MDR ← 010, {Enable PortC and Cnt3} c2;
temp ← address + 10, c3;
IO ← [rhAddr, temp + 0A], {Cnt3 MSB} c1;
MDR ← 0, c2;
Noop, c3;
IO ← [rhAddr, temp + 0B], {Cnt3 LSB} c1;
MDR ← 041, c2;
Noop, c3;
IO ← [rhAddr, temp + 0E], {Cnt3 Mode} c1;
MDR ← 0C2, {Sq out} c2;
Noop, c3;
IO ← [rhAddr, address + 0C], {Cnt3 Cmd} c1;
MDR ← 06, {Go} c2;
Noop, c3;
IO ← [rhAddr, address + 06], {Port C Direction} c1;
MDR ← 0FE, {Bit 0 ← output} c2;
Noop, c3;
InitThirdClock:
{Clock for third chip runs at 9600. 9600 => 104 microseconds/bit.
A count of 041H gives 9,621 bits/second. (measured)}
rhAddr ← 5, {Dialer1 drives LCc'} c1;
address ← 10, c2;
address ← address LRot8 {51000}, c3;
IO ← [rhAddr, address + 0], {Master Interrupt Control} c1;
MDR ← 0, c2;
Noop, c3;
IO ← [rhAddr, address + 1], {Master Config Control} c1;
MDR ← 010, {Enable PortC and Cnt3} c2;
temp ← address + 10, c3;
IO ← [rhAddr, temp + 0A], {Cnt3 MSB} c1;
MDR ← 0, c2;
Noop, c3;
IO ← [rhAddr, temp + 0B], {Cnt3 LSB} c1;
MDR ← 041, c2;
Noop, c3;
IO ← [rhAddr, temp + 0E], {Cnt3 Mode} c1;
MDR ← 0C2, {Sq out} c2;
Noop, c3;
IO ← [rhAddr, address + 0C], {Cnt3 Cmd} c1;
MDR ← 06, {Go} c2;
Noop, c3;
IO ← [rhAddr, address + 06], {Port C Direction} c1;
MDR ← 0FE, {Bit 0 ← output} c2;
Noop, c3;
InitLastClock:
{Clock for 4th chip runs at 9600. 9600 => 104 microseconds/bit.
A count of 041H gives 9,621 bits/second. (measured)}
rhAddr ← 6, {Dialer2 drives LCd'} c1;
address ← 10, c2;
address ← address LRot8 {61000}, c3;
IO ← [rhAddr, address + 0], {Master Interrupt Control} c1;
MDR ← 0, c2;
Noop, c3;
IO ← [rhAddr, address + 1], {Master Config Control} c1;
MDR ← 010, {Enable PortC and Cnt3} c2;
temp ← address + 10, c3;
IO ← [rhAddr, temp + 0A], {Cnt3 MSB} c1;
MDR ← 0, c2;
Noop, c3;
IO ← [rhAddr, temp + 0B], {Cnt3 LSB} c1;
MDR ← 041, c2;
Noop, c3;
IO ← [rhAddr, temp + 0E], {Cnt3 Mode} c1;
MDR ← 0C2, {Sq out} c2;
Noop, c3;
IO ← [rhAddr, address + 0C], {Cnt3 Cmd} c1;
MDR ← 06, {Go} c2;
Noop, c3;
IO ← [rhAddr, address + 06], {Port C Direction} c1;
MDR ← 0FE, {Bit 0 ← output} c2;
Noop, c3;
ScopeSyncPoint:
address ← chanB, rhAddr ← chanB, c1;
address ← address and ~0FF, c2;
rhAddr ← 6, {DES Chip, Byte mode} c3;
IO ← [rhAddr, address+01], {Command} c1;
MDR ← 00, {Reset} c2;
Noop, c3;
InitScc0:
address ← chanB, rhAddr ← chanB, c1;
address ← address and ~0F, c2;
Noop, c3;
IO ← [rhAddr, address+00], {WR0B/A} c1;
MDR ← 2, {Shift Left (ADR0 is ignored)} c2;
Noop, c3;
IO ← [rhAddr, address+09], {WR9x} c1;
MDR ← 0C9, {Reset, MIE, V, VIS} c2;
Noop, c3;
IO ← [rhAddr, address+02], {WR2x} c1;
MDR ← 080, {Int Vector} c2;
Noop, c3;
InitScc1:
address ← chanD, rhAddr ← chanD, c1;
address ← address and ~0F, c2;
Noop, c3;
IO ← [rhAddr, address+00], {WR0B/A} c1;
MDR ← 2, {Shift Left (ADR0 is ignored)} c2;
Noop, c3;
IO ← [rhAddr, address+09], {WR9x} c1;
MDR ← 0C9, {Reset, MIE, V, VIS} c2;
Noop, c3;
IO ← [rhAddr, address+02], {WR2x} c1;
MDR ← 090, {Int Vector} c2;
Noop, c3;
InitScc2:
address ← chanF, rhAddr ← chanF, c1;
address ← address and ~0F, c2;
Noop, c3;
IO ← [rhAddr, address+00], {WR0B/A} c1;
MDR ← 2, {Shift Left (ADR0 is ignored)} c2;
Noop, c3;
IO ← [rhAddr, address+09], {WR9x} c1;
MDR ← 0C9, {Reset, MIE, V, VIS} c2;
Noop, c3;
IO ← [rhAddr, address+02], {WR2x} c1;
MDR ← 0A0, {Int Vector} c2;
Noop, c3;
InitScc3:
address ← chanH, rhAddr ← chanH, c1;
address ← address and ~0F, c2;
Noop, c3;
IO ← [rhAddr, address+00], {WR0B/A} c1;
MDR ← 2, {Shift Left (ADR0 is ignored)} c2;
Noop, c3;
IO ← [rhAddr, address+09], {WR9x} c1;
MDR ← 0C9, {Reset, MIE, V, VIS} c2;
Noop, c3;
IO ← [rhAddr, address+02], {WR2x} c1;
MDR ← 0B0, {Int Vector} c2;
Noop, c3;
InitAllChips:
temp ← 01, L0 ← 07, {WR1X} c1;
Q ← 12, {Rx All Int, Tx Int En} c2;
CALL[SendToAll], c3;
temp ← 04, L0 ← 08, {WR4x} c1, at[07,10,SendAllRet];
Q ← 04A, {16xClock, 2 Stop Bits} c2;
CALL[SendToAll], c3;
temp ← 03, L0 ← 09, {WR3x} c1, at[08,10,SendAllRet];
Q ← 0C1, {8bits/char, RxE} c2;
CALL[SendToAll], c3;
temp ← 05, L0 ← 0A, {WR5x} c1, at[09,10,SendAllRet];
Q ← 0EA, {DTR, 8bits/char, TxE, RTS} c2;
CALL[SendToAll], c3;
{TC ← (PClk/(2*F))-2, Can't set it if it's active}
temp ← 0C, L0 ← 0B, {WR12x} c1, at[0A,10,SendAllRet];
Q ← 06, {Low byte of time constant} c2;
CALL[SendToAll], c3;
temp ← 0D, L0 ← 0C, {WR13x} c1, at[0B,10,SendAllRet];
Q ← 0, {High byte of time constant ← 0} c2;
CALL[SendToAll], c3;
temp ← 0E, L0 ← 0D, {WR14x} c1, at[0C,10,SendAllRet];
Q ← 3, {Enable Baud Rate Gen from PClk} c2;
CALL[SendToAll], c3;
temp ← 0B, L0 ← 0E, {WR11x} c1, at[0D,10,SendAllRet];
Q ← 050, {Clocks from BR Gen} c2;
CALL[SendToAll], c3;
temp ← 0F, L0 ← 0F, {WR15x} c1, at[0E,10,SendAllRet];
Q ← 000, {No ints (let CTS flow through)} c2;
CALL[SendToAll], c3;
mask ← 80, c1, at[0F,10,SendAllRet];
Noop, c2;
GOTO[MainLoop], c3;
{-------------------------------------------}
MainLoop:
Ybus ← line, AltUaddr, c1;
temp ← chanA, c2;
Noop, c3;
address ← temp, rhAddr ← temp LRot0, c1;
address ← address and ~0F, c2;
Noop, c3;
SetRTS:
IO ← [rhAddr, address+05], {WR5} c1;
MDR ← 0EA, {DTR, 8bits/char, TxE, RTS} c2;
Noop, c3;
CheckCTSSet:
IO ← [rhAddr, address+00], {RR0} c1;
Noop, c2;
Q ← MD, c3;
temp ← Q and 020, c1;
[] ← temp, ZeroBr, c2;
BRANCH[$, CTSNotSet], c3;
ClearRTS:
IO ← [rhAddr, address+05], {WR5} c1;
MDR ← 0E8, {DTR, 8bits/char, TxE, ~RTS} c2;
Noop, c3;
CheckCTSClear:
IO ← [rhAddr, address+00], {RR0} c1;
Noop, c2;
Q ← MD, c3;
temp ← Q and 020, c1;
[] ← temp, NZeroBr, c2;
BRANCH[$, CTSNotClear], c3;
SetDTR:
IO ← [rhAddr, address+05], {WR5} c1;
MDR ← 0EA, {DTR, 8bits/char, TxE, RTS} c2;
Noop, c3;
CheckDSRSet:
IO ← [rhModem, modem+0D], {Port A Data} c1;
Noop, c2;
Q ← MD, c3;
temp ← Q and mask, c1;
[] ← temp, ZeroBr, c2;
BRANCH[$, DSRNotSet], c3;
ClearDTR:
IO ← [rhAddr, address+05], {WR5} c1;
MDR ← 06A, {~DTR, 8bits/char, TxE, RTS} c2;
Noop, c3;
CheckDSRClear:
IO ← [rhModem, modem+0D], {Port A Data} c1;
Noop, c2;
Q ← MD, c3;
temp ← Q and mask, c1;
[] ← temp, NZeroBr, c2;
BRANCH[$, DSRNotClear], c3;
line ← line + 1, c1;
line ← line and 7, ZeroBr, c2;
mask ← mask RShift1, BRANCH[MainLoop, $], c3;
ExtCtrl ← 3, {Gets Bumped on rising edge} c1;
ExtCtrl ← 7, c2;
mask ← 80, GOTO[MainLoop], c3;
{-------------------------------------------}
CTSNotSet:
Noop, c1;
Noop, c2;
GOTO[MainLoop], c3;
CTSNotClear:
Noop, c1;
Noop, c2;
GOTO[MainLoop], c3;
DSRNotSet:
Noop, c1;
Noop, c2;
GOTO[MainLoop], c3;
DSRNotClear:
Noop, c1;
Noop, c2;
GOTO[MainLoop], c3;
{-------------------------------------------}
SendToAll:
address ← chanA, rhAddr ← chanA, c1;
address ← address and ~0F, c2;
Noop, c3;
IO ← [rhAddr, address+temp], c1;
MDR ← Q, c2;
Noop, c3;
address ← chanB, rhAddr ← chanB, c1;
address ← address and ~0F, c2;
Noop, c3;
IO ← [rhAddr, address+temp], c1;
MDR ← Q, c2;
Noop, c3;
address ← chanC, rhAddr ← chanC, c1;
address ← address and ~0F, c2;
Noop, c3;
IO ← [rhAddr, address+temp], c1;
MDR ← Q, c2;
Noop, c3;
address ← chanD, rhAddr ← chanD, c1;
address ← address and ~0F, c2;
Noop, c3;
IO ← [rhAddr, address+temp], c1;
MDR ← Q, c2;
Noop, c3;
address ← chanE, rhAddr ← chanE, c1;
address ← address and ~0F, c2;
Noop, c3;
IO ← [rhAddr, address+temp], c1;
MDR ← Q, c2;
Noop, c3;
address ← chanF, rhAddr ← chanF, c1;
address ← address and ~0F, c2;
Noop, c3;
IO ← [rhAddr, address+temp], c1;
MDR ← Q, c2;
Noop, c3;
address ← chanG, rhAddr ← chanG, c1;
address ← address and ~0F, c2;
Noop, c3;
IO ← [rhAddr, address+temp], c1;
MDR ← Q, c2;
Noop, c3;
address ← chanH, rhAddr ← chanH, c1;
address ← address and ~0F, c2;
Noop, c3;
IO ← [rhAddr, address+temp], c1;
MDR ← Q, L0Disp, c2;
DISP4[SendAllRet], c3;