XEROXPALO ALTO RESEARCH CENTERComputer Science LaboratoryApril, 1973 - CSL Archieve # 3AL-038retyped November 7, 1978To:Alto GroupFrom:C. ThackerSubject:Alto InterfacesThis memo is in response to the request for a description of the Alto I/O system. Familiaritywith the Alto is assumed1.There are two basic ways in which I/O devices may be connected to the Alto. A device mayappear to a program as one or more memory locations in the range 177000-177777, in whichcase it responds to addresses from MAR, for its selection, and transfers data on the memorydata bus, MD(00)'-MD(15)'. Alternatively, a device may connect directly to the processor bus,and be selected by task-specific F1 or F2 signals. The latter interface will usually have itsown task microcode, and will be used only for high speed devices (> 1K words/sec). Thememory bus interface will usually be used for slow peripherals which can be driven by a"Nova" program, although nothing prohibits mixing the interface methods, i.e., a memorybus device can have its own microcode task.Memory BusThe memory bus signals are:MD(00)'-MD(15)'Memory data. These lines are low true, bidirectional, opencollector. They should be driven by 74H01 or 7438gates, and should be received with onto TTL load, tominimize total capacitance.MAR(07)-MAR(14),XMAR(15)Memory address. These lines are the outputs of thememory address register. They are high true, and shouldbe only lightly loaded.XIOREFThis signal indicates that an I/O reference (address>177000) is in progress. It is the AND of MAR(00)-MAR(06). The processor does not check parity on I/Oreferences.XMT2This signal indicates the transfer cycle (170ns) of amemory reference is in progress. On a fetch, theprocessor strobes data during the last 25ns of XMT2.During a store, data is valid during the last 90ns of XMT2,and for approximately 15ns thereafter.MISYSCLKThis signal is the memory interface's version ot the systemclock. It is true during the last 25ns of everymicroinstruction.1See Alto: A Personal Computer System - C. Thacker, E. McCreightc Xerox Corporation 1979]hp[qZrXs$WRtu s Outu s Ltu sHl<"F~G F~CtYA;@jT>7'=`Z;).:V-*8*-7L+4Bq {18s..qt /j,j+4j*/'%qtj%!j$c!Yqt!4j %j+jZ Pqt 3 j 1j#ju'j& qt)j90jH#d? >R`*!! pqXr! ya2The timing of a memory cycle is shown in Figure 1. The memory address register is loadedat the end of a cycle in which a MAR-microinstruction is executed. The next four cycles, X,0, 1, 2 comprise the memory cycle. Data is transferred during MT2, and will be stored if themicroinstruction executed during MT2 is MD_, feteched if the microinstruction specifies_MD.Due to critical timing restrictions, I/O devices do not use the normal signals which indicate,during MT2, whether a store or a fetch is being done. Instead, the address determines thenature of the reference, and fetches are directed only to addresses capable of deliveringdata, stores are directed only to addresses capable of accepting data.Whenever an I/O device capable of delivering data detects its address, it places data on thememory bus. If it needs to know that the reference is finished, (to clear a buffer fullindicator, for example) it uses XMT2 for this purpose.Devices which accept stores should be designed to clock data from MD' on the falling edgeof XMT2, or, if latches are used, to load them with ADDRESS DETECTED.XMT2.MISYSCLK.<==<==<<170 ns.<>WAKEn'nACT'Time Betweenwakeup requestand task activationdepends on require-ments of higherpriority tasksqMicrocodeservicesrequest,and wake-up requestis removedqMicrocodeexecutesTASKfunctionTask remainsactive for one additionalcycleFigure 2: WAKEUP TIMINGCQv#Ms7"#K5'#JY#HW#G #DT #B{)1#@=#?qF#RS tN$9 N$9N$9N$9(N$91sN$9$9 $9 |2 9$t 9| $] t r  Vp  ! * 0t 9*2$*$22$)91s94:V4:94:)U1sN$*$*N$0U4:r4:U4:9pd G5W$|2y$v 8>t $ 9 $  $  $ : $ & $ - $ 4: $ : $ U k Uk UVk&VVk&VkU:k Ok9 k:W k:Wrk 8$=:e9$:|0ey$3t     r V U kG U $ 9G $G%| 2&V$#$!Vt !V!V!V !Vr !VV . $0 $0W|O,st ,s,s,s: $G4: $G4: kG4: 4: 4:4:rpd. k$# k$ d8$ " AE3Next(05)'-Next(09)'The NEXT bus is a low true, open collector bus whichspecifies the address of the microinstruction which will befeteched from the control memory during the next cycleand executed during the cycle following that. Branchesare done in the Alto by Oring onto this bus, and the low 5bits of the NEXT bus are provided on the backplane forthis purpose.By convention, branches are usually controlled by F2's. Atypical instruction sequence for a branch function whichORs a 1 into NEXT(09) if its condition is true is:!1,2,No,Yes;assembler directive specifying that;YES should be in an odd location, NO;in an even locationBRANCHFUNCTION;During the execution of this;instruction, the NEXT bus contains;the address specified by the following;instruction (i.e. NO). If the branch;condition is true, the NEXT bus;contains NO+1:NO;colon is the assembler syntax for;specifying the address of the;subsequent instruction.NO: mumble;get here on failure.YES: foo;get here on success.F1(0)-F1(3),F2(0)-F2(3)These lines are the outputs of MIR. By convention, F1'sand F2's from 0-7 are task independent, those from 10B to17B are interpreted according to the active task. Theselines are stable for the entire cycle, and change atapproximately -15ns. Because these lines can changeduring the system clock, they should be buffered in a latchif they are used to gate other clocks (see figure 3).<==0\#vRq@t* Qa8P$ )NM8Lm!K0 H#Gy"F2Cq @t$@A%@@L=Bq @t@;#@:'@9g&@8*@6 3q@t"@2^@0-q @t*q@t'q@t3@&~1@%A%@$ * @"@!;@ )" s.q0t!d8 9]=t9$| t l |  ,   y y, y H y e y  y  y  y t l l N  NH N Br$ y H$   %$  %$ @ P 3      y$ly$ zy$l 3 $^$ $z$ 9$r$V |, H,  $ $ $$ $d e$t  ,z  %G$s%$ ,$ 9$: $: $@ $  llP3# 9p]$yr$c+4the bus no later than 80ns into a cycle, and will remainstable until the end of the cycle.StartThis signal is generated when the emulator executes theSIO instruction. This signal is true for an entire cycle,and during the cycle, ACO is placed on the bus. The bitsof the bus may be used for arbitrary control functions.OKTORUNThis signal is provided for devices which requireinitialization. It remains false from the time power isturned on until +5v is at nominal level, and the bootstrapbutton has been pressed and released. When power isestablished, OKTORUN follows the bootstrap button.SYSCLK and ARCThese are the two versions of the system clock. SYSCLKoccurs at the end of every microinstruction, and is usedto load registers, etc. Some memory referencesequences may stop the processor for from one to threecycles by disabling SYSCLK. ARC (always running clock)has the same phase as SYSCLK, but is never stopped.These are the standard signals provided on the edge connectors for processor bus devices.These should be the only signals required to interface most I/O devices. For any furtherinformation, consult me. B%Zvj t#jJ"@qtj)j /jA77qt[)\j&j!j\& j2 q t &j j Sbc'j 6j(jxns'26#dh A?R&t TIMESROMANLOGO HELVETICA  HELVETICA  HELVETICA  HELVETICA TIMESROMAN TIMESROMAN  HELVETICA  HELVETICA GATES MATH  TIMESROMAN  HELVETICA  Y#B"Py:C:C"i rZ ( B "=i#B " 9eB: ;Z":#"iZ !WiW:Z": +iQB":B": +iGB":#* "B" : ;*PPB!l* "::B: ;Z":B":J"9W"iT"=#B ": C" 9B":qB)B:Z":*:B":B"i^: #: B":PP*J"PP*J":PPB"*iA":B: ;Z: ;Z"9X*J"9R"i]L"=#B " 9B: ;Z: #: B:Z"j/WaltoiNTERFACE.PRESS Swinehart18-Sep-79 8:05:07 PDT