ROUTE Program Logic ManualE. McCreightParc/CSLDraft of June 2, 1978 11:17 AMROUTE is a Bcpl program that is part of the Parc/SDD/EOD electronic design automationsystem. Its function is to combine the net lists describing a number of logic drawings thattogether describe an entire logic board, and to generate a set of wiring orders sufficient toproduce the board automatically.It has been said that a university is an otherwise unrelated set of colleges sharing a commonheating system. So it is with ROUTE. ROUTE is the current repository for a fairly largecollection of unrelated functions sharing a common net list input format and wire listoutput format. These functions are such diverse things as automatic terminator assignment,wire length minimization, and wiring order determination.ROUTE is further complicated by the necessity to carry out revisions incrementally. Thismeans, among other things, that nets must be recognized as "the same" even if net nameschange, and that terminator assignment must change as little as possible.0. Normal OperationROUTE is normally invoked from the Alto Executive with a command line like this:Route[/switches] board/B [metric/M] [exhaustive/E] [heuristic/H][boardlocation/L] file1 file2 file3 ...ROUTE normally reads a set of .nl-format files produced by the ANALYZE program andproduces several output files. If the first .nl file in the input list (file1) had the nameAARGH.nl, then the following output files would be produced* AARGH.wl, a file containing wiring orders for the stitchwelding program FAB tofabricate the board from scratch,* AARGH.re, a file containing error messages,* AARGH.bp, a file describing the external (backpanel, usually) connections of theboard, and* AARGH-x.nl, a file for each each external connector type x describing theconnections through that connector. These files are intended to be used as input forautomatic backpanel routing.If correction (revision) is specified, in addition ROUTE will read AARGH.wl and willproduce two other output files:* AARGH.wlnew, instead of AARGH.wl. That's so that if something goes awry, theoriginal AARGH.wl is unchanged and the correction can be re-run. The otheroutput file isc Xerox Corporation 1980Н²О^оpqpТфН$~О[9Н%ГОYnНєОVqТёНЇОQ'rsrТ∙Т√П9НЇОO╒Т≤ Т≥ПPНЇОNТ√ПZТ≈НЇОL≤ТНЇОIlТ│П@Т┌НЇОGГТцsrsrТдП-НЇОFbТиПVНЇОDщТ▌П'Т▐П3НЇОCXТП9НЇО@NsrТІТЇП5НЇО>иТ╔ПEТіНЇО=DТПIНЇО:qНЇО7rsrТХП@ТИ НґО3БqrqtrТюtqТаrtqrt qrtqrНґО2]tqrТtrtrtrНЇО/1srТ╪П;srНЇО-╛ТбПHtrТцНЇО,'qrТП3НґО(ШqТ≥ rПAsrНґО'vТП!НґО$Jq rП#НґО!qrТ°qrТ²П5НґО≥Т НґОmqrТЯqtqrТРП#trНґОХТ┴ПTНґОcТНЇО7ТъП4srТЮqrНЇО╡ТНґО├qТ≤rП=Т≥НґОТАП&ТБП$НґО|Т Ъ▐Ї5=7QШ,Н&ОэpqТXЪ▐&∙ЭaROUTE Program Logic Manual2* AARGH.ad, a file containing FAB wiring orders to implement the revision on thepre-existing board.The following switches have the indicated effect:c: This specifies that correction is to be done.b: This causes two .wl-format files to be produced, one containing all pins that areinitially floating, and one containing all pins trace-wired to a power plane. This isuseful for automated incoming board inspection.m: This requests Multiwire-format wiring output, suitable forsending to Photocircuits, Inc.h: This causes a list of hole positions to be produced in Multiwire-format.Photocircuits needs to know where not to put the wires, too.t: This causes a check list of trace-wired pins to be produced (not normally usefulexcept for Board debugging (see below)).The file board contains a concatenation of .BR files that collectively define all the Boardroutines (see below). The parameters exhaustive and heuristic together control the wire-routing part of ROUTE; their normal settings are 7 and 20. Better routings of long nets canbe gotten at the expense of longer running times by increasing heuristic. The metric iseither Manhattan (rectilinear) or Euclidean (as the crow flies); the default is Manhattan,which is faster. The boardlocation is a string that will be substituted for the connectorname x in the AARGH-x.nl file mentioned above.1. File Formats.1.1 .NL format.An .nl-format file is an ASCII text file that looks like this:...@...The is ASCII text preceded by a ";" and terminated by a carriage return.ANALYZE generates the comment from a piece of "boiler plate" in the drawing. Thestandard boiler plate template is known as LogicBlock.sil.The has the following format:: (//); For example,Н!ОfПrsrТёНЩН О_qТ▒ rsrТ▓П(Н О]▒ТН ОXЮП1Н ОUЄqrП/Н ОT/qrТ√П6Т≈Н ОR╙Т≤ПMТ≥Н ОQ%ТП/Н ОO═qrП<Н ОNН ОL√qrТ ТПDН ОKТП%Н+ўОJ╨Ч$Н-рОKН ОI▄qrТ°ПBТ²Н ОHТП(Н ОDшТ²trТ·ПMН ОCVТ╪П%t rТҐtrН ОAяТ░sr Т▒П8Н О@LТдП"ТеtrtrН О>гТЇqrqrТ╦qrН О=BТаtrТбП+Н О;ҐТtrqtqrН О5BqН О0otН О-CrsrН О* Н О(▓Н О' Н О%┬Н О$qН О"~r Н О ЫН Оt Н ОHТ╚Т╛ srП<Н ОцsrТЛП<ТМН О>ТП:Н ОП'Н ОФТлqrqr qrqr qrН ОaТН О5\Щ Н=7ZROUTE Program Logic Manual3h24: S04 (SN74S04/14/S) ; badfeThe is a string in one of two forms: either a lower-case letter followed by adecimal number, or a string preceded by "#". In the former case, the name is normalizedby suppressing leading 0's and then forcing the decimal number to be two digits long orlonger. Thus a004 and a4 would both be normalized to a04, and c04000 would benormalized to c4000. Interpretation of this normalized IC position string is strictly up tothe board routines, but some guidelines have developed among board designers:* It is pretty clear what ought to happen when the board socket and the IC arecongruent. It is less clear what ought to happen when a Sip is plugged into a Dipsocket, or an 8-pin Dip is plugged into a 16-pin socket, etc. Usually, something likea41 means that pin 1 of the IC is supposed to go into pin 1 of the board's socketa41, and the rest of the pins of the IC plug into other pins of the board in anobvious manner defined by the board routines.* For some boards, a41 means that the IC is to be inserted in some board-standardpart of a41. For example, D0 boards are covered with 20-pin sockets whose pin 10'sare trace-wired to GND. The D0 board routines interpret the number a41 on a 14-pin TTL IC as meaning that pin 1 of the IC goes in pin 4 of the socket, so that pin7 of the IC goes in pin 10 of the socket, the GND pin.* Most boards have adopted an offset convention. In this convention, #3a41 meansthat pin 1 of the IC is to be offset 0.3" in the direction of increasing socket pinnumbers from pin 1 of the socket. For the D0 board above, a41 and #3a41 wouldspecify the same position for a 14-pin TTL IC. If you wanted to put an 8-pin Sipin pins 12-19 of a 20-pin 300-mil-wide Dip socket, you would say #1_3a41,signifying a "sideways" shift of 300 mils and a "vertical" shift of 100 mils.* More positioning conventions will likely evolve. The idea is for any reasonablepositioning to be possible, and for common ones to be easily specified, preferablyto happen by default.The is a string from which ROUTE infers a number of characteristics of theIC, such asa) to what pins (if any) automatic terminator assignment applies,b) what fixed voltages are applied to what pins,c) how to compute the co-ordinates of pin i given the co-ordinates of pin 1.The has the following format:: , , ..., For example,Sin.15: j26.13o, E146stor08.sil+8: g22.2i, k25.12o, j23.11iWEo': g22.3iA is an alphanumeric string beginning with an alphabetic character andoptionally ending with the character "!". Two net names differing only in the final "!" areconsidered to be the same for matching purposes, and the "!" affects only automaticterminator assignment.НїОfПrsrТёНG⌠НґО_qТНЇО[ЙrТ░ПYТ▒НЇОZeТ╒П@ТёНЇОXЮТўПAТ╞НЇОW[ТqrТqrqrqrНЇОUжТї qrТ╗П0НЇОTQТПMНґОQ%ТбПGТцНґОO═Т╘П7Т╙НґОNТ┤ПFТ┬НґОL√qrТ╒П8ТёНґОKqrТ©ПLНґОI▄ТП-НґОF┌Т⌠qr Т■П0НґОDЩТ├qrТ┤ПFНґОCxТ▐П-Т░qrНґОAСТ┴П8Т┼НґО@nТП6НґО=dТ░Т▒П+qrНґО;ъТ╛П=ТґНґО:ZТ⌡Т°П!qrqrНґО8уТ≤П*Т≥П&НґО7PТЮТАП(qrНґО5кТЫТЗПAНґО2аТ╡ТЁП3НґО1<ТєП/Т╔П#НґО/ЇТНЇО+ТёТєsrП*НЇО)│Т НґО&UПAНґО$пП0НґО#KТчП%ТъtrП!НЇО ТП(НґОС qrqrqrqrНЇОгНґО⌡qНґОП&НґО▒НЇОerТКТЛПEНЇОЮТ ПWТ⌡НЇО [ТЛПSНЇОжТ тЇ▐=7\{JROUTE Program Logic Manual4In general, a may be one of the following:.A connector string is something like E or C. It may not end with a period or digit. An ICposition string is something like a41. It can contain periods but may not end with one.Interpretation of the connector strings and IC position strings rests with Board routines tobe described later. The final letter i or o or p indicates whether ANALYZE believes that thepin is an input pin, an output pin, or a power pin. These beliefs form the basis of some ofROUTE's warning messages.1.2 .wl format.An .wl-format file is an ASCII text file that looks like this:......@...The consists of a string followed by a carriage return. The stringuniquely encodes the board type. The 's are just the comment linescollected from the various .nl files. An now has the following form:: (//); ,...,where the 's are pins unused by any of the input .nl files. For example,i26: S04 (SN74S04/14/S); 8,13,14,15,16A looks like one of the following:CALIBRATE: <>; ... ... ...orDISCONNECT: <> ... ... ...Н!ОfПrsrТёНЩН О_ТП0Н О[ЙП#qrqrqrН ОZeqrqrqrqrНgОW[Т· Т÷qrqrП.НgОUжТгП!ТхqrП2НgОTQТєПPТ╔НgОRлТ²П%qrТ·qrqrsrНgОQGТ■П&Т∙П5НgОOбsrТН ОJОtrtН ОGцrsrН ОD≈Н ОC Н ОA█Н О@ Н О>┐Н О<ЧН О;yН О9ТqН О8orН О6ЙН О5eН О29ТЙПIТК Н О0ЄТП>ТН О//ТПNН О,ТТqrqr qrqrТУqrqrqrН О*~Н О'RТлП/ТмП%Н О$&qТП&Н О ЗrП9Н Онq rТёqrТєqrН ОIТП)Н ОдП)Н О?Н ОН ОГq rqrqrН ОbП)Н ОщП)Н ОXЪdЩ=ГYЫROUTE Program Logic Manual5or: <> () ... ... ...A is a string of the form:{,}where the two decimal numbers are interpreted as distances in the x and y axes, measuredin units of .025 inch, from the "origin" of the board (an arbitrary fixed position).For example,Sout.00: <8> (7) b01.05i {052,007} C176 {052, 000}CALIBRATE is a command that causes FAB to solicit operator assistance in attaching theboard to the x-y table, attaching a working tool, and locating four calibrating points on theboard, which must form the corners of a rectangle. After that FAB can find every point byitself until the board is removed from the table.DISCONNECT is a command to operate a milling tool to isolate a stitchweld pin from thetrace-wired net to which it was originally connected during board manufacture. Thisfacilitates installing TTL IC's in sockets intended for ECL IC's, for example. is an implicit command to wire up the named net in the same order as the pinsare mentioned.1.3 .ad format.An .ad-format file is almost a superset of a .wl-format file. There are two differences.First, an .ad-format file does not have the . Second, the .ad-format fileallows several additional wiring commands:UNPLUG: <> ... ... ...orDISCARD: <> ... ... ...orRECONNECT: <> ... ... НїОfПrsrТёНG⌠НЇО_НґО[ЙТІ qrqrqrТЇqrqrНґОZeТП)НґОXЮП)НґОW[НЇОT/П(НґОQqrqrqНЇОMвrТ·ПCТ÷НЇОLRТЖПTНЇОI&ТНґОEЗqНґОDuП(НЇОAIrТіsrТїП-НЇО?дТ├П>Т┤НЇО>?Т▐П'Т░srНЇО<╨ТП1НЇО9▌q rТ▄Т█П?НЇО8 ТПТЯПAНЇО6└ТПNНЇО3XТ─П0Т│П(НЇО1сТ НЇО-trtНЇО)тrТаПCТбНЇО(OТ╒ТёПQНЇО&йТП*НґО#·qrqrqrНґО"П)НґО ■П)НґОНЇОЦНґОЇqrqrqrНґО2П)НґОґП)НґО(НЇОЭНґО пq rqrqrНґОKП)НґО фП)ЪЗЇ =7]▀ЪROUTE Program Logic Manual6...orDELETE: <>; ... ... ...UNPLUG and DISCARD are commands designed to give the stitchwelding machineunrestricted access to stitchweld pins on which it will need to work. The difference is thatDISCARD means that the IC should not be replaced after the update, while UNPLUGmeans that the IC will be re-plugged afterwards. UNPLUG is actually a list of positionsthat will be re-plugged after the change, so it may contain board positions that originallywere empty. Sorry for the confusion.RECONNECT is a command to restore the connection from trace to pin that was earlierdestroyed by a DISCONNECT command. This would normally be done by soldering. TheBoard routines specify under what conditions the operator can be asked to do this.DELETE is a command to remove a net that was wired onto the board in an earlierrevision.1.4 Multiwire Net format1.5 Multiwire Hole format2. MetaProgram.First, let us imagine that ROUTE is being invoked to do its simplest task: collect togetherseveral .nl files and produce a .wl file, a .bp file, some -x.nl files, and a .re file. Processingproceeds as follows:1. The command line is processed to extract parameters. These include:a. the names of the .nl files,b. the names of the .wl, .bp, and .re files,c. the name of a .br-format file (or concatenation of .br-format files)containing compiled Bcpl Board routines,d. whether or not re-work is desired (/R), ande. parameters to control wire length minimization.2. Read in each .nl file. For each , accumulate a list of all 'scontained in that net.3. See whether any of the pin assignments in (2) above conflict with so-calledtrace-wired nets; that is, board-defined nets that are wired by PC-board traces. Ifso, and if this is permissible for the board type, disconnect the offending pins fromtheir trace-wired nets.4. All pins connected to trace-wired nets are partitioned into clusters according tothe closest pins that are still trace-wired. These clusters are then reassigned to newЪН!ОfПrsrТёНЩН О_Н О[ЙН ОXЎqrТqrqrН ОW9П)Н ОUЄП)Н ОT/Н ОQqrТqrП0ТН ОO~Т√П!Т≈П;Н ОMЫqrТоТпП"qН ОLtrТ╠Т╡qrН ОJОТ║П)Т╒П2Н ОIjТП$Н ОF>qrТ╙П>Т╚Н ОD╧Т╔q rТіП7Н ОC4ТШПFТЭН О@qrТьТыПDН О>┐Н О;ytТН О8oН О0oqН О-CrТ╘Т╙srП;Н О+ЎТ▌П/Т▐trП%Н О*9ТН О' ПFНО#АНО"\П,НО вТФП$ТГП#НОRТП(НОмП.НОHП2Н ОТкПOН О≈ТН ОkТтТуП5Н ОФТ╙П<Т╚Н ОaТ┘Т├ПFН ОэТН О╟Т║ Т╒ПIН О+Т÷ПRТ═PЩ Д=7]& ROUTE Program Logic Manual7nets with names like VCC1, VDD35, etc.5. All nets are routed if this has been requested. For each net this involves apermutation of the net order so as to minimize the total wire length. Additionaltermination pins may be added to nets in this step.6. The nets are then sorted into an order intended to optimize the wiring process.For stitchwelding this is currently believed to be:a) nets with very short arcs first, so other wires will not interfere with them,b) if two nets have shortest arcs of the same length, wire the shorter netfirst.7. All the output files are created from the data structures built up in steps 1-6.2.1 Automatic terminator assignment.The ECL logic family does not work properly unless each net contains at least oneterminating resistor. Assignment of terminating resistors to nets by hand is a tiresome task,and it is reasonable that the DA system should do it. Particularly for long wires, the drivershould be on one end of a wire and a terminating resistor be on the other, or else the drivershould be in the middle and terminators on both ends. ROUTE is the only program withenough information about board position and wire routing to be able to do rationalterminator assignment.First, let us expand on step 5 above to explain how termination comes about:5a. A permutation of the net is chosen to minimize the wire length, subject to thefollowing constraints:i) the first edge (or cable) pin is constrained to lie at the end of thepermutation, orii) if there is any ECL output pin in the net, and if exactly one pin in thenet is marked as an output pin, and if the net contains no edge or cablepins, then if the resulting net would be no longer than 1.2 times the lengthof the constrained net, the output pin is constrained to lie at the end of thepermutation.5b. If no instance of the net name ended in the character "!" (signifying thattermination is to be ignored) and there is an ECL output pin in the net, and thereare no terminating resistors explicitly included in the net, then either one or twoterminating resistors will be assigned to the net. Two resistors will be assigned if thenet is longer than 4 inches, or if the net contains more than one output pin, or ifany output pin is not at the end of the net. One resistor will be assigned otherwise.5c. If any terminating resistors are to be assigned, they are assigned either at theends of the nets or between the next-to-end and end pins in the net so as tominimize the increase in wire length (except if an unterminated stub longer than 3inches would result). Terminators are chosen as close as possible to the end pins. Ifonly one terminator is assigned, it is assigned on the opposite end of the net fromthe output or edge pin.НїОfПrsrТёНG⌠НґО_ТqrqrНґО[ЙТщП"ТчП-НґОZeТЇП.Т╦П"НґОXЮТП3НґОUЄТіП#ТїП/НґОT/ТП3НёОQТ┘П,Т├П$НёОMвТ╪ ТҐП<НёОLRНґОI&Т╣ТІПMНЇОDStТП$НЇОA'rТРП2ТСНЇО?╒Т┴П<Т┼П!НЇО>Т█ПRТ▌ НЇО<≤Т─П"Т│П;НЇО;Т╠П7srТ╡НЇО9▌ТХПFТИНЇО8 ТНЇО4щПLНґО1╠Т·Т÷ПAНґО0,ТНёО-ТДТЕПBНёО+{ТНёО(OТ П5Т⌡НёО&йТ╨ПBТ╩НёО%EТ ПEТ⌡НёО#юТ▐П8Т░НёО";НґОТчТъП<НґО┼Т≤ПLТ≥НґОТ╟П7Т╠НґО─Т┌ПTТ┐НґОШТ·П8Т÷НґОvТ▓ПUНґОJТЄТ╣П>НґОеТжТвП<НґО@Т■ПKТ∙НґО╩Т▓Т⌠П@НґО6Т П#Т⌡П0НґО╠Т ╪Їj=7[═,ROUTE Program Logic Manual82.2 Correction.Another practical consideration is correction (revision). It should be possible to correct aset of drawings and have the size of the resulting wiring change relate to the size of thechange in the drawings. This is done by reading the previous .wl file and only changing thewiring of a net if it differs between the old .wl file and the new one. Unfortunately, one ofthe least significant physical features of a net is its name, so ROUTE must be able torecognize identical nets as identical even if their names change. If re-work is requested, anew step 4.5 is inserted after the nets are completely specified but before they are routed:4.5 For each net in the old .wl file, determine what new net it is the same as, exceptfor terminating resistors. If it is not the same as any new net, then mark it fordeletion in the .ad file. If it is the same as some new net, and if the termination forthe old net makes sense for the new net, and if the new net has no explicittermination of its own, then route and terminate the new net exactly as the old onewas, and mark it as routed and terminated so that it will not be worked on in step 5nor output to the .ad file.3. Internal Data Structures.3.1 Names and Namees.The basic organizing concept in ROUTE is the "name". Nets have names, IC types havenames, board positions have names, etc. ROUTE maintains a single name data structure, andattached to each name is a list of named objects with that name. The name data structure isa hash table where each bucket is a pointer to a list of name blocks that all hash to thatbucket. A name block looks like this:structure name:[ next word// next name block in bucket list, or nilmark word// =-1. Namee list is circular and ends here.nameString @string]The name block is immediately followed by a namee block, several types of which aredescribed below.3.1.1 Nets.One namee is a net. A net block looks like this:sturcture net:[ next word // to next namee with this nameflags bit 4unused bit 8type bit 4// =netpinList word// pointer to first pin of pin listshortestarc word = netnum word = minSperge wordnetlength word]Н!ОfПrsrТёНЩН О_tТН О[ЙrТ╘П-Т╙П/Н ОZeТ╛ТґПTН ОXЮТ┬Т┴П?Н ОW[Т└П:Т┘П#Н ОUжТтПBsrН ОTQТ═П*Т║П2Н ОRлТ÷ПPТ═Н ОO═Т┤Т┬П?Н ОNТЎП7Т©Н ОL√Т┘П@Т├Н ОKТХП?ТИН ОI▄Т█ПSН ОHТ┐Т└ПAН ОF┌ТН О@qН О;4tН О8rТфТгsrП.Н О6┐Т▀Т▄ srП,Н О4ЧТ├Т┤ПAН О3yТ╗Т╘П3qrН О1ТТ qrН О.х qrНьО-CТ─ НдТП'НьО+ЎТ─НIТП+НьО*9НьО(ЄН О#АТкqrП0ТлН О"\ТН ОRt Н О&rqrН ОЗ qrНьОuП+НьОП НьОkНьОФТ─ НIТНьОaТ─НдТП!НьОэП/НьОW НьОр`Щ▀=7[ROUTE Program Logic Manual93.1.2 IC instances.Another namee is an IC instance. The name denotes the board position. An icinst blocklooks like this:sturcture icinst:[ next word // to next namee with this nametype word// =icinstictype word// pointer to ictype block for this ICpinattribute wordpin^1,npins// each one links to the next pin in// the pin list of its net, or nil]Note that one can chain one's way into an icinst block at some undetermined index in itspin vector, and then get properly aligned with the icinst block by scanning backward untildetecting type=icinst, which is an illegal value for pin, pinattribute, and ictype words.3.1.3 IC types.Another namee is the IC type. An ictype block looks like this:sturcture ictype:[ next word // to next namee with this namenpins bit 12 // same as npins in icinsttype bit 4// =ictypeicclass word// pointer to IC class containing this typeoutpins^1,npins bit 1// one bit per pin, true if pin// ever used in any IC instance as output]3.1.4 IC classes.The final namee is the IC class. An icclass block looks like this:structure icclass:[ next word // to next namee with this nameisTraceWired bit 1// needs termination?isConnector bit 1 // is this a terminator IC?printUsedList bit 1unused bit 9type bit 4// =icclassPinOffset word// PinOffset(npins, pinNo, lv XOffset, lv YOffset) is// a routine that computes the X- and Y- offsets// of the given pin from pin 1, in 25-mil units.// For a standard 14-pin DIP, pin 1 would result in//{0,0}, pin 2 would result in {4,0}, and pin 14 would// result in {12,0}.PinAttributes word// PinAttributes(icinst, pinNo) = attributes, such as// isEcl or isTerminatorImplicitICNets wordНїОfПrsrТёНG⌠НЇО_tТНЇО[ЙrТ╣ТІП)qrНЇОZeТНґОW9 qrНxОUЄП+НxОT/Т─НИТНxОR╙Т─ НdТqrНxОQ%НxОO═ НdП$НСОNП"НxОL√НЇОIjТ°П*qrТ²П"НЇОGЕТ≈П)Т≤ qrП!НЇОF`ТчПYНЇОA█tТНЇО>arП!qrНґО;5 qrНxО9╟П+НxО8+П!qНxО6іrТ─ НИТНxО5!Т─НdТП)НxО3°Т─Н!ZТНСО2П)НxО0▓НЇО+©tНЇО(⌠rП$qrНґО%g qrНxО#БП+НxО"]Т─Н!ZТНxО ьП-НxОSНxОнНxОIТ─ НИТНxОдТ─ НСО?ТП5НСО╨П0НСО5П0НСО╟П3НСО+НnП4НСОіНxО!НСО°П5НСО НxО▓Ъ└ЇK=7\©ROUTE Program Logic Manual10// ImplicitICNets(npins, icInstNameString) is// a routine that writes// nets for such things as IC power and ground onto// a file called "implicit.nl"npins word// # pins, overridden by ictype block... and other fairly esoteric stuff for terminators and trace-wired nets]3.2 Boards.A board is a set of Bcpl subroutines dynamically loaded into ROUTE. It is represented asone or more concatenated .BR files. These subroutines are:FindIndexFromCoord(xPos, yPos, picclass, pPinNo) = indexThis routine finds an integer from 1 to maxPins that uniquely represents theboard pin at co-ordinates xPos, yPos. It returns 0 if there is no board pin atco-ordinate xPos, yPos. If xPos = yPos = -1, then it returns maxPins+1. Inaddition, if the board pin is initially connected to some trace-wired net,@picclass is set to the icclass describing that trace-wired net and @pPinNois set to the number of the pin within the trace-wired net.DeclareInitialNets(TWBuild, TermBuild, ConnBuild)This routine declares all the trace-wired nets, terminator sets, andconnectors that the board has.ZeroTablePoint(point) = stringIf point=0 then the string name of the board is returned. If point is from 1to 4 the string name of the proper calibration point is returned. Thecalibration points should form a rectangle on the board.LevelTransform(level, x, y, px, py, pName, pPull, pWire) = existsA given pin is described by different co-ordinates according to whether aboard is positioned wiring-side up or component-side up. For each value oflevel, this subroutine implements a transformation from internal co-ordinates x,y to printing co-ordinates @px,@py. @pName is set to a stringgiving the name of this level. @pPull is set according to whethercomponents can be removed at this level. @pWire is set according towhether wiring can be done at this level.FindCoordFromString(s, px, py, vop1, hop1) = {absolute, relative, illegal}This routine takes the string name of a board location and computes theinternal co-ordinates x,y of that position. It then adds vop1 and hop1 as theoffsets vertically (the long way) and horizontally (the short way) of somedesired pin assuming that pin 1 is installed at x,y. The result is placed in@px,@py. The result is absolute if the pin is legal, and illegal otherwise.BoardPinCoord(s, icinst, pinNo, px, py) = {true, false}Н!ОfПrsrТёНЩНSО_ТП-НSО]▒НSО\П3НSОZ┤НьОY НSОW}П%НьОUЬПIНьОTsН ОO═t Н ОLtrТ╙П>srТ╚Н ОJОТП:Н ОGцП8НОD≈Т│П/Т┌НОCТ┬П2Т┴НОA█Т╔ПGТіНО@ТфТгП4НО>┐Т≈Т≤П;НО<ЧТП;Н О9рП1НО6іТQТRП+НО5!ТН О1УНО.иТ▒ПBТ▓ НО-DТВТЬПAНО+©ТП8Н О(⌠ПAНО%gТ╟П%Т╠П$НО#БТ▀Т▄П7НО"]Т&П7Т'НО ьТ⌡Т°П<НОSТ:Т;П2НОнТЗТШП*НОIТП)Н ОПJНОЯТ©ПCТюНОlТ┴ПFТ┼НОГТ╣П%ТІП%НОbТ╡ТЁП/НОщТ©П-ТюН О╠ТП7Ъ 2Щj=7[═ROUTE Program Logic Manual11This routine is normally defined by ROUTE itself (using the board'sFindCoordFromString), but the board module can override ROUTE'sdefinition. This routine takes the string name of a board location, a pointerto an IC instance, and a pin number, and computes the internal co-ordinatesx,y of that pin. The result is true if the pin position is legal, and falseotherwise. This routine would be defined instead of FindCoordFromStringif you want to do screwball ball things like put TTL IC's upside-down inEcl-wired sockets.НїОfПrsrТёНFмНёО_ТП%sr ТНёО]▒ТTП.ТU srНёО\Т▌П.Т▐НёОZ┤Т┐Т└П3НёОYТнП.ТоНёОW}ТґТўП8НёОUЬТ╟П'Т╠П!НёОTsТЪ"ёT,3KчT TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMAN MATH TIMESROMAN lБІНВ&т.Е5П;ЫB╛Ej/HFЪЪ∙┌b ЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪroutemanual.press Swinehart26-Jun-80 12:52:41 PDTF