XEROXPALO ALTO RESEARCH CENTERComputer Science LaboratoryJuly 17, 1979To:Route UsersFrom:Roger BatesSubject: Timing analysis of netsStored: MAXCNetDelays.pressThe program called "NetDelays.run", found on MAXC, is intended for helping the logicdesigner by providing some measure of the wire delay performance.The program is invoked by: NetDelays/VDM Foo.wlThe file must be a wire-list file produced by the Route program. The results will be written onto afile called Foo.nd ("nd" for Net Delays).Output information is displayed on the screen as the wire list is processed. The programcan be stopped by typing any character. You may then continue by typing any character,or skip the remaining nets by typing DEL.The optional switch V requests Verbose output, which will cause additional information tobe displayed that may be of value in determining the nets performance. Program outputwill be described in gory detail below.The optional switch D disables output to the display and sends results only to the disk file.The optional switch M causes wire lengths to be computed as Manhatten ( deltaX +deltaY ), as opposed to the default straight line distance.The output of this program contains Bravo format information specifying page headers, Tabstops, and Font 1. Bravo hardcopy will produce 2 columns per page of output (unless theVerbose switch was used). The output file is only reasonably formatted when read into Bravo andexamined or printed by Bravo. It assumes that a small font (I have Helvetica8) is installed as font1 in your User.cm for Bravo, and columns won't look good with larger fonts.This program was written as a result of the Dorado project which uses ECL logic, and thereforethe program is biased towards ECL. It ignores "Muffler" chips (a scheme of internal statesampling) as inputs, while including their pins for capacitive loading. It also recognizes "SelectedECL" chips as indicating nets involving clock distribution.The next page contains an example of NetDelays output when run in the Verbose mode. Theoutput that is only printed by Verbose mode is indicated by the use of italics.Additional summary information of net lengths and delays is printed on the last page ofoutput. This information is self-explanatory and not shown here. Н&зО`vpН iО^BqТXН"+О\TrН'⌡ОZfsНЇОS^tsН( НЇОP°tsН( НЇОMзtsН(НЇОKtsНґН(НЇОFEТЮТАПGНЇОDюТПAНЇОAІП1НЇО>╛Т┐П-Т└П7НЇО='ТП)НґО9ШТ░П>Т▒НґО8vТ├Т┤ПFНґО6ЯТП)НґО3еТ▐Т░ПDНґО2@Т▒ПWНґО0╩ТП'НґО-▐Т│ПRТ┌ НґО*cТ╩П)Т╪П(НґО(чТП;НЇО%╡ТшП<ТэНЇО$-ТрП'ТсП1НЇО"╗Т─Т│ПFНЇО!#Т┬П0Т┴П4НЇО·ТПKНЇОrТ ПIТ⌡НЇОМТзПZНЇОhТ┌П*Т┐П;НЇОЦТП;НЇОЇТ╞П$Т╟П4НЇО2ТПOНґОТ╘П1Т╙П&НґО│ТПBНЇЩAV;П2Muffler at a6Clock at a8Clock at a9Muffler at b6Found 4 Terminators CALIBRATE - skippedtiiiiiiio15.1,8=4.3r alu.00(614) Dly=4.3; L=7; T=1itiiiiiiiiiio15.4,13=5.3r5d BSel.2a(23) Dly=5.3; L=11; T=1tiiimiooit2.5,2=0.8w; 6.5,3=1.7f; 12.1,7=3.5r alub.00(233) Dly=4.3; L=6; T=2; WO=1.6otmioiit5.6,5=1.9w; 9,7=3f; 1.7,2=0.7r3w alua.00(223) Dly=4.9; L=4; T=2; WO=3.8omt FF.0mem - skippedtmiiiiio10.5,6=3r LastNext.0'(229) Dly=3.0; L=6; T=1 GND132 - skippedThe explanation of the output is as follows:First a table is made indicating what locations contain "Mufflers" (ie MU10164) and "Selected Ecl" IC's. Then thenets are examined one at a time and reported as follows:Each line starts with a string of characters that summarize the types of nodes on the net. The possible characters of"i o t m e" for input, output, terminator, muffler, and edge-pin respectively.Edge pins will be treated as an "input" unless the net contains no output, then the edge pin will be assumedto be the "output".After the net has been read in, three possible delay values are computed, and reported. The first is the delay betweenoutputs(labeled "w"), the second is the delay from the first output to the last input(labeled "f"), and third is the delayfrom the first input to the last output(labeled "r").The format of the report of this calculation is "d.d,p=t.t", where d.d is the distance between nodes (ininches), p is the number of pins between the nodes plus the end nodes, and t.t is the time for propagation(in nanoseconds).Next the name of the net, and its "net number" as assigned by route, are printed. Notice that some net names arepreceded by a 2(3) character "flag". The program examines the delay values for the nets, and "flags" those it thinksmight be worth examining. The flag is made up of the delay in nanoseconds and a character indicating what checkprompted the flag.The possible flags are"5d "delay on a simple net"3w "delay between wire-or'd ouputs"3dc"delay on a net with a clock output"1wc"delay between outputs with a clock outputThe numbers in these examples indicate the minimum delay that will prompt the flag."Dly=" the propagation time from the first input of the net, to the last output and back to the first output. This valueis computed for both directions down the net, and the maximum is reported."L=" the total number of loads on the net, inputs including mufflers, but not terminators."T=" the number of terminators."WO=" the round-trip propagation delay between the outputs.Now some comments about each of the nets in the above example:CALIBRATE is skipped for obvious reasons.alu.00 is an example of a simple net with only one output.BSel.2a is a simple net, but has been flagged due to excessive net delayalub.00 in an example of a multiple output net with good wire-or characteristics.alua.00 is an example of a multiple output net flagged due to poor wire-or characteristics.FF.0mem is skipped because its only input is a muffler, and that isn't interesting.LastNext.0' is an example of a net where the muffler input is on the end of the net.In this circumstance, the net delay calculated is from the first non-mufffler input on the left to the output onthe right.GND132 is skipped since it is a power net, as is VBB and VEE.НN ОfПsНЇОbAuТНЇОa НЇО_г НЇО^┼НЇО]MН$О\tuНЇОZсН$ Н*btТ─Н;yТНЇОY√uН$Н*btТ─Н;yТ НЇОXYu Н$Т─П#Н*btН;yТ≤НЇОWuН$Т─Н*btН;yТ≤НЇОUъuН*btТ─НЇОT╒uН$Н*btН;yТН*bОSeТ─uНЇОMysТП,НЇОJшtТ╔ПOТіП#НЇОI·ТП8НЇОG$Т┼ПUТ▀П!НЇОEГТПNНґОD╙Т┐ПBТ└П*НґОCmТНЇО@┬Т│П\Т┌НЇО?KТ▄ПJТ█П0НЇО>ТП5НґО<яТ╟Т╠ПQНґО;■Т■Т∙П]НґО:WТНЇО7rТ■Т∙П]НЇО65Т┴Т┼ПhНЇО4ЬТ■П5Т∙П;НЇО3╩ТНґО2~НЮО1AТ─Н`ТНЮО0Т─Н`ТНЮО.гН`П"НЮО-┼Н`П)НґО,MПSНЇО)сТ├П[Т┤НЇО(√ТПJНЇО%╠П[НЇО"лНЇОГП;НЇОIsП>НЇО@tП)НЇОП:НЇОфПHНЇО┴ПQНЇОLП[НЇОПSНЇОрПTНґО∙Т▐ПSТ░НґОXТ НЇОП=ЪЎЇ ╩AZO^3Multiple BoardsIn order to allow net delays to be calculated on backpannel nets between boards, an additionalslew of commands have been added to enable running NetDelays on multible wire list files.NetDelays/W Foo.wlThe global switch "W" can be invoked on a single wire list file to cause NetDElays to select justthe nets that touch edge pins (either E or C pins) and place them on a new file with the "wl"extension replaced with "Ewl". Using this on each board in a system will cause a series of".Ewl" files to be created, which will later be used as the input wire list files to NetDelays for finalbackpannel processing. The advantages of this processs are 1) The Ewl files are relatively smallso you should not run out of disk space 2) if minor edits are necessary (for signal name changes)are needed, Bravo can be used and finally 3) the NetDelays program will run faster.NetDelays/EC FooTerms/T Foo1.ewl Foo2.ewl Blank Blank Foo3.EwlThe global switch E or C are indications that NetDelays should process the edgepin nets for Epins or C pins respectively. I this case, the program expects a series of wirelist files, eithercomplete ".wl" files, or the preselected ".Ewl" files, or a mixture of both.The length of interconnections between boards is determined from the board dimensions foundwithin the wirelist file togeather with the count of wirelist files between entries. Currently theprogram uses 0.7 inches between boards. As a means of declairing an unused socket within aseries of .wl files, the reserved name Blank may be used in place of a board name. In the aboveexample, there is .7 inches between Foo1 and F002, and ther is assumed to be 2.1 inchesbetween boards Foo2 and Foo3.For the problem of terminations, it is possible that terminating resistors might be implemented aspart of the backpannel. If NetDelays is to be able to calculate the reasonableness of terminators,it must be told in some way about them. In the above example, the "FooTerms" is a text filewhich indicates 4 terminators associated with the socket for Foo1, 1 terminator for Foo2 and 5terminators associated with the socket for Foo3. The contents of file FooTerms looks like:Board 0E0E18C1C17Board 1E001Board 4E95E96C23C24C27НN ОfПsНЇОbAvТНЇО_9sТ═Т║ПMНЇО]ЄТуТжПRНґОZ┬ТXНЇОW\Т▓Т⌠ПLНЇОUвТ╙П'Т╚П6НЇОTRТцП[НЇОRмТ┘ПFТ├П"НЇОQHТ▐Т░ПKНЇОOцТ┐П'Т└П:НЇОN>ТПSНґОKТXП>НЇОGФТ╘ПFТ╙НЇОFaТдТеПZНЇОDэТПLНЇОA╟Т╗ Т╘ПQНЇО@+ТЎПUТ© НЇО>іТ║ПYТ╒НЇО=!Т▀Т▄ПLНЇО;°ТжПPТвНЇО:ТНЇО6КТ⌠Т■П[НЇО5fТ┴Т┼ПHНЇО3АТ╞ПRТ╟ НЇО2\Т╗Т╘ПMНЇО0вТчП0ТъП+НґО-╚rТНґО,&НґО*║НґО)НґО'≈НґО$█НґО#НґОЧНґОyНґОТНґОoНґОЙНґОe╟ЇАAQ)Ж4Running NetDelays on the above example might produce the following output on file F001.End0=;File=Foo1.sil Rev=Ba Date=11/2/78 Page=01 -MARKED BUILT-1=;File=Foo2.sil Rev=Ba Date=11/2/78 Page=01 -MARKED BUILT-2=;Blank3=;Blank4=;File=Foo2.sil Rev=Ba Date=11/2/78 Page=01 -MARKED BUILT-tiiiiioooie0,toe1,> 21.9,10=5.8r5d FG.0(22.7)Dly=5.8; S=4; L=6; T=2iiiiioooiet1,etot4,> 12.1,10=4.1r3T FG.1(21.1)Dly=4.1; S=4; L=6; T=3; Stub=4.6tiie0,tie4,> 22.1,3=4r0S Signal2(22.1)Dly=4.0; S=0; L=3; T=2tiie0,> 22.1,3=4r1B Signal1(22.1)Dly=4.0; S=0; L=2; T=1Unused backpannel terminator on Board 4 Pin E96.Total Nets = 5Average Net Length = 22.000 (based on Euclidean wire routing)Average Net Delay = 4.320Total Nets with delays between 3 and 4 ns = 1Total Nets with delays between 4 and 5 ns = 3Total Nets with delays between 5 and 6 ns = 1In Verbose mode, the net is characterised by the node strings ("tiioe") followed by the board number that the net is from, and separatedby commas.The reasons and minimum values for "flagging" a net are different in the EdgePin mode.The possible flags are"1B "The net only goes to one board"3T "The net contains to many terminators"0L "The net contains no inputs (Loads)"0S "The net contains no outputs (Sorces)"1sc"The clock net contains a "stub" which could cause a pulse of width >1"3s "The net contains a "stub" which could cause a pulse of width >3"3dc"The clock net has a delay >3"5d "The clock net has a delay >5ЪНN ОfПsНЇОbТ╟ПBТ╠НЇО_uТFП<НЇО]ьП<НЇО\⌡НЇО[^НЇОZ!П<НЇОWїН)Н:НЇОVjП!Н)Н:НЇОU-Н)Н:НЇОSПН)Н:НЇОQvП0НЇОM© НЇОL┌П>НЇОKEНЇОHкП-НЇОG▌П-НЇОFQП-НЇОB/tП┬НЇО@Р НЇО> ПVНґО<пТНЮО;⌠Т─Н`ТНЮО:VТ─Н`ТП!НЮО9Т─Н`ТНЮО7эТ─Н`ТП!НЮО6÷Н`ПEНЮО5bТ─Н`ТП<НЮО4%Н`НЮО2ХТ─Н`Т╙Ї/D∙8Э╨LOGO HELVETICA HELVETICA HELVETICA HELVETICA HELVETICA HELVETICA ╒ FЪЪj/⌠╩{qЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪnetdelays.bravoBatesJuly 17, 1979 11:39 AM