VarRegImpl.mesa
Copyright Ó 1987 by Xerox Corporation. All rights reserved.
Created by Jean Gastinel, October 17, 1987 12:28:01 pm PDT
This module simulate a register which contain a constant loadable by a prog
DIRECTORY
Core, CoreClasses, CoreCreate, CoreProperties, Ports, Rope, Rosemary, RosemaryUser;
VarRegImpl: CEDAR PROGRAM
IMPORTS CoreClasses, CoreCreate, CoreProperties, Ports, Rosemary
~ BEGIN
CellType : TYPE = Core.CellType;
Wire: TYPE = Core.Wire;
value: CARD ← 0;
VarRegState: TYPE = REF VarRegStateRec;
VarRegStateRec: TYPE = RECORD[
reg: Ports.LevelSequence, -- hold the value
Q: CARD,  -- the output
Clock: CARD,
b: CARD
];
Here are the 3 procs
VarRegDef: PUBLIC PROC [b: CARD] RETURNS [ct: CellType] ~ {
Here is where the name and the size of public wires must be given
public: Wire ← CoreCreate.WireList[
LIST[
CoreCreate.Seq["Q",8],
"Clock"
]];
This creates a celltype
ct ← CoreClasses.CreateUnspecified[public: public];
CoreProperties.PutCellTypeProp[ct,$b,NEW[CARD ← b]];
[] ← Rosemary.BindCellType[cellType: ct, roseClassName: VarReg];
Now the type of each pins
Ports.InitPorts[ct, ls, drive,"Q"];
Ports.InitPorts[ct, l, none,"Clock"];
};
VarRegInit: Rosemary.InitProc = {
Init the state 
--PROC [cellType: Core.CellType, p: Ports.Port, oldStateAny: REF ANY ← NIL] RETURNS [stateAny: REF ANY ← NIL]--
vareg: VarRegState ← IF oldStateAny=NIL THEN NEW[VarRegStateRec] ELSE NARROW[oldStateAny, VarRegState]; 
vareg.reg ← NEW[Ports.LevelSequenceRec[8]];
Ports.SetLS[vareg.reg, X];
[vareg.Q] ← Ports.PortIndexes[cellType.public,"Q"];
[vareg.Clock] ← Ports.PortIndexes[cellType.public,"Clock"];
vareg.b ← NARROW[CoreProperties.GetCellTypeProp[cellType, $b], REF CARD]^;
stateAny ← vareg;
};
VarRegEval: Rosemary.EvalProc = {
--PROC [p: Ports.Port, stateAny: REF ANY, clockEval: BOOL]--
vareg: VarRegState ← NARROW[stateAny];
Ports.LCToLS[(value / vareg.b),vareg.reg];
Assign the values of the output wires.
Ports.CopyLS[from: vareg.reg, to: p[vareg.Q].ls];
};
VarReg: Core.ROPE = Rosemary.Register[roseClassName: "VarRegDef", init: VarRegInit, evalSimple: VarRegEval, scheduleIfClockEval: TRUE];
END.