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0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 1 90E5 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0077 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 3 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 1 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 1 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 1 0 0 0 0 xx | x 1 98E5 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 1 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 1 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 1 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 1 90E9 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0088 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 3 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 1 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 1 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 1 0 0 0 0 xx | x 1 98E9 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 1 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 1 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 1 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 C 0 01 | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 C 0 01 | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 C 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x 11 x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 C 0 03 | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 C 0 03 | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 C 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x 22 x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 C 0 09 | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 C 0 09 | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 C 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x 33 x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 C 0 0B | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 C 0 0B | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 C 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x 44 x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 C 0 0D | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 C 0 0D | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 C 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x 55 x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 C 0 0F | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 C 0 0F | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 C 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x 66 x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 C 0 25 | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 C 0 25 | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 C 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x 77 x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 C 0 29 | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 C 0 29 | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 C 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x FF x . �SmallCacheInner-IOWrites.oracle Pradeep Sindhu May 6, 1988 11:37:09 pm PDT TEST COMPLETE NB: Each line corresponds to one cycle of the DynaBus clock The state of the cache following Reset is: all x's except for signals set otherwise by the hardware _ Logic.SetOracleFileName["SmallCacheInnerTest", "SmallCacheInner-IOWrites"] _ SmallCacheLogic.ArrayPutState[SmallCacheLogic.cacheStateValueK] Perform the reset sequence: Assert Reset till x's get flushed out (the last signal appears to be RamForP, which settles 3 cycles after BCtlRamForBCWS6, which settles in cycle 6): Pradeep Sindhu May 6, 1988 6:28:09 pm PDT D D D n n D D B B G G I P P P P | D H B B B R S P P P P P S A E D D S S C D L r S m C B D | B d D O S e S R F F D R h d x F R e e y a e a S o m y a | u r a w h q t e a a a e i d e r e r l c t n n t d d t t | s C t n a u o j u u t s f r c e s i e l a g t o e I e a | O y a e r e p e l l a c t e u e e a c e I t p I n S | u c O r e s O c t t h C s t z t l t 0 n h I n e | t l u O d t u t C e k s e e I n l | e t u O t o d n I | O t u d u n | u t e l | t e | Check that chip Id can be read out (scan path 0): D D D n n D D B B G G I P P P P | D H B B B R S P P P P P S A E D D S S C D L r S m C B D | B d D O S e S R F F D R h d x F R e e y a e a S o m y a | u r a w h q t e a a a e i d e r e r l c t n n t d d t t | s C t n a u o j u u t s f r c e s i e l a g t o e I e a | O y a e r e p e l l a c t e u e e a c e I t p I n S | u c O r e s O c t t h C s t z t l t 0 n h I n e | t l u O d t u t C e k s e e I n l | e t u O t o d n I | O t u d u n | u t e l | t e | Shift In MyId (scan path 1) (Recall that MyId is only one bit so only one bit needs to be shifted in): D D D n n D D B B G G I P P P P | D H B B B R S P P P P P S A E D D S S C D L r S m C B D | B d D O S e S R F F D R h d x F R e e y a e a S o m y a | u r a w h q t e a a a e i d e r e r l c t n n t d d t t | s C t n a u o j u u t s f r c e s i e l a g t o e I e a | O y a e r e p e l l a c t e u e e a c e I t p I n S | u c O r e s O c t t h C s t z t l t 0 n h I n e | t l u O d t u t C e k s e e I n l | e t u O t o d n I | O t u d u n | u t e l | t e | SmallCacheInner-IOWrites: NB: Our chip's type is 1 and Id is 1, so IO Address from bus side must be 11xx xxxx IOWriteRequest-Foreign-Miss (devType=1, devId=1, address not in cache) IOWriteRequest-Foreign-Miss (devType=1, devId=0, address in cache) IOWriteRequest-Foreign-Miss (devType=0, devId=1, address in cache) IOWriteRequest-Foreign-Miss (devType=0, devId=0, address in cache) IOWriteRequest-Foreign-Hit (CWSOld) Should update contents of CWSOld IOWriteRequest-Foreign-Hit (CWSNew) Should update contents of CWSNew IOWriteRequest-Foreign-Hit (AID) Should update contents of AID IOWriteRequest-Foreign-Hit (FaultCode) Should update contents of FaultCode IOWriteRequest-Foreign-Hit (InterruptStatus) Should update contents of InterruptStatus IOWriteRequest-Foreign-Hit (InterruptMask) Should update contents of InterruptMask IOWriteRequest-Foreign-Hit (Modes) Should update contents of Modes IOWriteRequest-Foreign-Hit (LocalFaultCode) Should update contents of LocalFaultCode Check that the IO locations have the right values Read it back [01]: Read it back [03]: Read it back [09]: Read it back [0B]: Read it back [0D]: Read it back [0F]: Read it back [25]: Read it back [29]: The state of the cache at this point should be: SmallCacheArrayStateValues.cacheStateValueL ��C��Icode�*�J�J� J�J�J�;J��c�cJ��L�LJ��A�AJ��J�J��f�J��K�)J�J��%�ef��AJ��%��AJ��%��AJ��%��AJ��%��AJ��#��?J��"��=J��5J��1J��'J��"J��fz�efz� �!J�J��J�JJ��E�EJ��J�JJ��E�EJ�J��J�JJ��E�EJ��J�JJ��E�EJ�J��J�JJ��E�EJ��J�JJ��E�EJ�J��J�JJ��E�EJ��J�JJ��E�EJ�J��J�JJ��E�EJ��J�JJ��F�FJ�J��J�JJ��F�FJ��J�JJ��F�FJ�J��J�JJ��F�FJ��J�JJ��F�F�J��1�1J��%��AJ��%��AJ��%��AJ��%��AJ��%��AJ��#��?J��"��=J��5J��1J��'J��"J�� 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