TimeOutCounter.oracle
Pradeep Sindhu February 23, 1988 1:48:27 pm PST
Test completed June 24
Signal Order is:
NonFBTIP | TimeOut
The counter has 3 bits, which means a time out will occur in 2**(3-1), or 4 cycles. The two stages of delay at the end of the counter mean that the signal will be seen in 6 cycles.
First ensure that TimeOut stays low as long as NonFBTIP is low for less than 4 cycles at a time
0 | X
0 | X
0 | 0
0 | 0
1 | 0
0 | 0
1 | 0
1 | 0
0 | 0
1 | 0
1 | 0
1 | 0
0 | 0
0 | 0
0 | 0
0 | 0
0 | 0
0 | 0
0 | 0
0 | 0
Then ensure that TimeOut does go high if NonFBTIP stays high for 4 or more cycles
1 | 0
1 | 0
1 | 0
1 | 0
1 | 0
1 | 0
1 | 0
1 | 1
1 | 0
1 | 0
1 | 0
1 | 0
1 | 0
1 | 0
1 | 0
1 | 1
1 | 0
1 | 0
.