SmallCacheInner-ClrAllVPV.oracle
Pradeep Sindhu May 6, 1988 11:25:53 pm PDT
TEST COMPLETE
NB: Each line corresponds to one cycle of the DynaBus clock
The state of the cache following Reset is: SmallCacheArrayStateValues.cacheStateValueE
← SmallCacheLogic.ArrayPutState[SmallCacheLogic.cacheStateValueE]
Perform the reset sequence:
Assert Reset till x's get flushed out (the last signal appears to be RamForP, which settles 3 cycles after BCtlRamForBCWS6, which settles in cycle 6):
Pradeep Sindhu May 6, 1988 6:28:09 pm PDT
D D D n n D D B B G G I P P P P | D H B B B R S P P P P P
S A E D D S S C D L r S m C B D | B d D O S e S R F F D R
h d x F R e e y a e a S o m y a | u r a w h q t e a a a e
i d e r e r l c t n n t d d t t | s C t n a u o j u u t s
f r c e s i e l a g t o e I e a | O y a e r e p e l l a c
t e u e e a c e I t p I n S | u c O r e s O c t t h
C s t z t l t 0 n h I n e | t l u O d t u t C e
k s e e I n l | e t u O t o d
n I | O t u d u
n | u t e l
| t e
|
( 0 0 0 1 0 0 ) 0 0 0000 0 0 0 0 0 0 00 | x x xxxx x x x x x x x xx x --A
( 0 0 0 1 0 0 ) 0 0 0000 0 0 0 0 0 0 00 | x x xxxx x x x x x x x xx x
( 0 0 0 1 0 0 ) 0 0 0000 0 0 0 0 0 0 00 | x x xxxx x x x x x x x xx x --B
( 0 0 0 1 0 0 ) 0 0 0000 0 0 0 0 0 0 00 | x x xxxx x x x x x x x xx x
( 0 0 0 1 0 0 ) 0 0 0000 0 0 0 0 0 0 00 | x x xxxx x x x x x 0 x xx x --A
( 0 0 0 1 0 0 ) 0 0 0000 0 0 0 0 0 0 00 | x x xxxx x x x x x 0 x xx x
( 0 0 0 1 0 0 ) 0 0 0000 0 0 0 0 0 0 00 | x x xxxx x x x x x 0 x xx x --B
( 0 0 0 1 0 0 ) 0 0 0000 0 0 0 0 0 0 00 | x x xxxx x x x x x 0 x xx x
( 0 0 0 1 0 0 ) 0 0 0000 0 0 0 0 0 0 00 | x x xxxx x x x x x 0 x xx x --A
( 0 0 0 1 0 0 ) 0 0 0000 0 0 0 0 0 0 00 | x x xxxx x x x x x 0 x xx x
( 0 0 0 1 0 0 ) 0 0 0000 0 0 0 0 0 0 00 | x x xxxx x x x x x 0 x xx x --B
( 0 0 0 1 0 0 ) 0 0 0000 0 0 0 0 0 0 00 | x x xxxx x x x x x 0 x xx x
( 0 0 0 1 0 0 ) 0 0 0000 0 0 0 0 0 0 00 | x x xxxx x x x x x 0 x xx x --A
( 0 0 0 1 0 0 ) 0 0 0000 0 0 0 0 0 0 00 | x x xxxx x x x x x 0 x xx x
( 0 0 0 1 0 0 ) 0 0 0000 0 0 0 0 0 0 00 | x x xxxx x x x x x 0 x xx x --B
( 0 0 0 1 0 0 ) 0 0 0000 0 0 0 0 0 0 00 | x x xxxx x x x x 0 0 x xx x
( 0 0 0 1 0 0 ) 0 0 0000 0 0 0 0 0 0 00 | x x xxxx x x x x 0 0 x xx x --A
( 0 0 0 1 0 0 ) 0 0 0000 0 0 0 0 0 0 00 | x x xxxx x x x x 0 0 x xx x
( 0 0 0 1 0 0 ) 0 0 0000 0 0 0 0 0 0 00 | x x xxxx x x x x 0 0 x xx x --B
( 0 0 0 1 0 0 ) 0 0 0000 0 0 0 0 0 0 00 | x x xxxx x x x x 0 0 x xx x
( 0 0 0 1 0 0 ) 0 0 0000 0 0 0 0 0 0 00 | x x xxxx x x x x 0 0 x xx x --A
( 0 0 0 1 0 0 ) 0 0 0000 0 0 0 0 0 0 00 | x x xxxx x x x x 0 0 x xx x
( 0 0 0 1 0 0 ) 0 0 0000 0 0 0 0 0 0 00 | x x xxxx x x x x 0 0 x xx x --B
( 0 0 0 1 0 0 ) 0 0 0000 0 0 0 0 0 0 00 | x x xxxx x x x x 0 0 x xx x
( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 00 | x 0 xxxx 0 0 0 0 0 0 x xx x --A
( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 00 | x 0 xxxx 0 0 0 0 0 0 x xx x
( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 00 | x 0 xxxx 0 0 0 0 0 0 x xx x --B
( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 00 | x 0 xxxx 0 0 0 0 0 0 x xx x
Check that chip Id can be read out (scan path 0):
D D D n n D D B B G G I P P P P | D H B B B R S P P P P P
S A E D D S S C D L r S m C B D | B d D O S e S R F F D R
h d x F R e e y a e a S o m y a | u r a w h q t e a a a e
i d e r e r l c t n n t d d t t | s C t n a u o j u u t s
f r c e s i e l a g t o e I e a | O y a e r e p e l l a c
t e u e e a c e I t p I n S | u c O r e s O c t t h
C s t z t l t 0 n h I n e | t l u O d t u t C e
k s e e I n l | e t u O t o d
n I | O t u d u
n | u t e l
| t e
|
( 0 1 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 00 | x 0 xxxx 0 0 0 0 0 0 x xx x --A
( 1 1 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 00 | x 0 xxxx 0 0 0 0 0 0 x xx x
( 0 1 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 00 | x 0 xxxx 0 0 0 0 0 0 x xx x --B
( 1 1 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 00 | x 0 xxxx 0 0 0 0 0 0 x xx x
( 0 1 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 00 | x 0 xxxx 0 0 0 0 0 0 x xx x --A
( 1 1 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 00 | x 0 xxxx 0 0 0 0 0 0 x xx x
( 0 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 0 0 xxxx 0 0 0 0 0 0 x xx x --B
( 1 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 1 0 xxxx 0 0 0 0 0 0 x xx x
( 0 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 1 0 xxxx 0 0 0 0 0 0 x xx x --A
( 1 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 0 0 xxxx 0 0 0 0 0 0 x xx x
( 0 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 0 0 xxxx 0 0 0 0 0 0 x xx x --B
( 1 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 1 0 xxxx 0 0 0 0 0 0 x xx x
( 0 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 1 0 xxxx 0 0 0 0 0 0 x xx x --A
( 1 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 0 0 xxxx 0 0 0 0 0 0 x xx x
( 0 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 0 0 xxxx 0 0 0 0 0 0 x xx x --B
( 1 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 0 0 xxxx 0 0 0 0 0 0 x xx x
( 0 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 0 0 xxxx 0 0 0 0 0 0 x xx x --A
( 1 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 0 0 xxxx 0 0 0 0 0 0 x xx x
( 0 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 0 0 xxxx 0 0 0 0 0 0 x xx x --B
( 1 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 1 0 xxxx 0 0 0 0 0 0 x xx x
( 0 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 1 0 xxxx 0 0 0 0 0 0 x xx x --A
( 1 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 0 0 xxxx 0 0 0 0 0 0 x xx x
( 0 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 0 0 xxxx 0 0 0 0 0 0 x xx x --B
( 1 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 1 0 xxxx 0 0 0 0 0 0 x xx x
( 0 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 1 0 xxxx 0 0 0 0 0 0 x xx x --A
( 1 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 0 0 xxxx 0 0 0 0 0 0 x xx x
( 0 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 0 0 xxxx 0 0 0 0 0 0 x xx x --B
( 1 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 1 0 xxxx 0 0 0 0 0 0 x xx x
( 0 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 1 0 xxxx 0 0 0 0 0 0 x xx x --A
( 1 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 1 0 xxxx 0 0 0 0 0 0 x xx x
( 0 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 1 0 xxxx 0 0 0 0 0 0 x xx x --B
( 1 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 1 0 xxxx 0 0 0 0 0 0 x xx x
( 0 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 1 0 xxxx 0 0 0 0 0 0 x xx x --A
( 1 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 0 0 xxxx 0 0 0 0 0 0 x xx x
( 0 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 0 0 xxxx 0 0 0 0 0 0 x xx x --B
( 1 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 1 0 xxxx 0 0 0 0 0 0 x xx x
( 0 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 1 0 xxxx 0 0 0 0 0 0 x xx x --A
( 1 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 0 0 xxxx 0 0 0 0 0 0 x xx x
( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 00 | x 0 xxxx 0 0 0 0 0 0 x xx x --B
( 1 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 00 | x 0 xxxx 0 0 0 0 0 0 x xx x
Shift In MyId (scan path 1) (Recall that MyId is only one bit so only one bit needs to be shifted in):
D D D n n D D B B G G I P P P P | D H B B B R S P P P P P
S A E D D S S C D L r S m C B D | B d D O S e S R F F D R
h d x F R e e y a e a S o m y a | u r a w h q t e a a a e
i d e r e r l c t n n t d d t t | s C t n a u o j u u t s
f r c e s i e l a g t o e I e a | O y a e r e p e l l a c
t e u e e a c e I t p I n S | u c O r e s O c t t h
C s t z t l t 0 n h I n e | t l u O d t u t C e
k s e e I n l | e t u O t o d
n I | O t u d u
n | u t e l
| t e
|
( 0 1 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 00 | x 0 xxxx 0 0 0 0 0 0 x xx x --A
( 1 1 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 00 | x 0 xxxx 0 0 0 0 0 0 x xx x
( 0 1 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 00 | x 0 xxxx 0 0 0 0 0 0 x xx x --B
( 1 1 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 00 | x 0 xxxx 0 0 0 0 0 0 x xx x
( 0 1 0 1 1 1 ) 0 0 0000 0 0 0 0 0 0 00 | x 0 xxxx 0 0 0 0 0 0 x xx x --A
( 1 1 0 1 1 1 ) 0 0 0000 0 0 0 0 0 0 00 | x 0 xxxx 0 0 0 0 0 0 x xx x
( 0 0 0 1 1 1 ) 1 0 0000 0 0 0 0 0 0 00 | x 0 xxxx 0 0 0 0 0 0 x xx x --B
( 1 0 0 1 1 1 ) 1 0 0000 0 0 0 0 0 0 00 | 1 0 xxxx 0 0 0 0 0 0 x xx x
( 0 0 0 1 1 1 ) 1 0 0000 0 0 0 0 0 0 00 | 1 0 xxxx 0 0 0 0 0 0 x xx x --A
( 0 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 1 0 xxxx 0 0 0 0 0 0 x xx x
( 0 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 1 0 xxxx 0 0 0 0 0 0 x xx x --B
( 0 0 0 1 1 0 ) 1 0 0000 0 0 0 0 0 0 00 | 1 0 xxxx 0 0 0 0 0 0 x xx x
SmallCacheInner-ClrAllVPV:
Do a ClearAllVPV (Memory|Special|Write)
Initiate ClearAllVPV(Adrs=Don'tCare, Data=Don'tCare):
( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 E F 33 | x 0 xxxx 0 0 0 0 0 0 x xx x --A
( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 E F 33 | x 0 xxxx 0 0 0 0 0 0 x xx x
( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 E F 22 | x 0 xxxx 0 0 0 0 1 0 x xx x --B
( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 22 | x 0 xxxx 0 0 0 0 1 0 x xx x
( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --A
( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x
( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 1 0 x xx x --B
( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 1 0 x xx x
( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --A
( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x
( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B
( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x
.