RML234.oracle
Pradeep Sindhu June 30, 1987 2:33:06 pm PDT
TEST COMPLETED Feb 12, 1987 [PSS]
Checked again after putting together cache top level June 30, 1987 2:32:50 pm PDT [PSS]
Note that clock supplied to circuit is half the speed of the oracle clock, so that one "cycle" corresponds to two lines in this file.
Signal Order is:
QStage1 LRM1 | ( LdRML2 nLdRML2 LdRML3 nLdRML3 LdRML4 nLdRML4 ) LRM4
First, pulse QStage1 for one cycle and check that all the Ld signals become non-X's:
1 0 | ( X X X X X X ) X
1 0 | ( X X X X X X ) X
0 0 | ( X X X X X X ) X
0 0 | ( 1 0 X X X X ) X
0 0 | ( 0 1 X X X X ) X
0 0 | ( 0 1 1 0 X X ) X
0 0 | ( 0 1 0 1 X X ) X
0 0 | ( 0 1 0 1 1 0 ) 0
0 0 | ( 0 1 0 1 0 1 ) 0
0 0 | ( 0 1 0 1 0 1 ) 0
Now, push different values through the pipe at max throughput and check they come out the other end with the right delay (value must be held at input for two cycles starting at a half cycle and ending at a half cycle):
1 0 | ( 0 1 0 1 0 1 ) 0
1 1 | ( 0 1 0 1 0 1 ) 0
0 1 | ( 0 1 0 1 0 1 ) 0
0 1 | ( 1 0 0 1 0 1 ) 0
1 1 | ( 0 1 0 1 0 1 ) 0
1 2 | ( 0 1 1 0 0 1 ) 0
0 2 | ( 0 1 0 1 0 1 ) 0
0 2 | ( 1 0 0 1 1 0 ) 1
1 2 | ( 0 1 0 1 0 1 ) 1
1 3 | ( 0 1 1 0 0 1 ) 1
0 3 | ( 0 1 0 1 0 1 ) 1
0 3 | ( 1 0 0 1 1 0 ) 2
1 3 | ( 0 1 0 1 0 1 ) 2
1 4 | ( 0 1 1 0 0 1 ) 2
0 4 | ( 0 1 0 1 0 1 ) 2
0 4 | ( 1 0 0 1 1 0 ) 3
1 4 | ( 0 1 0 1 0 1 ) 3
1 5 | ( 0 1 1 0 0 1 ) 3
0 5 | ( 0 1 0 1 0 1 ) 3
0 5 | ( 1 0 0 1 1 0 ) 4
1 5 | ( 0 1 0 1 0 1 ) 4
1 6 | ( 0 1 1 0 0 1 ) 4
0 6 | ( 0 1 0 1 0 1 ) 4
0 6 | ( 1 0 0 1 1 0 ) 5
1 6 | ( 0 1 0 1 0 1 ) 5
1 7 | ( 0 1 1 0 0 1 ) 5
0 7 | ( 0 1 0 1 0 1 ) 5
0 7 | ( 1 0 0 1 1 0 ) 6
1 7 | ( 0 1 0 1 0 1 ) 6
1 8 | ( 0 1 1 0 0 1 ) 6
0 8 | ( 0 1 0 1 0 1 ) 6
0 8 | ( 1 0 0 1 1 0 ) 7
1 8 | ( 0 1 0 1 0 1 ) 7
1 9 | ( 0 1 1 0 0 1 ) 7
0 9 | ( 0 1 0 1 0 1 ) 7
0 9 | ( 1 0 0 1 1 0 ) 8
1 9 | ( 0 1 0 1 0 1 ) 8
1 A | ( 0 1 1 0 0 1 ) 8
0 A | ( 0 1 0 1 0 1 ) 8
0 A | ( 1 0 0 1 1 0 ) 9
1 A | ( 0 1 0 1 0 1 ) 9
1 B | ( 0 1 1 0 0 1 ) 9
0 B | ( 0 1 0 1 0 1 ) 9
0 B | ( 1 0 0 1 1 0 ) A
1 B | ( 0 1 0 1 0 1 ) A
1 C | ( 0 1 1 0 0 1 ) A
0 C | ( 0 1 0 1 0 1 ) A
0 C | ( 1 0 0 1 1 0 ) B
1 C | ( 0 1 0 1 0 1 ) B
1 D | ( 0 1 1 0 0 1 ) B
0 D | ( 0 1 0 1 0 1 ) B
0 D | ( 1 0 0 1 1 0 ) C
1 D | ( 0 1 0 1 0 1 ) C
1 E | ( 0 1 1 0 0 1 ) C
0 E | ( 0 1 0 1 0 1 ) C
0 E | ( 1 0 0 1 1 0 ) D
1 E | ( 0 1 0 1 0 1 ) D
1 F | ( 0 1 1 0 0 1 ) D
0 F | ( 0 1 0 1 0 1 ) D
0 F | ( 1 0 0 1 1 0 ) E
0 F | ( 0 1 0 1 0 1 ) E
0 X | ( 0 1 1 0 0 1 ) E
0 X | ( 0 1 0 1 0 1 ) E
0 X | ( 0 1 0 1 1 0 ) F
Next, push a few values with increasing intervals between arrivals:
1 X | ( 0 1 0 1 0 1 ) F
1 A | ( 0 1 0 1 0 1 ) F
0 A | ( 0 1 0 1 0 1 ) F
0 A | ( 1 0 0 1 0 1 ) F
0 A | ( 0 1 0 1 0 1 ) F
0 X | ( 0 1 1 0 0 1 ) F
1 X | ( 0 1 0 1 0 1 ) F
1 B | ( 0 1 0 1 1 0 ) A
0 B | ( 0 1 0 1 0 1 ) A
0 B | ( 1 0 0 1 0 1 ) A
0 B | ( 0 1 0 1 0 1 ) A
0 X | ( 0 1 1 0 0 1 ) A
0 X | ( 0 1 0 1 0 1 ) A
0 X | ( 0 1 0 1 1 0 ) B
1 X | ( 0 1 0 1 0 1 ) B
1 C | ( 0 1 0 1 0 1 ) B
0 C | ( 0 1 0 1 0 1 ) B
0 C | ( 1 0 0 1 0 1 ) B
0 C | ( 0 1 0 1 0 1 ) B
0 X | ( 0 1 1 0 0 1 ) B
0 X | ( 0 1 0 1 0 1 ) B
0 X | ( 0 1 0 1 1 0 ) C
0 X | ( 0 1 0 1 0 1 ) C
0 X | ( 0 1 0 1 0 1 ) C
1 X | ( 0 1 0 1 0 1 ) C
1 D | ( 0 1 0 1 0 1 ) C
0 D | ( 0 1 0 1 0 1 ) C
0 D | ( 1 0 0 1 0 1 ) C
0 D | ( 0 1 0 1 0 1 ) C
0 X | ( 0 1 1 0 0 1 ) C
0 X | ( 0 1 0 1 0 1 ) C
0 X | ( 0 1 0 1 1 0 ) D
.