[_CD6_]<dragon7.0>SmallCache>Oracle>IOLRCam.oracle!3

IOLRCam.oracle
Paraminder Sahai July 21, 1987 11:01:32 am PDT

Pradeep Sindhu September 26, 1987 6:27:01 pm PDT

TEST COMPLETED July 21, 1987 11:02:08 am PDT

Note that clock supplied to circuit is half the speed of the oracle clock, so that one "cycle" corresponds to two lines in this file.

The Signal Order is:
CamSelect Reset AVM AVct xCSCmd1 PCtlDrABusRB PCtlDrABusRP xRdRCam xPartRMch
xDrRCamBL xLdRCabWR xEnCamSelExt BCycle1 RPValidIn RAdrsIn | RCamlfcCtlForFlags
RAdrsOut QStage1 LRM1ForVCam LRM1 ARM CamSelExt

Flush out x's from the control part:

0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( x 1 x x x ) ( x x x x x x x x x ) x x x x 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( x 1 x x 0 ) ( x x x x x x x x x ) x x x x 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( x 1 x x 0 ) ( x x x x x x x x x ) 0 x x x 0

In the following comments Lines 0,2 and 4 refer respectively to the first, second
and third line of IOLRCam.sch:

Note that Line 0 is selected when CamSelectExt is 4, Line 2 is selected when
CamSelectExt is 2 and Line 4 is selected when CamSelectExt is 1

Read each of the three lines

Read Line 0

0 0 0 1 0 0 0 1 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( x 1 x x 0 ) ( x x x x x x x x x ) 0 x x x 0

0 0 0 1 0 0 0 1 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 1 x x 0 ) ( x x x x x x x x x ) 0 x x x 0

4 0 0 1 0 0 0 1 0 0 0 1 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 0 1 0 ) ( x x x x x x x x x ) 0 x x x 4

4 0 0 1 0 0 0 0 0 0 0 1 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 0 1 0 ) ( x x x x x x x x x ) 0 x x x 4

4 0 1 1 0 1 1 0 0 0 0 1 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 0 1 1 ) ( 1 1 1 0 0 0 0 0 1 ) 0 x x x 4

0 0 1 1 0 1 1 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 1 ) ( 1 1 1 0 0 0 0 0 1 ) 0 x x x 0

Read Line 2

0 0 0 1 0 0 0 1 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 0 x x x 0

0 0 0 1 0 0 0 1 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 1 1 0 0 ) ( x x x x x x x x x ) 0 x x x 0

2 0 0 1 0 0 0 1 0 0 0 1 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 0 1 0 ) ( x x x x x x x x x ) 0 x x x 2

2 0 0 1 0 0 0 0 0 0 0 1 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 0 1 0 ) ( x x x x x x x x x ) 0 x x x 2

2 0 1 1 0 1 1 0 0 0 0 1 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 0 1 1 ) ( 1 1 1 0 1 0 0 0 1 ) 0 x x x 2

0 0 1 1 0 1 1 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 1 ) ( 1 1 1 0 1 0 0 0 1 ) 0 x x x 0

Read Line 4

0 0 0 1 0 0 0 1 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 0 x x x 0

0 0 0 1 0 0 0 1 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 1 1 0 0 ) ( x x x x x x x x x ) 0 x x x 0

1 0 0 1 0 0 0 1 0 0 0 1 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 0 1 0 ) ( x x x x x x x x x ) 0 x x x 1

1 0 0 1 0 0 0 0 0 0 0 1 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 0 1 0 ) ( x x x x x x x x x ) 0 x x x 1

1 0 1 1 0 1 1 0 0 0 0 1 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 0 1 1 ) ( 1 1 1 1 0 0 0 0 1 ) 0 x x x 1

0 0 1 1 0 1 1 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 1 ) ( 1 1 1 1 0 0 0 0 1 ) 0 x x x 0

Reread the lines with EnCamSelectExt = 0 to check that the page part alone can be read
( the block and valid bits will be read as 1 since the bit lines are precharged to 1 )

Line 0

0 0 0 1 0 0 0 1 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 0 x x x 0

0 0 0 1 0 0 0 1 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 1 1 0 0 ) ( x x x x x x x x x ) 0 x x x 0

4 0 0 1 0 0 0 1 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 0 1 0 ) ( x x x x x x x x x ) 0 x x x 0

4 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 0 1 0 ) ( x x x x x x x x x ) 0 x x x 0

4 0 1 1 0 1 1 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 0 1 1 ) ( 1 1 1 1 1 1 0 0 1 ) 0 x x x 0

0 0 1 1 0 1 1 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 1 ) ( 1 1 1 1 1 1 0 0 1 ) 0 x x x 0

Line 2

0 0 0 1 0 0 0 1 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 0 x x x 0

0 0 0 1 0 0 0 1 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 1 1 0 0 ) ( x x x x x x x x x ) 0 x x x 0

2 0 0 1 0 0 0 1 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 0 1 0 ) ( x x x x x x x x x ) 0 x x x 0

2 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 0 1 0 ) ( x x x x x x x x x ) 0 x x x 0

2 0 1 1 0 1 1 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 0 1 1 ) ( 1 1 1 1 1 1 0 0 1 ) 0 x x x 0

0 0 1 1 0 1 1 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 1 ) ( 1 1 1 1 1 1 0 0 1 ) 0 x x x 0

Line 4

0 0 0 1 0 0 0 1 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 0 x x x 0

0 0 0 1 0 0 0 1 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 1 1 0 0 ) ( x x x x x x x x x ) 0 x x x 0

1 0 0 1 0 0 0 1 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 0 1 0 ) ( x x x x x x x x x ) 0 x x x 0

1 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 0 1 0 ) ( x x x x x x x x x ) 0 x x x 0

1 0 1 1 0 1 1 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 0 1 1 ) ( 1 1 1 1 1 1 0 0 1 ) 0 x x x 0

0 0 1 1 0 1 1 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 1 ) ( 1 1 1 1 1 1 0 0 1 ) 0 x x x 0

Now test match circuitry (remember RPValid = 0 to match )

Check that Line 0 matches

0 0 0 1 0 0 0 0 0 1 1 0 1 0 ( 1 1 x 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 0 x x x 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 1 x x x 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 1 4 4 0 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 0 4 4 1 0

Check that Line 2 matches

0 0 0 1 0 0 0 0 0 1 1 0 1 0 ( 1 1 x 0 1 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 0 x x x 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 1 x x x 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 1 2 2 0 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 0 2 2 1 0

Check that Line 4 matches

0 0 0 1 0 0 0 0 0 1 1 0 1 0 ( 1 1 x 1 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 0 x x x 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 1 x x x 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 1 1 1 0 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 0 1 1 1 0

Check that RPValidin = 1 dosen't match

Line 0

0 0 0 1 0 0 0 0 0 1 1 0 1 1 ( 1 1 x 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 0 x x x 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 1 x x x 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 1 0 0 0 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 0 0 0 0 0

Line 2

0 0 0 1 0 0 0 0 0 1 1 0 1 1 ( 1 1 x 0 1 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 0 x x x 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 1 x x x 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 1 0 0 0 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 0 0 0 0 0

Line 4

0 0 0 1 0 0 0 0 0 1 1 0 1 1 ( 1 1 x 1 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 0 x x x 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 1 x x x 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 1 0 0 0 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 0 0 0 0 0

Check that all three lines match when partial match is enabled

0 0 0 1 0 0 0 0 1 1 1 0 1 0 ( 1 1 x 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 0 x x x 0

0 0 0 1 0 0 0 0 1 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 1 x x x 0

0 0 0 1 0 0 0 0 1 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 1 7 7 0 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 0 7 7 1 0

Check that we can read from more than one line when the page part has the same value

(the block part will read as 1 1 1) (xEnCamSelExt = 0)

0 0 0 1 0 0 0 1 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 0 ) ( x x x x x x x x x ) 0 x x x 0

0 0 0 1 0 0 0 1 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 1 1 0 0 ) ( x x x x x x x x x ) 0 x x x 0

6 0 0 1 0 0 0 1 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 0 1 0 ) ( x x x x x x x x x ) 0 x x x 0

6 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 0 1 0 ) ( x x x x x x x x x ) 0 x x x 0

6 0 1 1 0 1 1 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 0 1 1 ) ( 1 1 1 1 1 1 0 0 1 ) 0 x x x 0

0 0 1 1 0 1 1 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 1 0 1 ) ( 1 1 1 1 1 1 0 0 1 ) 0 x x x 0

.