SCacheNotes.tioga
Don Curry June 7, 1988 9:44:50 pm PDT
June 7, 1988 9:44:08 pm PDT
Removed IO2PC ? State from PCtl PmCode
June 1, 1988 2:18:45 pm PDT
Removed D flop from before BCtlLdFIFO8 in BCtl.sch
May 31, 1988 11:47:30 am PDT
Added PCtlLdRBufDataLo ← H to PmCode (PCWS10PC AND RamForP)
May 31, 1988 8:35:31 am PDT
Added RplySharedOut
Changed Schematics, code and oracles to make SharedOut = ~IO
May 26, 1988 10:29:21 am PDT
Removed BCmdLSBForRply34 (always TRUE).
Set Shared always TRUE in replies.
Set User/Fault to FALSE in replies - NOTE: bus side Bad IOWrite not checked.
May 24, 1988 1:43:31 pm PDT
Added buffers for array control signals.
May 23, 1988 7:44:04 pm PDT
Changed PCtl...VPV to agree with PmCodeImpl.
Included Christian's changes to PmCodeImpl (defaults ← 0 in two cases).
May 23, 1988 7:44:04 pm PDT
Modified PAll to test setting and clearing mulitple interrupt mask bits.
May 20, 1988 8:32:51 am PDT
Add Read IO and Write IO misses to SmallCacheInner-PAll and SmallCache-PAll.
May 20, 1988 8:32:51 am PDT
Removed TestCode inputs from FSM code and schematics.
May 20, 1988 8:30:57 am PDT
Set the hi word of the data cycle of WS to X's in the SmallCache-BAll.oracle.
Hi word can't be set up with fixed value in idle (copy of lo word) because we need to use the hi word to hold test words.
May 17, 1988 6:40:34 pm PTD
Fixed drawing error in PCtlDrABusPAdrsLo decode in PmCodeFSM.
May 17, 1988 6:40:34 pm PDT
Fixed - OR gate for computing LdRBufDataHiDr from LdRBufDataHi and ShiftEn was missing from SCache schematics.
May 17, 1988 6:40:34 pm PTD
Discovered that SmallCacheTest.sch does not work with bits/byte # 2 and output section is schematics. The header constructor needs a bused ground.
May 17, 1988 6:40:34 pm PDT
Modified SmallCachePmCodeImpl in three places where stack is referenced. Terminal warnings issued in the case of strange stack values but the effects now correspond to what FSM does.
Problem: Procedure impl of PmCode starts at Init=0 while FSM starts at Init=1 and PC's must be built into debug routines.
May 17, 1988 10:07:12 am PDT
Change SmallCachePmCodeImpl.mesa to begin with Init=1
Problem: X in the LSB (valid) when doing TestReadVCamPC
May 16, 1988 8:59:07 pm PDT
Changed decode of PCtlDrABusPAdrsLo to be 0000 or 0110 only
PCtlNonFSM.sch
PCtlFSMSC.sch
PCtlFSMPLA.sch
Problem: Bounds Fault in SmallCacheArrayImpl
May 16
Changed limits in shift code
SmallCacheInner-Debug.oracle
Perform the reset sequence:
Don Curry May 16, 1988 2:57:44 pm PDT
nDReset 0 for 24 clocks
nDReset 1 for 4 clocks
Check that chip Id can be read out (scan path 0):
Shift In address  000
Shift with DSelect 1010 0010 1011 1010
Shift In MyId (scan path 1) (Recall that MyId is only one bit so only one bit needs to be shifted in):
Shift In DAddress  001
Shift with DSelect 1
Write AID [09], Kernel Mode: 33
Read it back to check it [09]:33
Read In Two Blocks (this stuff is the same as the first two reads of SmallCacheInner-Pall):
Now do PReads to fill lines 7 and 6:
PReadMiss-MapMiss-NoVictim[50]:
Let the grant come here, so we send our MapRqst E150 3333
Here's our map request on our input wires, followed immediately by the MapRply E9DE 0000
Give the grant for the RBRqst 01D0 xxxx
And shortly thereafter the RBRply 09D0 ABC1 BAC2 CAB3 CBA4
PReadMiss-MapHit-NoVictim[59]
Give the grant for the RBRqst 01D9 xxxx
And shortly thereafter the RBRply 09D9 AABB CCDD EEFF 8899
Now Let SStopIn come in to freeze the cache
Shift In DAddress 01 with SStop?
Shift In DAddress 01 with ~SStop?
Shift In WdAdrs and PC and (scan path 3) (Recall that WdAdrs is 3 bits and PC is 7 bits)
Shift In DAddress  011
Shift in the value TestResetVictimPC = 4C Hex; WdAdrs=0
Shift with DSelect 100 1100 000
Execute TestResetVictimPC by holding DExecute high for 1 cycle
DExecute with DSelect 1 cycle
Shift in the value TestReadVCamPC = 4B Hex; WdAdrs=0
Shift with DSelect 100 1011 000
Execute TestReadVCamPC by holding DExecute high for a cycle
DExecute with DSelect 1 cycle
Now shift out the contents of RequestBufHi register (scan path 2) and check if we get the expected value
Shift In DAddress 010
Shift with DSelect 11010101 or 10000000
ABus Source Codes
ABusIOOld: 8                x
ABusIONew: 9                x
ABusIOAId: 12                x
ABusIOFault: 13                x
ABusFault:  8                x
ABusPAdd:  0 PAHi   PALo
ABusRqstBuf: 1   RqstBuf
ABusVCam: 4     PALo VP VB
forbidden:  5
ABusCam:  6     PALo   VB RP
ABusRCam:  7           RP  RB
PCtlDrABusPAdrsHi 0000
PCtlDrABusRqstBuf   0001
PCtlDrABusPAdrsLo    0xx0
PCtlDrABusVP        010x
PCtlDrABusVB          01x0
PCtlDrABusRP            011x
PCtlDrABusRB              01x1
drive ABus MSB                1xxx
Array Control Loads
Here are the loads (expressed in n/p channel lengths, plus some in N/P diff area when the signal attacks a pass gate) for all the control signals received by the array (all loads have already been doubled to account for CAM symmetry):
Signal   n   p  Used in
Clock   Do a separate pass for this one
d�
xCSCmd   180   648  CSMuxInterface.sch
    16x5N, 32x5P  *2  pass gates in VictimInterface
d←ld← 25 + (SCParms.numMemLines+5)/6 + 4
assume 25 for SC
Reset   4*nRamLines   CamCtlCell.sch
    96   144  VictimInterface.sch
d�
BAREn   256   512  BARData.sch
d←(SCParms.numMemLines+5)/6 + 24
xLdVCamWR  64   128  RML1Interface.sch
    32*16  32*32 CamInterfaceFFEn.sch
    32   64  VCamAMInterface.sch
    4*nRamLines 6*nRamLines AMCell.sch (ClampM)
d←(SCParms.numMemLines+5)/6 + 24
xLdRCamWR  64   128  RML1Interface.sch
    32*16  32*32 CamInterfaceFFEn.sch
    4*nRamLines 6*nRamLines RCamAMCell.sch (ClampRM)
d←(SCParms.numMemLines+2)/3 + 5
LdVML   120   240  VCamAMInterface.sch
    8*nRamLines   AMCell.sch
d�
nPartVMch  7*32  7*32 CamInterfaceDriverCell.sch
nxPartRMch  7*32  7*32 CamInterfaceDriverCell.sch
d𡤈
PCtlFrzVictim  150   300  VictimInterface.sch
nEnRS   120   240  RSMuxInterface.sch
    50   100  SharedOwnerInterface.sch
RBCycle2  32   64  BigFF.sch/VCamAMInterface.sch
    32   64  BigFF.sch/RML23Interface.sch
    80   80  VCamAMInterface.sch
d←(SCParms.numMemLines+5)/6
PCtlClrAllVPV 4*nRamLines   CamCtlCell.sch
d ←(SCParms.numMemLines+2)/3
ClrVPV   8*nRamLines   CamCtlCell.sch
No buffering
VAdrsInOut  4x8N, 5x10P  *2  5x16N, 5x32P  *2 outputs
RAdrsIn   4x8N, 5x10P  *2  CamInterfaceFFEn.sch
FlagsIn   4x8N, 5x10P  *2  pass gates in CamInterfaceFFEn.sch
BCtlSetOw  108   216  SharedOwnerInterface.sch
SetSh   108   216  SharedOwnerInterface.sch
xWtRam   52   152  BigFF.sch/SharedOwnerInterface.sch
xRSCmd   60   216  RSMuxInterface.sch
VPValidIn  16   32  CamCtlInterfaceFF.sch
ClrSh   16   32  SharedOwnerInterface.sch
nxByteSel  16   16  SharedOwnerInterface.sch
nxWdSel   46   46  SharedOwnerInterface.sch
nxSelWdData  36   72  SharedOwnerInterface.sch
BCtlClrOw  16   32  SharedOwnerInterface.sch
PWtInProg  32   64  BigFF.sch/SharedOwnerInterface.sch
xEnCamSel  32   64  BigFF.sch/CSMuxInterface.sch
xDrRCamBL  32   64  BigFF.sch/VictimInterface.sch
PCtlDrABusRB 96   64  VictimInterface.sch
PCtlDrABusRP 96   64  VictimInterface.sch
xLdRCamRL  32   64  BigFF.sch/VictimInterface.sch
xCRCamPr  32   64  BigFF.sch/VictimInterface.sch
xDrVCamBL  32   64  BigFF.sch/VictimInterface.sch
PCtlDrABusVP 96   64  VictimInterface.sch
PCtlDrABusVB 96   64  VictimInterface.sch
xLdVCamRL  32   64  BigFF.sch/VictimInterface.sch
xCVCamPr  32   64  BigFF.sch/VictimInterface.sch
xLdUse   40   20  VictimInterface.sch
PCtlResetVictim 16   64  VictimInterface.sch
PCtlShftVictim4 20   40  VictimInterface.sch
xEnCamSelExt  32   64  BigFF.sch/VCamAMInterface.sch
nPMFlags  32   32  CamInterfaceDriverCell.sch
RPValidIn  16   32  CamCtlInterfaceFF.sch