Detailed Status
Block Sch Sim Layout
RCam Yes Yes Yes
RCamIfc Yes Yes No
VCam Yes Yes Yes
VCamIfc Yes Yes No
RMPipe Yes Yes No
Victim Yes Yes No
CSMux Yes Yes No
RSMux Yes Yes No
ShdOwn Yes Yes No
Ram Yes Yes Yes
RamIfc Yes Yes No
IOBlk No No No
OutputSec Yes Yes No
BlkAsmRg Yes Yes No
CSWCmp Yes No No
InputSec Yes No No
Snooper Yes No No
PInterface Yes No No
RCamIlkCtl Yes Yes No
RamIlkCtl Yes Yes No
PIntCtl Yes No No
BIntCtl Yes No No
What's left and When It'll be Done
· Completion of individual block simulations
March 10
· Psuedocode to Microcode Translation
March 20
· Transistor level Simulation of Entire Chip
March 31
· Layout, Assembly and Floorplanning
May 31 (assuming I have full-time help)