DIRECTORY Rope, SCParms; SCParmsImpl: CEDAR PROGRAM IMPORTS Rope EXPORTS SCParms ~ BEGIN OPEN SCParms; numBitsPerByte: PUBLIC NAT _ 0; numBytesPerWord: PUBLIC NAT _ 0; numWordsPerCycle: PUBLIC NAT _ 2; -- Fixed by the architecture numCyclesPerLine: PUBLIC NAT _ 0; numMemLines: PUBLIC NAT _ 0; numIOLines: PUBLIC NAT _ 0; numFIFOLines: PUBLIC NAT _ 0; numTimeOutCounterBits: PUBLIC NAT _ 0; smallCacheSpec: PUBLIC CellTypeSpec _ Unspecified; sCacheHybridSpec: PUBLIC CellTypeSpec _ Unspecified; sCacheSpec: PUBLIC CellTypeSpec _ Unspecified; innerSpec: PUBLIC CellTypeSpec _ Unspecified; leftCtlSpec: PUBLIC CellTypeSpec _ Unspecified; rightCtlSpec: PUBLIC CellTypeSpec _ Unspecified; dataPathSpec: PUBLIC CellTypeSpec _ Unspecified; arraySpec: PUBLIC CellTypeSpec _ Unspecified; outputSectionSpec: PUBLIC CellTypeSpec _ Unspecified; bCyclePipeSpec: PUBLIC CellTypeSpec _ Unspecified; bWdWtPipeSpec: PUBLIC CellTypeSpec _ Unspecified; vPagePattern: PUBLIC ROPE _ NIL; vBlock0Pattern: PUBLIC ROPE _ NIL; vBlock1Pattern: PUBLIC ROPE _ NIL; vBlock2Pattern: PUBLIC ROPE _ NIL; vBlock3Pattern: PUBLIC ROPE _ NIL; vBlock4Pattern: PUBLIC ROPE _ NIL; vBlock5Pattern: PUBLIC ROPE _ NIL; rPagePattern: PUBLIC ROPE _ NIL; rBlock0Pattern: PUBLIC ROPE _ NIL; rBlock1Pattern: PUBLIC ROPE _ NIL; rBlock2Pattern: PUBLIC ROPE _ NIL; rBlock3Pattern: PUBLIC ROPE _ NIL; rBlock4Pattern: PUBLIC ROPE _ NIL; rBlock5Pattern: PUBLIC ROPE _ NIL; numBitsPerWord: PUBLIC NAT; numBitsPerCycle: PUBLIC NAT; numBitsPerLine: PUBLIC NAT; numWordsPerLine: PUBLIC NAT; logNumWordsPerLine: PUBLIC NAT; logNumCyclesPerLine: PUBLIC NAT; numPageBits: PUBLIC NAT; numBlockBits: PUBLIC NAT; numDevIdBits: PUBLIC NAT; numDevTypeBits: PUBLIC NAT; numZerosBitsInHeader: PUBLIC NAT; Set: PUBLIC PROC [NumBitsPerByte: NAT _ 8, NumBytesPerWord: NAT _ 4, NumCyclesPerLine: NAT _ 4, NumMemLines: NAT _ 4, NumIOLines: NAT _ 3, NumFIFOLines: NAT _ 4, NumTimeOutCounterBits: NAT _ 10] RETURNS [INT] ~ { temp: NAT; numBitsPerByte _ NumBitsPerByte; numBytesPerWord _ NumBytesPerWord; numCyclesPerLine _ NumCyclesPerLine; numMemLines _ NumMemLines; numIOLines _ NumIOLines; numFIFOLines _ NumFIFOLines; numTimeOutCounterBits _ NumTimeOutCounterBits; numBitsPerWord _ numBitsPerByte*numBytesPerWord; numBitsPerCycle _ numBitsPerWord*numWordsPerCycle; numBitsPerLine _ numBitsPerCycle*numCyclesPerLine; numWordsPerLine _ numWordsPerCycle*numCyclesPerLine; logNumWordsPerLine _ Log2[numWordsPerLine]; logNumCyclesPerLine _ Log2[numCyclesPerLine]; numPageBits _ (22*(numBitsPerWord-logNumWordsPerLine))/29; numBlockBits _ numBitsPerWord-numPageBits-logNumWordsPerLine; BEGIN IF numBlockBits < 3 THEN {temp _ numBlockBits; numBlockBits _ numPageBits; numPageBits _ temp}; IF numBlockBits < 3 THEN ERROR; END; numDevIdBits _ IF (numBitsPerWord-7) < 10 THEN (numBitsPerWord-7) ELSE 10; numDevTypeBits _ numBitsPerWord-(numDevIdBits+numBlockBits+logNumWordsPerLine); numZerosBitsInHeader _ numBitsPerCycle-(7+numDevIdBits+numBitsPerWord); BEGIN vPagePattern _ "1"; -- IO bit FOR i: NAT IN [0..numPageBits) DO vPagePattern _ Rope.Cat[vPagePattern, "0"]; ENDLOOP; vBlock0Pattern _ vBlock1Pattern _ vBlock2Pattern _ vBlock3Pattern _ vBlock4Pattern _ vBlock5Pattern _ ""; FOR i: NAT IN [0..numBlockBits-3) DO vBlock0Pattern _ Rope.Cat[vBlock0Pattern, "0"]; vBlock1Pattern _ Rope.Cat[vBlock1Pattern, "0"]; vBlock2Pattern _ Rope.Cat[vBlock2Pattern, "0"]; vBlock3Pattern _ Rope.Cat[vBlock3Pattern, "0"]; vBlock4Pattern _ Rope.Cat[vBlock4Pattern, "0"]; vBlock5Pattern _ Rope.Cat[vBlock5Pattern, "0"]; ENDLOOP; vBlock0Pattern _ Rope.Cat[vBlock0Pattern, "000"]; vBlock1Pattern _ Rope.Cat[vBlock1Pattern, "001"]; vBlock2Pattern _ Rope.Cat[vBlock2Pattern, "010"]; vBlock3Pattern _ Rope.Cat[vBlock3Pattern, "011"]; vBlock4Pattern _ Rope.Cat[vBlock4Pattern, "100"]; vBlock5Pattern _ Rope.Cat[vBlock5Pattern, "101"]; END; BEGIN rPagePattern _ "1"; -- IO bit FOR i: NAT IN [0..numPageBits-numDevIdBits-1) DO rPagePattern _ Rope.Cat[rPagePattern, "0"]; ENDLOOP; rPagePattern _ Rope.Cat[rPagePattern, "1"]; -- 1 bit for DeviceType FOR i: NAT IN [numPageBits-numDevIdBits..numPageBits) DO rPagePattern _ Rope.Cat[rPagePattern, "X"]; ENDLOOP; rBlock0Pattern _ rBlock1Pattern _ rBlock2Pattern _ rBlock3Pattern _ rBlock4Pattern _ rBlock5Pattern _ ""; FOR i: NAT IN [0..numBlockBits-3) DO rBlock0Pattern _ Rope.Cat[rBlock0Pattern, "0"]; rBlock1Pattern _ Rope.Cat[rBlock1Pattern, "0"]; rBlock2Pattern _ Rope.Cat[rBlock2Pattern, "0"]; rBlock3Pattern _ Rope.Cat[rBlock3Pattern, "0"]; rBlock4Pattern _ Rope.Cat[rBlock4Pattern, "0"]; rBlock5Pattern _ Rope.Cat[rBlock5Pattern, "0"]; ENDLOOP; rBlock0Pattern _ Rope.Cat[rBlock0Pattern, "000"]; rBlock1Pattern _ Rope.Cat[rBlock1Pattern, "001"]; rBlock2Pattern _ Rope.Cat[rBlock2Pattern, "010"]; rBlock3Pattern _ Rope.Cat[rBlock3Pattern, "011"]; rBlock4Pattern _ Rope.Cat[rBlock4Pattern, "100"]; rBlock5Pattern _ Rope.Cat[rBlock5Pattern, "101"]; END; RETURN[NumBitsPerByte*NumBytesPerWord*NumCyclesPerLine*NumMemLines*NumIOLines*NumFIFOLines]; }; SetCellTypeSpecs: PUBLIC PROC [ SmallCacheSpec: CellTypeSpec _ Schematic, SCacheHybridSpec: CellTypeSpec _ Schematic, SCacheSpec: CellTypeSpec _ Schematic, InnerSpec: CellTypeSpec _ Schematic, LeftCtlSpec: CellTypeSpec _ Schematic, RightCtlSpec: CellTypeSpec _ Schematic, DataPathSpec: CellTypeSpec _ Schematic, ArraySpec: CellTypeSpec _ Schematic, OutputSectionSpec: CellTypeSpec _ Schematic, BCyclePipeSpec: CellTypeSpec _ Schematic, BWdWtPipeSpec: CellTypeSpec _ Schematic ] ~ { smallCacheSpec _ SmallCacheSpec; sCacheHybridSpec _ SCacheHybridSpec; sCacheSpec _ SCacheSpec; innerSpec _ InnerSpec; leftCtlSpec _ LeftCtlSpec; rightCtlSpec _ RightCtlSpec; dataPathSpec _ DataPathSpec; arraySpec _ ArraySpec; outputSectionSpec _ OutputSectionSpec; bCyclePipeSpec _ BCyclePipeSpec; bWdWtPipeSpec _ BWdWtPipeSpec }; PagePatternHi: PUBLIC PROC [pagePattern: ROPE] RETURNS [ROPE] ~ { RETURN[Rope.Substr[pagePattern, 0, numPageBits+1-numDevIdBits]]; }; PagePatternLo: PUBLIC PROC [pagePattern: ROPE] RETURNS [ROPE] ~ { RETURN[Rope.Substr[pagePattern, numPageBits+1-numDevIdBits, numDevIdBits]]; }; Log2: PROC [n: INT] RETURNS [log: INT _ 0] ~ { WHILE n > 1 DO n _ n/2; log _ log+1 ENDLOOP }; END. SCParmsImpl.mesa Copyright c 1986 by Xerox Corporation. All rights reserved. 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