<> <> <> <> <<>> <> <<>> DIRECTORY CD, Core, CoreCreate, Sisyph, TilingClass; SmallCacheUtils: CEDAR DEFINITIONS ~ BEGIN <> CellType : TYPE = Core.CellType; CellTypes: TYPE = LIST OF Core.CellType; Properties : TYPE = Core.Properties; ROPE: TYPE = Core.ROPE; Wire: TYPE = Core.Wire; Wires: TYPE = Core.Wires; PA: TYPE = CoreCreate.PA; WR: TYPE = CoreCreate.WR; <> Names: TYPE = LIST OF ROPE; <> Log2: PROC [n: INT] RETURNS [INT]; ComRecord: PROC [pattern: ROPE, cx: Sisyph.Context, ctName: ROPE] RETURNS [ct: CellType]; RecordX: PROC [obNames: Names, cx: Sisyph.Context, ctName: ROPE] RETURNS [ct: CellType]; RamInterfaceRout: PROC [cx: Sisyph.Context] RETURNS [ct: CellType]; Interleave: PROC [b: NAT] RETURNS [public: Core.Wires]; Interleave2: PROC [b: NAT] RETURNS [public: Core.Wires]; FuseGroups: PROC [numGroups, groupSize: NAT] RETURNS [public: Core.Wires]; Flatten: PROC [numGroups, groupSize: NAT] RETURNS [public: Core.Wires]; HexToBin: PROC [h: ROPE] RETURNS [b: ROPE _ NIL]; BinToHex: PROC [b: ROPE] RETURNS [h: ROPE _ NIL]; BlockToInterleavedBlock: PROC [b: ROPE] RETURNS [ib: ROPE]; InterleavedBlockToBlock: PROC [ib: ROPE] RETURNS [b: ROPE]; GetDesign: PROC [name: ROPE] RETURNS [design: CD.Design]; LayoutDesign: PROC [] RETURNS [design: CD.Design]; <> workingDirectory: ROPE; END.