
<<SmallCacheBCyclePipe.mesa>>
    <<Pradeep Sindhu April 27, 1988 9:58:12 am PDT>>
    <<Paraminder Sahai September 24, 1987 0:28:32 am PDT>>
    <<Don Curry May 31, 1988 8:55:41 am PDT>>
<<>>
<<>>
    DIRECTORY
        Core, CoreClasses, CoreCreate, CoreFlat, Ports, Rosemary, RosemaryUser, SmallCacheLogic, SCParms, Sisyph;
<<>>
    SmallCacheBCyclePipe: CEDAR PROGRAM
    IMPORTS CoreClasses, CoreCreate, CoreFlat, Ports, Rosemary, SCParms, Sisyph
    EXPORTS SmallCacheLogic
    ~ BEGIN OPEN SmallCacheLogic;

<<Constants and Type Defs>>
    NumBitsPerWord: NAT = SCParms.numBitsPerWord;
    NumBitsPerCycle: NAT = SCParms.numBitsPerCycle;
    LogNumWordsPerLine: NAT = SCParms.logNumWordsPerLine;

    InternalState: TYPE = RECORD [
        a, b, c, d: LevelSequence _ NIL 
        ];
    State: TYPE = REF StateRec;
    StateRec: TYPE = RECORD [
    master: InternalState,
    slave: InternalState
        ];
<<Signal Defs>>
    BCycle6, BCycle4, BCycle2, RAdrs, D, Q, BWdAdrs56, BCmd34, RplyShared34, BCmd2, Clock: NAT;
<<Public Procs>>

    BCyclePipe: PUBLIC PROC [cts: CellTypeSpec, cx: Context] RETURNS [ct: CellType] = {
        public: Wire _ CoreCreate.WireList[LIST[CoreCreate.Seq["RAdrs",NumBitsPerWord],
        CoreCreate.Seq["D",NumBitsPerCycle], CoreCreate.Seq["Q",NumBitsPerCycle], CoreCreate.Seq["BCmd2",5], 
        CoreCreate.Seq["BCmd34",5], CoreCreate.Seq["BWdAdrs56",LogNumWordsPerLine], "BCycle6", "BCycle4", "BCycle2", 
        "RplyShared34", "Clock"]];

        SELECT cts FROM
            Schematic    => ct _ Sisyph.ES["BCyclePipe.sch", cx];
            Procedure    => {
                ct _ CoreClasses.CreateUnspecified[public: public]; 
                [] _ Rosemary.BindCellType[cellType: ct, roseClassName: bCyclePipeName];
                [] _ CoreFlat.CellTypeCutLabels[ct, "Logic"];
                Ports.InitPorts[ct, ls, none, "D"];
                Ports.InitPorts[ct, l, none, "BCycle6", "BCycle4", "BCycle2", "Clock"];
                Ports.InitPorts[ct, l, drive, "RplyShared34"];
                Ports.InitPorts[ct, ls, drive, "RAdrs"];
                Ports.InitPorts[ct, ls, drive, "BCmd2"];
                Ports.InitPorts[ct, ls, drive, "BCmd34"];
                Ports.InitPorts[ct, ls, drive, "BWdAdrs56"];
                Ports.InitPorts[ct, ls, drive, "Q"]
                };
            CoreFile    => ERROR
            ENDCASE    => ERROR
    };
<<Internal Procs>>
    Init: Rosemary.InitProc = {
        s: State;

        IF oldStateAny=NIL
            THEN {
                s _ NEW [StateRec];
                s.master.a _ NEW[LevelSequenceRec[NumBitsPerCycle]];
                s.master.b _ NEW[LevelSequenceRec[NumBitsPerCycle]];
                s.master.c _ NEW[LevelSequenceRec[NumBitsPerCycle]];
                s.master.d _ NEW[LevelSequenceRec[NumBitsPerCycle]];

                s.slave.a _ NEW[LevelSequenceRec[NumBitsPerCycle]];
                s.slave.b _ NEW[LevelSequenceRec[NumBitsPerCycle]];
                s.slave.c _ NEW[LevelSequenceRec[NumBitsPerCycle]];
                s.slave.d _ NEW[LevelSequenceRec[NumBitsPerCycle]];
                }
            ELSE s _ NARROW[oldStateAny, State];

        Ports.SetLS[s.master.a, X];
        Ports.SetLS[s.master.b, X];
        Ports.SetLS[s.master.c, X];
        Ports.SetLS[s.master.d, X];

        Ports.SetLS[s.slave.a, X];
        Ports.SetLS[s.slave.b, X];
        Ports.SetLS[s.slave.c, X];
        Ports.SetLS[s.slave.d, X];

        [BCycle6, BCycle4, BCycle2, RAdrs, D, Q, BWdAdrs56, BCmd34, RplyShared34, BCmd2, Clock ] _ Ports.PortIndexes[cellType.public,  
        "BCycle6", "BCycle4", "BCycle2", "RAdrs", "D", "Q", "BWdAdrs56", "BCmd34", "RplyShared34", "BCmd2", "Clock" ];

        stateAny _ s;
        };

    Simple: Rosemary.EvalProc = {
        s: State _ NARROW[stateAny];

        IF NOT clockEval THEN SELECT p[Clock].l FROM
            L => {
                Ports.CopyLS[p[D].ls, s.master.a];
                IF p[BCycle2].l=H THEN Ports.CopyLS[s.slave.a, s.master.b];
                IF p[BCycle4].l=H THEN {
                    Ports.CopyLS[s.slave.b, s.master.c];
                    s.master.c[4*2] _ H;        -- Reply     (4=>8 because of interleaving)
                    s.master.c[5*2] _ L;        -- No Fault
                    s.master.c[6*2] _ Ports.NotL[s.master.c[0]]}; -- Shared = is memory operation
                IF p[BCycle6].l=H THEN Ports.CopyLS[s.slave.c, s.master.d];
                };
            H => {
                Ports.CopyLS[s.master.a, s.slave.a];
                Ports.CopyLS[s.master.b, s.slave.b];
                Ports.CopyLS[s.master.c, s.slave.c];
                Ports.CopyLS[s.master.d, s.slave.d];
                };
            X => {
                Ports.SetLS[s.master.a, X];
                Ports.SetLS[s.master.b, X];
                Ports.SetLS[s.master.c, X];
                Ports.SetLS[s.master.d, X];

                Ports.SetLS[s.slave.a, X];
                Ports.SetLS[s.slave.b, X];
                Ports.SetLS[s.slave.c, X];
                Ports.SetLS[s.slave.d, X];
                };
            ENDCASE => ERROR;

        Ports.CopyLS[s.slave.d, p[Q].ls];
        FOR i:NAT IN [0..NumBitsPerWord) DO
            p[RAdrs].ls[i] _ s.slave.a[2*i+1];
            ENDLOOP;
        FOR i:NAT IN [0..4] DO
            p[BCmd2].ls[i] _ s.slave.a[2*i];
            p[BCmd34].ls[i] _ s.slave.b[2*i];
            ENDLOOP;
        p[RplyShared34].l _ s.slave.b[12];
        FOR i:NAT IN [0..LogNumWordsPerLine) DO
            p[BWdAdrs56].ls[i] _ s.slave.c[2*(NumBitsPerWord-LogNumWordsPerLine+i)+1]
            ENDLOOP;
        };

    bCyclePipeName: ROPE = Rosemary.Register[roseClassName: "SmallCacheBCyclePipe", init: Init, evalSimple: Simple, 
    scheduleIfClockEval: TRUE];
    END.
<<>>