[_CD6_]<dragon7.0>SmallCache>Code>SCParmsImpl.mesa!16

SCParmsImpl.mesa

Written by: Pradeep Sindhu, October 2, 1986 10:52:55 pm PDT

Pradeep Sindhu, April 29, 1988 3:56:13 pm PDT

Don Curry June 10, 1988 1:23:38 pm PDT

DIRECTORY

Rope, SCParms;

SCParmsImpl: CEDAR PROGRAM

IMPORTS Rope

EXPORTS SCParms

~ BEGIN OPEN SCParms;

Independent Parameters

numBitsPerByte: PUBLIC NAT ← 0;

numBytesPerWord: PUBLIC NAT ← 0;

numWordsPerCycle: PUBLIC NAT ← 2; -- Fixed by the architecture

numCyclesPerLine: PUBLIC NAT ← 0;

numMemLines: PUBLIC NAT ← 0;

numIOLines: PUBLIC NAT ← 0;

numFIFOLines: PUBLIC NAT ← 0;

numTimeOutCounterBits: PUBLIC NAT ← 0;

smallCacheSpec: PUBLIC CellTypeSpec ← Unspecified;

sCacheHybridSpec: PUBLIC CellTypeSpec ← Unspecified;

sCacheSpec: PUBLIC CellTypeSpec ← Unspecified;

innerSpec: PUBLIC CellTypeSpec ← Unspecified;

leftCtlSpec: PUBLIC CellTypeSpec ← Unspecified;

rightCtlSpec: PUBLIC CellTypeSpec ← Unspecified;

dataPathSpec: PUBLIC CellTypeSpec ← Unspecified;

arraySpec: PUBLIC CellTypeSpec ← Unspecified;

outputSectionSpec: PUBLIC CellTypeSpec ← Unspecified;

bCyclePipeSpec: PUBLIC CellTypeSpec ← Unspecified;

bWdWtPipeSpec: PUBLIC CellTypeSpec ← Unspecified;

vPagePattern: PUBLIC ROPE ← NIL;

vBlock0Pattern: PUBLIC ROPE ← NIL;

vBlock1Pattern: PUBLIC ROPE ← NIL;

vBlock2Pattern: PUBLIC ROPE ← NIL;

vBlock3Pattern: PUBLIC ROPE ← NIL;

vBlock4Pattern: PUBLIC ROPE ← NIL;

vBlock5Pattern: PUBLIC ROPE ← NIL;

rPagePattern: PUBLIC ROPE ← NIL;

rBlock0Pattern: PUBLIC ROPE ← NIL;

rBlock1Pattern: PUBLIC ROPE ← NIL;

rBlock2Pattern: PUBLIC ROPE ← NIL;

rBlock3Pattern: PUBLIC ROPE ← NIL;

rBlock4Pattern: PUBLIC ROPE ← NIL;

rBlock5Pattern: PUBLIC ROPE ← NIL;

Dependent Parameters

numBitsPerWord: PUBLIC NAT;

numBitsPerCycle: PUBLIC NAT;

numBitsPerLine: PUBLIC NAT;

numWordsPerLine: PUBLIC NAT;

logNumWordsPerLine: PUBLIC NAT;

logNumCyclesPerLine: PUBLIC NAT;

numPageBits: PUBLIC NAT;

numBlockBits: PUBLIC NAT;

numDevIdBits: PUBLIC NAT;

numDevTypeBits: PUBLIC NAT;

numZerosBitsInHeader: PUBLIC NAT;

Parameter Constraints

numBitsPerWord e 8 (from BCmd+RplySh+M/F+Id=8)

numWordsPerLine e 2 (need to take log and have it be > 0)

numCyclesPerLine e 2 (need to take log and have it be > 0)

numBlockBits e 3 (need 5 IO lines, so block address must be at least 3 bits)

Exported Procs

Set: PUBLIC PROC [NumBitsPerByte: NAT ← 8, NumBytesPerWord: NAT ← 4, NumCyclesPerLine: NAT ← 4, NumMemLines: NAT ← 4, NumIOLines: NAT ← 3, NumFIFOLines: NAT ← 4, NumTimeOutCounterBits: NAT ← 10] RETURNS [INT] ~ {

temp: NAT;

numBitsPerByte ← NumBitsPerByte;

numBytesPerWord ← NumBytesPerWord;

numCyclesPerLine ← NumCyclesPerLine;

numMemLines ← NumMemLines;

numIOLines ← NumIOLines;

numFIFOLines ← NumFIFOLines;

numTimeOutCounterBits ← NumTimeOutCounterBits;

numBitsPerWord ← numBitsPerByte*numBytesPerWord;

numBitsPerCycle ← numBitsPerWord*numWordsPerCycle;

numBitsPerLine ← numBitsPerCycle*numCyclesPerLine;

numWordsPerLine ← numWordsPerCycle*numCyclesPerLine;

logNumWordsPerLine ← Log2[numWordsPerLine];

logNumCyclesPerLine ← Log2[numCyclesPerLine];

numPageBits ← (22*(numBitsPerWord-logNumWordsPerLine))/29;

numBlockBits ← numBitsPerWord-numPageBits-logNumWordsPerLine;

Exchange numBlock and numPage bits if numBlock bits is too small

BEGIN

IF numBlockBits < 3 THEN {temp ← numBlockBits; numBlockBits ← numPageBits; numPageBits ← temp};

IF numBlockBits < 3 THEN ERROR;

END;

numDevIdBits ← IF (numBitsPerWord-7) < 10 THEN (numBitsPerWord-7) ELSE 10;

numDevTypeBits ← numBitsPerWord-(numDevIdBits+numBlockBits+logNumWordsPerLine);

numZerosBitsInHeader ← numBitsPerCycle-(7+numDevIdBits+numBitsPerWord);

Initialize the virtual page and block patterns

BEGIN

vPagePattern ← "1"; -- IO bit

FOR i: NAT IN [0..numPageBits) DO

vPagePattern ← Rope.Cat[vPagePattern, "0"];

ENDLOOP;

vBlock0Pattern ← vBlock1Pattern ← vBlock2Pattern ← vBlock3Pattern ← vBlock4Pattern ← vBlock5Pattern ← "";

FOR i: NAT IN [0..numBlockBits-3) DO

vBlock0Pattern ← Rope.Cat[vBlock0Pattern, "0"];

vBlock1Pattern ← Rope.Cat[vBlock1Pattern, "0"];

vBlock2Pattern ← Rope.Cat[vBlock2Pattern, "0"];

vBlock3Pattern ← Rope.Cat[vBlock3Pattern, "0"];

vBlock4Pattern ← Rope.Cat[vBlock4Pattern, "0"];

vBlock5Pattern ← Rope.Cat[vBlock5Pattern, "0"];

ENDLOOP;

vBlock0Pattern ← Rope.Cat[vBlock0Pattern, "000"];

vBlock1Pattern ← Rope.Cat[vBlock1Pattern, "001"];

vBlock2Pattern ← Rope.Cat[vBlock2Pattern, "010"];

vBlock3Pattern ← Rope.Cat[vBlock3Pattern, "011"];

vBlock4Pattern ← Rope.Cat[vBlock4Pattern, "100"];

vBlock5Pattern ← Rope.Cat[vBlock5Pattern, "101"];

END;

Initialize the real page and block patterns

BEGIN

rPagePattern ← "1"; -- IO bit

FOR i: NAT IN [0..numPageBits-numDevIdBits-1) DO

rPagePattern ← Rope.Cat[rPagePattern, "0"];

ENDLOOP;

rPagePattern ← Rope.Cat[rPagePattern, "1"]; -- 1 bit for DeviceType

DeviceId bits must be X since they are matched outside the array

FOR i: NAT IN [numPageBits-numDevIdBits..numPageBits) DO

rPagePattern ← Rope.Cat[rPagePattern, "X"];

ENDLOOP;

rBlock0Pattern ← rBlock1Pattern ← rBlock2Pattern ← rBlock3Pattern ← rBlock4Pattern ← rBlock5Pattern ← "";

FOR i: NAT IN [0..numBlockBits-3) DO

rBlock0Pattern ← Rope.Cat[rBlock0Pattern, "0"];

rBlock1Pattern ← Rope.Cat[rBlock1Pattern, "0"];

rBlock2Pattern ← Rope.Cat[rBlock2Pattern, "0"];

rBlock3Pattern ← Rope.Cat[rBlock3Pattern, "0"];

rBlock4Pattern ← Rope.Cat[rBlock4Pattern, "0"];

rBlock5Pattern ← Rope.Cat[rBlock5Pattern, "0"];

ENDLOOP;

rBlock0Pattern ← Rope.Cat[rBlock0Pattern, "000"];

rBlock1Pattern ← Rope.Cat[rBlock1Pattern, "001"];

rBlock2Pattern ← Rope.Cat[rBlock2Pattern, "010"];

rBlock3Pattern ← Rope.Cat[rBlock3Pattern, "011"];

rBlock4Pattern ← Rope.Cat[rBlock4Pattern, "100"];

rBlock5Pattern ← Rope.Cat[rBlock5Pattern, "101"];

END;

RETURN[NumBitsPerByte*NumBytesPerWord*NumCyclesPerLine*NumMemLines*NumIOLines*NumFIFOLines];

};

SetCellTypeSpecs: PUBLIC PROC [

SmallCacheSpec: CellTypeSpec ← Schematic,

SCacheHybridSpec: CellTypeSpec ← Schematic,

SCacheSpec: CellTypeSpec ← Schematic,

InnerSpec: CellTypeSpec ← Schematic,

LeftCtlSpec: CellTypeSpec ← Schematic,

RightCtlSpec: CellTypeSpec ← Schematic,

DataPathSpec: CellTypeSpec ← Schematic,

ArraySpec: CellTypeSpec ← Schematic,

OutputSectionSpec: CellTypeSpec ← Schematic,

BCyclePipeSpec: CellTypeSpec ← Schematic,

BWdWtPipeSpec: CellTypeSpec ← Schematic ] ~ {

smallCacheSpec ← SmallCacheSpec;

sCacheHybridSpec ← SCacheHybridSpec;

sCacheSpec ← SCacheSpec;

innerSpec ← InnerSpec;

leftCtlSpec ← LeftCtlSpec;

rightCtlSpec ← RightCtlSpec;

dataPathSpec ← DataPathSpec;

arraySpec ← ArraySpec;

outputSectionSpec ← OutputSectionSpec;

bCyclePipeSpec ← BCyclePipeSpec;

bWdWtPipeSpec ← BWdWtPipeSpec };

PagePatternHi: PUBLIC PROC [pagePattern: ROPE] RETURNS [ROPE] ~ {

RETURN[Rope.Substr[pagePattern, 0, numPageBits+1-numDevIdBits]];

};

PagePatternLo: PUBLIC PROC [pagePattern: ROPE] RETURNS [ROPE] ~ {

RETURN[Rope.Substr[pagePattern, numPageBits+1-numDevIdBits, numDevIdBits]];

};

Log2: PROC [n: INT] RETURNS [log: INT ← 0] ~ {

WHILE n > 1 DO n ← n/2; log ← log+1 ENDLOOP

};

END.