<> <> <> <> <<>> <> <<>> DIRECTORY Core, CoreCreate, Ports; SCLogic: CEDAR DEFINITIONS ~ BEGIN <> CellType : TYPE = Core.CellType; CellTypes: TYPE = LIST OF Core.CellType; Level: TYPE = Ports.Level; LevelSequence: TYPE = Ports.LevelSequence; LevelSequenceRec: TYPE = Ports.LevelSequenceRec; LevelType: TYPE = Ports.LevelType; PA: TYPE = CoreCreate.PA; Port: TYPE = Ports.Port; Properties : TYPE = Core.Properties; ROPE: TYPE = Core.ROPE; Wire: TYPE = Core.Wire; Wires: TYPE = Core.Wires; WR: TYPE = CoreCreate.WR; <> SignalType: TYPE = {Input, Output, InputOutput, Power}; Signals: TYPE = REF SignalsRec; SignalsRec: TYPE = RECORD [ numSignals: NAT _ 0, signals: SEQUENCE size: NAT OF RECORD [ name: ROPE _ NIL, size: NAT _ 0, st: SignalType, l: Level _ X, ls: LevelSequence _ NIL, index: NAT _ Xs ] ]; <> Xs: NAT = LAST[NAT]; NumStackBits, NumPCBits: NAT; <> SCPmCode: PROC [] RETURNS [ct: CellType]; SCOutputSection: PROC [] RETURNS [ct: CellType]; SCArray: PROC [] RETURNS [ct: CellType]; SCBCyclePipe: PROC [] RETURNS [ct: CellType]; SCBlockAssemblyRegister: PROC [] RETURNS [ct: CellType]; SCBWdWtPipe: PROC [] RETURNS [ct: CellType]; <> Declare: PROC [signals: Signals, name: ROPE, l: Level, st: SignalType] RETURNS [ix: NAT]; DeclareS: PROC [signals: Signals, name: ROPE, size: NAT, lc: CARD, st: SignalType] RETURNS [ix: NAT]; Create: PROC [roseClassName: ROPE, signals: Signals] RETURNS [ct: CellType]; XInInputs: PROC [p: Port, s: Signals] RETURNS [BOOL _ FALSE]; OutputsToX: PROC [p: Port, s: Signals]; OutputsToDefault: PROC [p: Port, s: Signals]; CopyInputValues: PROC [s: Signals, p: Port]; CopySignals: PROC [to, from: Signals]; CopyLS: PROC [dest, source: LevelSequence, index: NAT _ 0]; XInLS: PROC [ls: LevelSequence] RETURNS [BOOL _ FALSE]; END.