SCBlockAssemblyRegisterImpl.mesa
Pradeep Sindhu October 6, 1987 6:08:08 pm PDT
Paraminder Sahai September 24, 1987 0:27:17 am PDT
DIRECTORY
Core, CoreClasses, CoreCreate, CoreFlat, Ports, Rosemary, RosemaryUser, SCLogic, SCParms;
SCBlockAssemblyRegisterImpl: CEDAR PROGRAM
IMPORTS CoreClasses, CoreCreate, CoreFlat, Ports, Rosemary, SCParms
EXPORTS SCLogic
~ BEGIN OPEN SCLogic;
Constants and Type Defs
NumBitsPerWord: NAT = SCParms.numBitsPerWord;
NumBitsPerCycle: NAT = SCParms.numBitsPerCycle;
NumWordsPerCycle: NAT = SCParms.numWordsPerCycle;
NumWordsPerLine: NAT = SCParms.numWordsPerLine;
LogNumWordsPerLine: NAT = SCParms.logNumWordsPerLine;
NumCyclesPerLine: NAT = SCParms.numCyclesPerLine;
LogNumCyclesPerLine: NAT = SCParms.logNumCyclesPerLine;
NumBitsPerLine: NAT = SCParms.numBitsPerLine;
InternalState: TYPE = RECORD [
bar: LevelSequence,
en: LevelSequence
];
State: TYPE = REF StateRec;
StateRec: TYPE = RECORD [
bCycleAdrs: LevelSequence,
master: InternalState,
slave: InternalState
];
Signal Defs
CycleIn, BCtlBlkWt5, BCycle0, BCycle1, BlkWtData, Clock: NAT;
Public Procs
SCBlockAssemblyRegister: PUBLIC PROC [] RETURNS [ct: CellType] = {
public: Wire ← CoreCreate.WireList[LIST[CoreCreate.Seq["CycleIn", NumBitsPerCycle],
CoreCreate.Seq["BlkWtData", NumBitsPerLine], "BCtlBlkWt5", "BCycle0", "BCycle1", "Clock"]];
ct ← CoreClasses.CreateUnspecified[public: public];
[] ← Rosemary.BindCellType[cellType: ct, roseClassName: myBlockAssRegName];
[] ← CoreFlat.CellTypeCutLabels[ct, "Logic"];
Ports.InitPorts[ct, ls, none, "CycleIn"];
Ports.InitPorts[ct, l, none, "BCtlBlkWt5", "BCycle0", "BCycle1", "Clock"];
Ports.InitPorts[ct, ls, drive, "BlkWtData"];
};
Internal Procs
Init: Rosemary.InitProc = {
--PROC [cellType: Core.CellType, p: Ports.Port, oldStateAny: REF ANY ← NIL] RETURNS [stateAny: REF ANY ← NIL]--
s: State;
IF oldStateAny=NIL
THEN {
s ← NEW [StateRec];
s.bCycleAdrs ← NEW [LevelSequenceRec[LogNumCyclesPerLine]];
s.master.bar ← NEW [LevelSequenceRec[NumBitsPerLine]];
s.master.en ← NEW [LevelSequenceRec[NumCyclesPerLine]];
s.slave.bar ← NEW [LevelSequenceRec[NumBitsPerLine]];
s.slave.en ← NEW [LevelSequenceRec[NumCyclesPerLine]];
}
ELSE s ← NARROW [oldStateAny, State];
Ports.SetLS[s.bCycleAdrs, X];
Ports.SetLS[s.master.bar, X];
Ports.SetLS[s.master.en, X];
Ports.SetLS[s.slave.bar, X];
Ports.SetLS[s.slave.en, X];
[CycleIn, BCtlBlkWt5, BCycle0, BCycle1, BlkWtData, Clock] ← Ports.PortIndexes[cellType.public, "CycleIn", "BCtlBlkWt5", "BCycle0", "BCycle1", "BlkWtData", "Clock"];
stateAny ← s;
};
Simple: Rosemary.EvalProc = {
s: State ← NARROW[stateAny];
IF NOT clockEval THEN SELECT p[Clock].l FROM
L => {
numEnablesHigh: NAT ← 0;
FOR cycle: NAT IN [0..NumCyclesPerLine) DO
Compute master.en[cycle]
IF p[BCycle0].l=H OR p[BCtlBlkWt5].l=H
THEN s.master.en[cycle] ← L
ELSE {
prevCycle: INT;
FOR i: NAT IN [0..LogNumCyclesPerLine) DO
s.bCycleAdrs[i] ← p[CycleIn].ls[NumBitsPerCycle-NumWordsPerCycle*(LogNumWordsPerLine-i)+1];
ENDLOOP;
prevCycle ← (cycle-1) MOD NumCyclesPerLine;
IF prevCycle<0 THEN prevCycle ← NumCyclesPerLine-1;
IF (p[BCycle1].l=H AND Ports.LSToC[s.bCycleAdrs]=cycle) OR s.slave.en[prevCycle]=H
THEN s.master.en[cycle] ← H
ELSE s.master.en[cycle] ← L
};
Compute master.bar[cycle]
SELECT s.slave.en[cycle] FROM
H => {
IF (numEnablesHigh ← numEnablesHigh+1) > 1 THEN ERROR;
FOR i: NAT IN [0..NumBitsPerWord) DO
s.master.bar[i*NumWordsPerLine+NumWordsPerCycle*cycle] ← p[CycleIn].ls[2*i];
s.master.bar[i*NumWordsPerLine+NumWordsPerCycle*cycle+1] ← p[CycleIn].ls[2*i+1]
ENDLOOP;
};
X => {
FOR i: NAT IN [0..NumBitsPerWord) DO
s.master.bar[i*NumWordsPerLine+NumWordsPerCycle*cycle] ← X;
s.master.bar[i*NumWordsPerLine+NumWordsPerCycle*cycle+1] ← X
ENDLOOP;
};
ENDCASE
ENDLOOP;
};
H => {
Ports.CopyLS[s.master.en, s.slave.en];
Ports.CopyLS[s.master.bar, s.slave.bar];
};
X => {
Ports.SetLS[s.master.en, X];
Ports.SetLS[s.master.bar, X];
Ports.SetLS[s.slave.en, X];
Ports.SetLS[s.slave.bar, X];
};
ENDCASE => ERROR;
Ports.CopyLS[s.slave.bar, p[BlkWtData].ls]
};
myBlockAssRegName: ROPE = Rosemary.Register[roseClassName: "SCBlockAssemblyRegister", init: Init, evalSimple: Simple, scheduleIfClockEval: TRUE];
END.