SICLog.tioga
Copyright © 1988 by Xerox Corporation. All rights reserved.
Richard Bruce, March 17, 1988
Last Edited by: RBruce September 26, 1988 3:38:14 pm PDT.
Scanner Interface Chip for sensing scanner charge and making 8 bit output.
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XEROX
Overview
8/13 Fix Comparator schematic by merging current mirrors to get lichen to work.
Chang interest rectangle in
psdcontstrip, psdcontstripquarter, nwellcontstrip
metal2topolycont has a problem!!!!!!!! check it out
8/14 Cells like psdcontstrip are in different design objects as [3891326] cell [hint: psdcontstrip] I cannot change them once and forall.
Formula for effectively flattening cells. Get rid of all reps including the contact reps inside of psdcontstrip and nwellcontstrip (these are bad because of the nwell surround ???). Take transistors down to elemental sizes.
8/15 Put in latches in Control Logic to prevent gliches on reset. Remove pass gates on latch and shiftregister to prevent backflow.
8/17 Add Pause and RefCtl(1). Change logic for latch and SR ,
Add SRLoad output call PauseStrobe. Add analogtestpulse(ATP) to control logic and put on maunal ouveride and a ATPON pad. Change SRTest to SRTestON.
8.19 CompInit form ADCReset, LatchReset from Reset, RefCtl is TestRefCtl, RefCK
9/21 Eliminate MCEnable,
Add Ref pads on bottom to access split in refhi and reflo
Analog power and ground are now coming in from pads on the side of the chip in the middle of the analog inputs
9/22 Bias current select pads have been put in the middle of the chip sides. Levels on these pads determine the bias current.
9/26 Increase the cycle to 47 clocks