sic.tioga
copyright © 1988 by Xerox Corporation. all rights reserved.
Richard Bruce, August 18, 1988
Last Edited by: RBruce October 17, 1988 11:19:54 am PDT
Louis Monier August 30, 1988 3:30:10 pm PDT
scanner interface chip for sensing scanner charge and making 8 bit output.
confidential xerox corporation
Overview
SIC is a Scanner Interface Chip. It uses 64 A/D converters to sense charge from a scanner, loads the 8-bit values into a shift register, and outputs two 8-bit values per cycle. SIC uses a 11MHz system clock; the sensing, conversion, and transfer define the basic circuit pipeline period, which is 47 cycles. A pause feature allows the circuit to be synchronized on a longer period.
Structure of the circuit
The circuit is composed of a top row of pads, a large block, two rows of standard cells implementing most of the control, and a bottom row of pads.
The central block is made of two symetrical halves. Each one is made of 32 8-bit ADC and a 32-bit long, 8-bit wide shift register.
Pads
The pads description listed below is correct for the chip orintated with the output drivers on the top.
Left Column (top to bottom) 36 Pads
LTAnalogIn
Analog inputs of the ADCs. Even values from 0 to 30. This is the upper left quadrant.
AGnd, AVdd
Ground and power for the left analog block
LBiasCurCtl
Two pads for selecting the bias current. The top pad is the lsb and the bottom is the msb. A BiasCurCtl value of 11 selects the lowest current and a 00 selects the highest. This selection must be done after fabrication since the current value depends on the resistivity of n+ diffusion. The pads are connected to Vdd by a fuse and Gnd by a 100kW resistor so that the lowest bias current is selected before fuses are blown.
LBAnalogIn
Analog inputs of the ADCs. Even values from 32 to 62. This is the lower left quadrant.
Right Cloumn (top to bottom) 36 Pads
RAnalogIn
Analog inputs of the ADCs. Odd values from 1 to 31. This is the upper right quadrant.
AGnd, AVdd
Ground and power for the right analog block
RBiasCurCtl
Two pads for selecting the bias current. The top pad is the lsb and the bottom is the msb. A BiasCurCtl value of 11 selects the lowest current and a 00 selects the highest. This selection must be done after fabrication since the current value depends on the resistivity of n+ diffusion. The pads are connected to Vdd by a fuse and Gnd by a 100kW resistor so that the lowest bias current is selected before fuses are blown.
RAnalogIn
Analog inputs of the ADCs. Odd values from 33 to 63. This is the lower right quadrant.
Top Row (left to right) 39 Pads
PGnd
PGnd or pad ground is used to ground the substrate near the input protection diodes. This separate ground minimizes coupling of the ground noise generated in the digital section.
LAGC[0..2]
Analog Gain Control input for the left analog section. The levels on these pads select the size of the integration capacitor which determines the gain of the input amplifier. Read these levels as a binary number where 0 (the leftmost pad) is the highest order bit. The capacitor value is calculated from the applied levels as C = (binary number +1) x 1.25pF.
TLRefCtl
This pad connects the adjacent two pads to specific internal levels. TLRefCtl is low in normal operation. When high, it connects the internal signals, TLRefHi and TLRefLo to the pads adjacent on the right. The RefHi and RefLo signals are produced separately for a quarter of the chip and monitored at the top and bottom of each side while LVbias0 is generated for half the chip and is measured at the top for each side. During other testing, TLRefCtl is low to prevent the tester from loading these reference levels.
TLRefHi, TLRefLo, LIbiasC
Analog reference voltages. These pads are connected to the respective internal reference levels when LTRefCtl is high. Note LIbiasC is the pad where the bias current for the left half of the chip is monitored. The current is monitored by connecting the pad to ground through a low impeadance current meter.
Digital Vdd, Digital Gnd
Power and ground for the digital logic.
Output[0..7]
The output of the left shift register. The leftmost bit (0) is the most significant bit.
OutVdd
Power for the 16 output buffers.
AnIn
The analog test input is used to test uniformity by applying a fixed amount of charge to each input channel individually. This charge is generated by applying an external voltage step to an internal capacitor. The channel to be tested is selected by applying a low level on the designated input pad. All other input pads must be high. AnIn is disconnected during normal operation by making Test2 low.
OutGnd
Ground for the 16 output buffers.
Output[8..15]
The output of the right shift register. The leftmost bit (8) is the most significant.
Digital Vdd, Digital Gnd
Power and ground for the digital logic.
TRRefCtl
See above for TLRefCtl.
TRRefHi, TRRefLo, RIbias0
See above for TRRefHi, TRRefLo, RIbias0. Note RIbias0 is the pad where the bias current for the right half of the chip is monitored.
RAGC[2..0 ]
Analog Gain Control input for the right analog section. The levels on these pads select the size of the integration capacitor which determines the gain of the input amplifier. Read these levels as a binary number where 0 (the rightmost. pad) is the highest order bit. The capacitor value is calculated from the applied levels as C = (binary number +1) x 1.25pF.
PGnd
PGnd or pad ground is used to ground the substrate near the input protection diodes. This separate ground minimizes coupling of the ground noise generated in the digital section.
Bottom Row (left to right) 48 Pads
Digital Vdd (2 pads)
Power for the digital section.
BLRefCtl
This pad connects the adjacent two pads to specific internal levels. BLRefCtl is low in normal operation. When high, it connects the internal signals, BLRefHi and BLRefLo to the pads adjacent on the right. The RefHi and RefLo signals are produced separately for a quarter of the chip and monitored at the top and bottom of each side. During other testing, BLRefCtl is low to prevent the tester from loading these reference levels.
BLRefHi, BLRefLo
Analog reference voltages. These pads are connected to the respective internal reference levels when BTRefCtl is high.
Pause
Pause is used to freeze the chip operation for times less than 100ms and is synchronized by PauseStrobe. The chip operation freezes one half cycle after the rising clock edge after pause goes high and stays frozen until one half cycle after the rising clock edge after pause goes low.
LTestCtl[0..2] = Test0, Test1, Test2 (from left to right)
Test0 is high for normal operation. When Test0 is low the chip is in test mode.
Test1 is low for normal operation and high for testing linearity with one capacitor per channel.
Test2 is low for normal operation and high for uniformity test.
MTVP
An external test voltage pulse (TVP) can be applied to this pad. The TVP discharges internal capacitors during the pulse duration. Each analog input is attached to a capacitor. This tests gain and offset of the individual channels.
TVPOn
TVPOn must be high to implement external test voltage pulses (TVP). This is used only during testing. TVPOn must be low during normal operation and when using the internal TVP. See the timing diagram for information on the internal TVP duration.
SRInput[0..1]
Shift Register Input are two pins connecting to adjacent columns of the shift register. The left most pad will connect to the odd bits (note the bits are numbered starting with 0). These patterns will appear on shift out after 32 shift register (MSRCK) cycles during shift register test.
SRTestOn
SRTestOn must be high to test the shift register. It then inhibits the normal loading of the shift register. SRTestOn is low during normal operation.
Clock
The chip is designed to work with a single phase 10 MHz clock running at a 50% duty cycle (we'll se how fast it will go later).
Start
Start is used to synchronize the chip and the scanner. The chip begins accepting data (ie TFT gate goes high) two rising clock edges after the falling edge of start.
Digital Vdd
Power for the digital section.
PauseStrobe
Pause strobe provides a pulse to gate the pause signal. The pause signal should be applied on the next clock cycle after the pause strobe.
TFTGate
TFTGate is high when the chip expects to be sensing a photodiode. This pulse is used to switch on the TFT gates connecting the chip input to a bank on sensors.
Digital Gnd
Ground for the digital section.
MReset1
Reset 1 resets the input integrator. (It shorts the integration capacitor.)
MReset2
When Reset 2 is high the array is connected to the input integrator.
MStore1
Transfers charge from the integrator to the amplifier.
MStore2
Shorts the switch capacitor amplifier which then acts as a Vrefhi buffer.
MRefCtl
A clock to switch the bias section.
MCompEReset
Shorts input to output of comparator first stage during charge transfer from the second amplifier to the ADC capacitor array for offset cancellation.
MCompInit (former MADCReset???)
This helps the comparator recover quickly form overdrive.
MBitSel
MBitSel is used to select a paticular bit for analysis. The bits must be selected in desending order starting from bit 0 (the left most pad). A bit is tested when M BitSel is high.
MSRLoad
Manual Shift Register Load (MRSLoad) causes the bits latched after the AtoD conversion to be transfered to the shift register. The shift register clock (MSRCK) must cycle once while MRSLoad is high for the transfer to be completed.
MSRCK
The shift register clock (SRCK) shifts data out the shift register. Words 0 and 1 are exposed during load and after 31 SRCK pulses, words 62 and 63 reach the output.
MSet1
Set1 updates the local Vreflo buffer.
MLatchReset
Used to clear the ADC latches and to connect the ADC capacitor array to Vreflo while Vrefhi buffer is amplifing the signal.
Digital Vdd, Digital Gnd
Power supplies for the digital logic.
RTestCtl[0..2] = Test0, Test1, Test2
Similar to left version.
BRRefCtl
This pad connects the adjacent two pads to specific internal levels. BRRefCtl is low in normal operation. When high, it connects the internal signals, BRRefHi and BRRefLo to the pads adjacent on the right. The RefHi and RefLo signals are produced separately for a quarter of the chip and monitored at the top and bottom of each side. During other testing, BRRefCtl is low to prevent the tester from loading these reference levels.
BRRefHi, BRRefLo
Analog reference voltages. These pads are connected to the respective internal reference levels when BTRefCtl is high.
Digital Ground
Ground for the digital section.
Functions
Normal operation
Hold low all manual override signals (Mxxx), SRTestOn, Pulse, and Start.
Testing Shift Register
SRTestOn is held high to inhibit the shift register load. Words 31 and 63 are connected to SRInputs (see pad description).
Manual override
All controls issued by the standard cell block can be overriden externally by the Mxxx signals. These are normally held low, and a weak pull-down on each such input garantees this low value if the input is unconnected.
After pulsing Start, each Mxxx input must be kept low. If a Mxxx goes high, it will permanently override the internally generatedcointrol signal until a Start pulse resets the operation.
Digital - Analog Interface
As previously mentioned, the chip is organized with 32 input AtoD slices stacked on each side of the chip, a digital control section and shift register in the middle of the chip, and a control section at the bottom. The control logic at the bottom sends most of the control signals vetically through all the AtoD slices. The control section in the middle passes bit select signals horizontally to each AtoD slice individually. Each analog slice in turn passes the AtoD comparitor output to the center logic where it is latched and passed to an output shift register.

To evaluate a specific bit, the corresponding bit select signal is passed to the AtoD slice. At the end of the bit evaluation period, the AtoD comparitor output is latched in the center control section. This latched value replaces the corresponding bit select for the remainder of the cycle and is passed to the shift register at the end.
Power considerations
For safety sake, the power buses should be oversized in the prototype. A bus of 100m match the width of the power pad, and is a good choice.
Digital section
The sum of gate area in one bit ADC latch+shift register is about 700m2, or 0.85pF. There are 32 such cells sharing the same power lines, so assuming 100ns cycle time, the upper bound on the average current is 0.85e-12*5e7*32=1.4mA. The size of the power line is no issue! We use at least 4m metal1 lines for power, and power is supplied form both sides: the resistance for a 4mm long 4m wide line is about 45W, or a dV < 32mV.
The entire digital section draws less than 15mA from each side.
Standard cells section
There are 238 cells. Assuming they are all inverters switching simultaneously, we find a gate capacitance of 40pF, and an average current of 20mA. This power could be supplied mostly from the bottom.
Analog section
Analog power: 240 mA total through dedicated pads. That's 60mA per pad pair.
Digital power: negligible.
Output buffers on top pads
Assume the output drivers drive 50W each 100ns (this is an overestimate both in load and in time), then each driver will need 2.5ma or 20ma for each bank. This corresponds to 20mm wide m2 buses with a 3W resistance worst case.
Internal Buses
AnCtrl
nCompEReset, nADCReset, nSet1, nStore2, nStore1, nReset1, nReset2, Reset2, Reset1, Store1, Store2, Set1, ADCReset, CompEReset