Dragon System Overview
January 1989
1
MultiProcessor Architectures
Dragon System Overview
I Introduction
II DynaBus : a VLSI Bus
III Dragon VLSI Chip Set
IV Micro-Packaging
V System Architectures
VI Sun Cooperation
VII
Conclusions
Motivations
Foundations for building architectures for a wide range of document processing machines
· controllers : Printer, Network, Scanners...
· servers : Data base servers, Printers, Gateway
· workstations : mid, high & very high end
=> high data bandwidth, high data processing
For this variety, for incrementality, for cost...
=> Multiprocessor Architecture
· Follows a first generation of shared memory
multiprocessor on conventional Bus.
Currently implemented in a Xerox product.
· new generation using more advanced concepts
in the Bus & new technology : VLSI, packaging
Design Space
What kind of multiprocessor ?
loosely coupled / thigtly coupled / Highly parallel ?
· Moderate number (<100) of nearly state of the art
microprocessors the more thigtly coupled possible
=> more MIPS/$, more applications
What kind of programming Model ?
Message Passing / Shared memory ?
· We'll choose Shared memory because more flexibility
What kind of communication ?
Busses, Cross-bar, Hypercube ?
· For first level connection Busses are simpler
& more flexibility
All solutions are difficult to implement until the technology exits for an economic implementation of the Memory System.
The Dragon Technology solves this problem
Basic Technology
· DynaBus VLSI BUS, MultiProc, High Bandwidth
· VLSI Chip Set
[Artwork node; type 'Artwork on' to command tool]
· Micro-Packaging
APPLICATIONS
Applications & Markets
· High end parallel computer : SERVER
file server, cycle server, data base server
· High end printer servers
· DeskTop multiprocessor
High end graphic workstation
· Add-in boards in standards platform
· Industrial control
· OEM multiprocessor
· Chip Set & Packaging
II. The DynaBus : a VLSI Bus
New generation of Bus for VLSI
· Primarily an "on board" Bus for connecting VLSI
· Implement Cache coherency for Multiprocessor
· High Bandwidth
Primarily Characteristics
· Packet switched for very high speed & flexibility
=> dissociation between data transport time
& memory access time => scalability
· Versatility in configurations
Implementation
· Mathematical model and proof of coherence
· Bridges with industrial standards busses
· Multilevel Cache support
· Extension to non busses communication
· Debug Bus for initialization and debugging
· Minimun number of wires for 64 bits Data path
· Bandwidth from 200 to more than 700 MByte/sec
DynaBus Configurations
Mono-Board Computer
[Artwork node; type 'Artwork on' to command tool]
Multi-Board Computer
[Artwork node; type 'Artwork on' to command tool]
Multi-Board & Multi-Module Computer
Multi DynaBus
VLSI Interface
VLSI functions = previous Board functions
VLSI interface = Connector
=> The DynaBus define a standard VLSI interface, like Backpanel Busses define Board interface
LOGIC OF THE BUS
Minimal number of wires for 64 bits data path. All commands are coded on 64 bits
Performances
Tcycle Raw BdWidth Usable BdWidth(*8/11)
25 ns 320 MB/sec 232 MB/sec
10 ns 800 MB/sec 581 MB/sec
DBus
Serial Path. Used for initialization & debugging
Bus Transactions
Only 13 transactions for all operations
Read Block RA,VRA RA,D0-D7
Write Block RA,D0-D7 RA,X
Flush Block RA,D0-D7 RA,X
Write Single RA,D RA,D
CondWS RA,D0-D7 RA,D0-D7
CtlRead IOA,X IOA,D
CtlWrite IOA,D IOA,X
CtlReadBlock RA,VRA RA,D0-D7
CtlWriteBlock RA,D0-D7 RA,X
Interrupt IOA,D0-D7 IOA,X
Map VA,X RA,X
DeMap RA,X RA,X
KillBlock RA,X RA,X
III. Dragon VLSI Chip Set
Only Seven Chips for all the family
· Arbiter : distributed arbiter
· Memory Controller : High performance with ECC
· Cache : connected to the processor
· IOB : Input-Output Bridge for Industrial Busses
· Display/Printer Chip : Programmable format
· Map Cache : for virtual memory
· BIC : Bus interface Chip
IV. MicroPackaging
DynaBus take account micropackaging evolution flexible pipelining, good electrical interface.
For short cycles, lines must act as perfect transmission lines
[Artwork node; type 'Artwork on' to command tool]
Using SMD and BiCMOS interface very good characteristics
[Artwork node; type 'Artwork on' to command tool]
Next step is using MultiChip Hybrid module
[Artwork node; type 'Artwork on' to command tool]
V. System Architectures
Monoboard system
Monoboard system with Module
(100 Mips)
MultiBoard Multiple Bus system
(>400 Mips)
MultiBoard system with Modules
VI SUN Cooperation
Common colocated Xerox-Sun Team
· 10 Xerox researchers
· 30 Sun engineers
Joint development to
· Push the DynaBus as an open Standard
· Design of the VLSI Chip set for this standard
· Develop a symetric MP UNIX Kernel compatible
· Build a High performance Multiprocessor Server
Dragon architecture & DynaBus are still Xerox proprietary. Xerox only has the right to licence the technology.
Benefit to PARC & Xerox :
· royalties
· price reduction on Sparc based machine
· master an advance Hardware architecture
compatible with futur software platform
VII Conclusions
High Performance System Building Blocks
· VLSI Bus => SPEED & PERFORMANCE
High quality & Robust multiprocessor Bus
· VLSI Chip Set => COST & SIMPLICITY
only seven LSI for all the family
Architecture for a Wide range of applications
Unique Open architecture to industrial standards => EASY INTEGRATION
· Microprocessor independant
· Bridge with existing standard Busses
Good candidate for BUS standardization
Cooperation with Sun will increase Chips market & will allow software compatibility