The research phase of the Dragon project is now ending. This year has been devoted to the transfer of the project. After main technical evaluations of the Dragon technology, Sun microsystem has been very excited in a joint development program for building a complete multiprocessor product line. Sun had actually a nice program related to future microprocessor development, but was really weak in term of multiprocessor architecture. The Dragon technology appeared to be the ideal complement of their strategy. For Xerox the advantage to be part of such cooperation is that we will be able to master a complete architecture compatible with future Sun platforms and compatible with future Unix software. Last September a cooperation agreement has been signed specifying this cooperation. An another interesting area of activity started this year around the study of special purpose Chips for speeding up some document processing operations. Last area is the Softcard which is working and had been demonstrated as an impressive printer controller.
VLSI Studies
The main technical accomplishment this year has been to send for processing all chips of the Dragon chip set. Some of them have been tested and worked as expected. At chip level some new orientation focused on special purpose operators has been started, and some new document processing chips have been designed.
Bus Interface Chip Another version of BIC was submitted in July, and more copies were received in November. The circuit was used on a bus prototype and functionned up to 80 MHz.[L. Monier, R. Bruce]
Clock generator Chip The clock generator chip has been designed, fabricated, and tested. The circuit uses a delay locking scheme with a very novel reset circuit which extends the useable frequency range to beyond the limitations of the delay line itself. An example of this chip has been made and shows operation with less than 1 nsec skew at 40 Mhz clock rates. There is reason to believe that this circuit should work to much higher clock speeds, and further investigation must be done. It may be as simple as taking a sample from a different wafer.[Ed. Richley, L. Monier, B. Gunning]
Arbiter Chip The first implementation of the Dynabus Arbiter was tested on the new PC based tester. The design proved to be 100% functional with a yield of 2/3 (4 of 6 chips). [D. Curry, Ed McCreight]
Cache Chip The Cache chip design has been complete and sent in August for fabrication. A large work of logic design, layout assembly and design verification by simulation has been accomplished. This chip is by far the most complex piece of the project and we organized the work quite well for succeeding to finish it. A complete documentation has been written. The chip came back in november and has not yet been tested because tester problems.[P. Sindhu, D. Curry, JM Frailong] (6 lines)
New Cache Design A new architecture and novel BiCMOS circuits have been designed which demonstrate the feasibility of building a 32 kByte, 20 ns access time, fully associative cache with a die size of 13mm X 8mm. This work involving extensive circuit simulation and layout of key cells to determine die size, has been done in cooperation with National Semiconductor using their BiCMOS III process. Topics in the study included the topological construction, critical path analysis, and manufacturability. Much of National's existing memory technology is leveraged in this design to help expedite the work and permit focusing on the novel features of the cache. [M. Ross, P. Sindhu]
Memory Controller Chip Some initial testing of the fabricated Memory Controller parts was performed. Of the five packaged parts tested, none were fully functional, although some functions, such are refresh, were operating. A complete specification of the Memory Controller chip was written. [J. Gasbarro]
Input-Output Bridge Chip 6 packaged IOBridge chips were tested. None of them was found to be functional: 2 chips had power shorts (>2A supply current), 3 failed at the same test vector, the last one failed slightly earlier. More tests need to be done on unpackaged parts to determine fault reasons. [JM. Frailong]
Display/Printer Chip The design of the display controller chip, including an enhancement to handle printing requirements, was completed. It's now fabricated but not tested, because the tester can't yet test unpackaged parts and management doesn't want to package complex parts without testing them first. [J. Hoel]
Map-Cache Chip The Map Cache was sent to fabrication in July and came back in November. The testing will proceed after higher-priority circuits have cleared the testing pipeline.[L. Monier]
Arithmetic Frequency Synthesizer Chip A joint patent was granted on the design of the Arithmetic Frequency Synthesizer, a VLSI device to be used in scan linearity, motor hunt and facet error correction in the Firebird laser printer. The first CMos implementation was tested at the beginning of the year by Doug Curry and proved to be 100% functional. [Doug Curry, Don Curry]
Scanner inteface Chip Together with Alan Lewis, Richard Bruce, and a consultant, I designed and implemented an interface circuit for an amorphous silicon scanner bar. The circuit is an ambitious CMOS design; it comprises 64 8-bit A/D converters and some digital logic. The circuit took about one man-year to design with the CSL CAD tools. It was sent to fabrication in October.[L. Monier, A. Lewis, R. Bruce]
Reed Solomon Error Correction Code Decoder Chip Finishing off previous work, a Reed Solomon Error Correction Code Decoder capable of automatic correction of 8 random byte errors in 255 byte codewords was designed in CMos. Various aspects of the design were submitted as an invention proposal. [Don Curry]
High Speed Bus Studies & Micro-packaging
Drivers & receivers study An analysis of several different driver and receiver circuits has led to a proposed high performance design. It has roughly one half the power dissiation on the VLSI and one fourth the system power of the previous design. Validation by the VLSI vendor is progressing.[B. Gunning, J. Hoel]
Micro-packaging The multichip process technology has been transfered to large area (5"x12") glass plates without loss of yield. Ultrasonic drilling has been identified as the most likely process for drilling holes in the glass for heatsinking (necessary for high performance applications), and the capability is being established in EIL.[R. Bruce]
High Speed Bus Prototype The hybrid package fast bus test fixture has successfully operated at 80 Mhz clock rates. This system tests communication betwen backplane coupler hybrids over a 64 bit bus. The test fixture downloads backplane coupler hybrids from a PC via the DBus, adjusts clock skews, and runs the bus for a specified number of clock cycles. Up to five hybrid packages can be tested on a common bus at one time [E. Richley, B. Gunning, M. Overton, R. Bruce]
System Architecture
Dragon system simulation A complete system simulation containing all the Chips connected together has been made. It allowed to find many errors in almost all the chips before sending them for processing. This simulation has been very usefull in particular for testing the implementation of the Bus protocol in the Cache. [J. Gastinel]
Multi-Sparc Dragon Prototype The Multi-Sparc Dragon Prototype machine is a test vehicule that will be used to debug and prove the Dragon chipset. A total of 5 PC Boards have been designed for it and 4 of them are already built. [JC Cuenod, J. Gastinel, F. Vest]
SoftCard
The SPARC Softcard is a single board addon to the 6085 which provides SUN 4/260 computing power for 6085 applications. The board has a SUN SPARC processor, 16 megabytes of memory and external I/O ports for a display, high-end IOTs and Versatec printers. Execution of currently existing Cedar code is made possible by the portable Mesa/Cedar compiler and by the Portable Common Runtime (PCR) system. A prototype of the Softcard is working and had been demonstrated as a printer controler. Another potential application is workstation upgrade for the 6085.[JC Cuenod]
Documentation of the Dragon System
Documentation was written to describe the seven computer chips that implement the DynaBus architecture. This documentation included datasheets for the arbiter, the clock generator, the display controller/printer, the IOBridge, the map cache, the memory controller, and the processor cache. In addition, a detailed, logical specification of the DynaBus was completed. All of this documentation (over 250 pages) was distributed as preparatory material for a day-long design review of the SunDragon Project held for Sun Management at the Holiday Inn in November, 1988.[L. Bland]