Jean Gastinel July 22, 1988 9:37:40 am PDT
Xerox Palo Alto Research Center
3333 Coyote Hill Road
Palo Alto, California 94304
(415) 494-4429
Dear Dhuval,
Here is the proposed schedule for the presentation of the Dragon technology.
Feel free to suggest some changes.
Sincerely,
Jean
First Day : System Architecture
9:00-10:30 Introduction & Global architecture: J. Gastinel
10:00-12:30 Bus & Data Consistency protocol: P. Sindhu
1:30-3:00 Input-Output Architecture: JM Frailong
Second Day : Chips
9:00-10:30 Memory Controller Chip : Jim Gasbarro
10:30-12:30 Cache Chip: P. Sindhu, M. Ross
1:30-3:00 Map Cache Chip: L. Monier
Third Day : Chips & Analog design
9:00-10:30 IOBridge Chip : JM Frailong
10:30-12:30 Display/Printer Chip : J. Hoel
1:30-2:30 Arbiter Chip : D. Curry
2:30-4:00 Clock generator Chip, BIC chip & Electrical Designs
B. Gunning, E. Richley, R. Bruce