Create:
PROC
RETURNS [ct: CellType] = {
IsCmd:
PROC [cmd: Cmd]
RETURNS [expr: Boole.Expression] = {
expr ← BooleCore.EqualInt[Command, cmd.ORD];
};
fsa: StateMachine;
Command0: Wire ← CoreOps.CreateWire[name: "Command0"];
Command1: Wire ← CoreOps.CreateWire[name: "Command1"];
Command2: Wire ← CoreOps.CreateWire[name: "Command2"];
Command3: Wire ← CoreOps.CreateWire[name: "Command3"];
Command4: Wire ← CoreOps.CreateWire[name: "Command4"];
Command: Wire ← CoreOps.CreateWire[LIST[Command0, Command1, Command2, Command3, Command4]];
DataAvailable: Wire ← CoreOps.CreateWire[name: "DataAvailable"];
DelayDone: Wire ← CoreOps.CreateWire[name: "DelayDone"];
TwoReqPending: Wire ← CoreOps.CreateWire[name: "TwoReqPending"];
RefreshReq: Wire ← CoreOps.CreateWire[name: "RefreshReq"];
Post2Cycle: Wire ← CoreOps.CreateWire[name: "Post2Cycle"];
PostCWS: Wire ← CoreOps.CreateWire[name: "PostCWS"];
PostNeedS: Wire ← CoreOps.CreateWire[name: "PostNeedS"];
PostNeedO: Wire ← CoreOps.CreateWire[name: "PostNeedO"];
PostReq: Wire ← CoreOps.CreateWire[name: "PostReq"];
StartA: Wire ← CoreOps.CreateWire[name: "StartA"];
Read: Wire ← CoreOps.CreateWire[name: "Read"];
Write: Wire ← CoreOps.CreateWire[name: "Write"];
Refresh: Wire ← CoreOps.CreateWire[name: "Refresh"];
Precharge: Wire ← CoreOps.CreateWire[name: "Precharge"];
WriteBufWrAdd0: Wire ← CoreOps.CreateWire[name: "WriteBufWrAdd0"];
WriteBufWrAdd1: Wire ← CoreOps.CreateWire[name: "WriteBufWrAdd1"];
WriteBufWrEn: Wire ← CoreOps.CreateWire[name: "WriteBufWrEn"];
EnbCAdd: Wire ← CoreOps.CreateWire[name: "EnbCAdd"];
ReplyBufWrAdd: Wire ← CoreOps.CreateWire[name: "ReplyBufWrAdd"];
ReplyBufWrEn: Wire ← CoreOps.CreateWire[name: "ReplyBufWrEn"];
SwWPort: Wire ← CoreOps.CreateWire[name: "SwWPort"];
Unload: Wire ← CoreOps.CreateWire[name: "Unload"];
SelIORdData: Wire ← CoreOps.CreateWire[name: "SelIORdData"];
WrCtlReg: Wire ← CoreOps.CreateWire[name: "WrCtlReg"];
CmdIdle: Wire ← CoreOps.CreateWire[name: "CmdIdle"];
public: Wire ← WireList[
LIST["Vdd", "Gnd", "Clock", "Reset",
Command0, Command1, Command2, Command3, Command4, DataAvailable, DelayDone, TwoReqPending, RefreshReq,
Post2Cycle, PostCWS, PostNeedS, PostNeedO, PostReq, StartA, Read, Write, Refresh, Precharge, WriteBufWrAdd0, WriteBufWrAdd1, WriteBufWrEn, EnbCAdd, ReplyBufWrAdd, ReplyBufWrEn, SwWPort, Unload, SelIORdData, WrCtlReg, CmdIdle]];
states: LIST OF ATOM ← LIST[$Idle, $Decode];
states ← StateSeq[states, "RefA", 3];
states ← StateSeq[states, "RefB", 4];
states ← StateSeq[states, "RB", 8];
states ← StateSeq[states, "WB", 6];
states ← StateSeq[states, "WS", 2];
states ← StateSeq[states, "IOR", 2];
states ← StateSeq[states, "IOW", 2];
states ← StateSeq[states, "CWS", 2];
states ← StateSeq[states, "BD", 2];
fsa ← NewMachine[states];
Mealy[fsa, $Idle,
LIST[EnbCAdd, Unload, CmdIdle],
LIST [
[$Idle, And[Not[DataAvailable], Not[RefreshReq]]],
[$Decode, And[DataAvailable, Not[RefreshReq]]],
[$RefA0, RefreshReq]
]];
Mealy[fsa, $RefA0, LIST[StartA, Refresh], LIST[[$RefA1, true]]];
Mealy[fsa, $RefA1, LIST[Refresh], LIST[[$RefA1, Not[DelayDone]], [$RefA2, DelayDone]]];
Mealy[fsa, $RefA2, LIST[Precharge], LIST[[$Idle, true]]];
Mealy[fsa, $RefB0, LIST[StartA, Refresh], LIST[[$RefB1, true]]];
Mealy[fsa, $RefB1, LIST[Refresh], LIST[[$RefB1, Not[DelayDone]], [$RefB2, DelayDone]]];
Mealy[fsa, $RefB2, LIST[Precharge], LIST[[$RefB3, true]]];
Mealy[fsa, $RefB3, NIL, LIST[[$Decode, true]]];
Mealy[fsa, $Decode,
NIL,
LIST [
[$Decode, Not[DelayDone]],
[$Decode, And[DelayDone, TwoReqPending, Not[RefreshReq]]],
[$RefB0, And[DelayDone, TwoReqPending, RefreshReq]],
[$RB0, And[IsCmd[RBRqst], DelayDone, Not[TwoReqPending]]],
[$WB0, And[Or[IsCmd[WBRqst], IsCmd[FBRqst]], DelayDone, Not[TwoReqPending]]],
[$WS0, And[IsCmd[WSRqst], DelayDone, Not[TwoReqPending]]],
[$IOR0, And[IsCmd[IORRqst], DelayDone, Not[TwoReqPending]]],
[$IOW0, And[IsCmd[IOWRqst], DelayDone, Not[TwoReqPending]]],
[$CWS0, And[IsCmd[CWSRqst], DelayDone, Not[TwoReqPending]]],
[$BD0, And[Or[IsCmd[BIOWRqst], IsCmd[DeMapRqst]], DelayDone, Not[TwoReqPending]]]
]];
Mealy[fsa, $RB0, LIST[StartA, Read, ReplyBufWrEn], LIST[[$RB1, true]]];
Mealy[fsa, $RB1, NIL, LIST[[$RB1, Not[DelayDone]], [$RB2, DelayDone]]];
Mealy[fsa, $RB1, NIL, LIST[[$RB1, Not[DelayDone]]]];
Mealy[fsa, $RB2, LIST[PostReq, PostNeedO, PostNeedS], LIST[[$RB3, true]]];
Mealy[fsa, $RB3, NIL, LIST[[$RB4, true]]];
Mealy[fsa, $RB4, NIL, LIST[[$RB5, true]]];
Mealy[fsa, $RB5, NIL, LIST[[$RB6, true]]];
Mealy[fsa, $RB6, NIL, LIST[[$RB7, true]]];
Mealy[fsa, $RB7, LIST[SwWPort, Precharge], LIST[[$Idle, true]]];
Mealy[fsa, $WB0, LIST[WriteBufWrEn, PostReq, Post2Cycle, Unload, ReplyBufWrEn], LIST[[$WB1, true]]];
Mealy[fsa, $WB1, LIST[WriteBufWrAdd1, WriteBufWrEn, Unload, ReplyBufWrAdd, ReplyBufWrEn, SwWPort], LIST[[$WB2, true]]];
Mealy[fsa, $WB2, LIST[WriteBufWrAdd0, WriteBufWrEn, Unload], LIST[[$WB3, true]]];
Mealy[fsa, $WB3, LIST[WriteBufWrAdd0, WriteBufWrAdd1, WriteBufWrEn, Unload, StartA, Write], LIST[[$WB4, true]]];
Mealy[fsa, $WB4, LIST[Write], LIST[[$WB4, Not[DelayDone]], [$WB5, DelayDone]]];
Mealy[fsa, $WB5, LIST[Precharge], LIST[[$Idle, true]]];
Mealy[fsa, $WS0, LIST[EnbCAdd, Unload, PostReq, Post2Cycle, PostNeedS, ReplyBufWrEn], LIST[[$WS1, true]]];
Mealy[fsa, $WS1, LIST[ReplyBufWrAdd, ReplyBufWrEn, SwWPort], LIST[[$Idle, true]]];
Mealy[fsa, $IOR0, LIST[PostReq, Post2Cycle, ReplyBufWrEn], LIST[[$IOR1, true]]];
Mealy[fsa, $IOR1, LIST[ReplyBufWrAdd, ReplyBufWrEn, SelIORdData, SwWPort], LIST[[$Idle, true]]];
Mealy[fsa, $IOW0, LIST[Unload, PostReq, Post2Cycle, ReplyBufWrEn, WrCtlReg], LIST[[$IOW1, true]]];
Mealy[fsa, $IOW1, LIST[ReplyBufWrAdd, ReplyBufWrEn, SwWPort], LIST[[$Idle, true]]];
Mealy[fsa, $CWS0, LIST[EnbCAdd, Unload, PostReq, PostCWS, PostNeedS, ReplyBufWrEn], LIST[[$CWS1, true]]];
Mealy[fsa, $CWS1, LIST[ReplyBufWrAdd, ReplyBufWrEn, SwWPort], LIST[[$Idle, true]]];
Mealy[fsa, $BD0, LIST[EnbCAdd, Unload, PostReq, Post2Cycle, ReplyBufWrEn], LIST[[$BD1, true]]];
Mealy[fsa, $BD1, LIST[ReplyBufWrAdd, ReplyBufWrEn, SwWPort], LIST[[$Idle, true]]];
fsa.initialState ← FindState[fsa, $Idle];
ct ← StateMachineCell[public, fsa];
};