1 1 X X X X X X X X X X X X XX | X X X X X X XX X X X -- Initial state
1 1 1 1 1 1 X X X X X X X X XX | X X X X X X XX X X X -- Reset
1 1 1 1 1 1 X X X X X X X X XX | X X X X X X XX X X X -- Reset
1 1 1 1 1 1 X X X X X X X X XX | X X X X X X XX X X X -- Reset
1 1 1 1 1 1 X X X X X X X X XX | X X X X X X XX X X X -- Reset
1 1 1 1 1 1 X X X X X X X X XX | X X X X X X XX X X X -- Reset
1 1 1 1 1 1 X X X X X X X X XX | X X X X X X XX X X X -- Reset
1 1 1 1 1 1 X X X X X X X X XX | X X X X X X XX X X X -- Reset
1 1 1 1 1 1 X X X X X X X X XX | X X X X X X XX X X X -- Reset
1 1 1 1 1 1 X X X X X X X X XX | X X X X X X XX X X X -- Reset
1 1 1 1 1 1 X X X X X X X X XX | X X X X X X XX X X X -- Reset
0 1 1 1 1 1 X X X X X X X X XX | 0 0 0 0 0 X XX 0 0 0 -- Check results
0 1 1 1 1 1 X X X X X X X X XX | 0 0 0 0 0 X XX 0 0 0 -- Check results
0 1 1 1 1 1 X X X X X X X X XX | 0 0 0 0 0 X XX 0 0 0 -- Check results, Hard reset removed
0 1 0 1 1 1 1 0 0 0 0 X X 0 XX | 1 0 0 0 0 3 98 0 0 0 -- Initiate read cycle
0 1 0 1 1 1 1 0 0 0 0 X X 0 XX | 1 0 0 0 0 3 98 0 0 0 -- pass 1st sync
0 1 0 1 1 1 1 0 0 0 0 X X 0 XX | 1 0 0 0 0 3 98 0 0 0 -- pass 2nd sync
0 1 0 1 1 1 1 0 0 0 0 X X 0 XX | 0 0 0 0 0 3 98 0 0 0 -- Done (well, looks like)
0 1 1 1 1 1 1 0 0 0 0 X X 0 XX | 0 0 0 0 0 3 98 0 0 0 -- Idle
0 1 0 1 1 1 0 1 0 1 0 X X 0 XX | 1 0 0 0 0 2 XX 0 0 0 -- Initiate read cycle
0 1 0 1 1 1 0 1 0 1 0 X X 0 XX | 1 0 0 0 0 2 XX 0 0 0 -- pass 1st sync
0 1 0 1 1 1 0 1 0 1 0 X X 0 XX | 1 0 0 0 0 2 XX 0 0 0 -- pass 2nd sync
0 1 0 1 1 1 0 1 0 1 0 X X 0 XX | 1 0 0 0 0 2 XX 0 0 0 -- EndOfCycle
0 1 0 1 1 1 0 1 0 1 0 X X 0 XX | 0 0 0 0 0 2 XX 0 0 0 -- Done
0 1 1 1 1 1 0 1 0 1 0 X X 0 XX | 0 0 0 0 0 2 XX 0 0 0 -- Idle
0 0 1 1 1 1 0 1 0 1 0 X X 0 XX | 0 0 0 0 0 2 XX 0 0 0 -- Remove Reset
0 0 1 1 1 1 0 1 0 1 0 X X 0 XX | 0 0 0 0 0 2 XX 0 0 0 -- Remove Reset
0 0 1 1 1 1 0 1 0 1 0 X X 0 XX | 0 0 0 0 0 2 XX 0 0 0 -- Remove Reset
0 0 1 1 1 1 X X X 0 0 X X X XX | 0 0 0 0 0 3 XX 0 0 0 -- lo word
0 0 1 1 1 1 X X X 0 1 X X X XX | 0 0 0 0 0 1 XX 0 0 0 -- lo-byte of lo-word (LSB)
0 0 1 1 1 1 X X X 1 0 X X X XX | 0 0 0 0 0 2 XX 0 0 0 -- hi byte of lo word
0 0 1 1 1 1 X X X 1 1 X X X XX | 0 0 0 0 0 X XX 0 0 0 -- *** forbidden ***
0 0 1 1 1 1 X X X 2 0 X X X XX | 0 0 0 0 0 C XX 0 0 0 -- hi word
0 0 1 1 1 1 X X X 2 1 X X X XX | 0 0 0 0 0 4 XX 0 0 0 -- lo-byte of hi-word
0 0 1 1 1 1 X X X 3 0 0 0 X XX | 0 0 0 0 0 8 XX 0 0 0 -- hi-byte of hi-word (MSB)
0 0 1 1 1 1 X X X 3 1 X X X XX | 0 0 0 0 0 X XX 0 0 0 -- *** forbidden ***
0 0 0 1 1 1 1 0 0 0 0 X X 0 XX | 1 0 0 0 0 3 98 0 0 0 -- Initiate read cycle
0 0 0 1 1 1 1 0 0 0 0 X X 0 XX | 1 0 0 0 0 3 98 0 0 0 -- pass 1st sync
0 0 0 1 1 1 1 0 0 0 0 X X 0 XX | 1 0 0 0 0 3 98 0 0 0 -- pass 2nd sync
0 0 0 1 1 1 1 0 0 0 0 X X 0 XX | 1 1 0 0 0 3 98 0 1 1 -- PhA1
0 0 0 1 1 1 1 0 0 0 0 X X 0 XX | 1 1 0 0 0 3 98 0 1 1 -- PhA2
0 0 0 1 1 1 1 0 0 0 0 X X 0 XX | 1 0 1 0 0 3 98 0 0 0 -- PhB1
0 0 0 1 1 1 1 0 0 0 0 0 0 0 XX | 1 0 1 0 0 3 00 1 0 0 -- PhB2
0 0 0 1 1 1 1 0 0 0 0 X X 0 XX | 1 0 0 0 0 3 00 0 0 0 -- PhB3
0 0 0 1 1 1 1 0 0 0 0 X X 0 XX | 0 0 0 0 0 3 98 0 0 0 -- Done
0 0 1 1 1 1 1 0 0 0 0 X X 0 XX | 0 0 0 0 0 3 98 0 0 0 -- Idle
0 0 1 0 1 1 1 0 0 2 1 X X 0 XX | 1 0 0 0 0 4 A1 0 0 0 -- Initiate write cycle
0 0 1 0 1 1 1 0 0 2 1 X X 0 XX | 1 0 0 0 0 4 A1 0 0 0 -- pass 1st sync
0 0 1 0 1 1 1 0 0 2 1 X X 0 XX | 1 0 0 0 0 4 A1 0 0 0 -- pass 2nd sync
0 0 1 0 1 1 1 0 0 2 1 X X 0 XX | 1 1 0 0 0 4 A1 0 1 1 -- PhA1
0 0 1 0 1 1 1 0 0 2 1 X X 0 XX | 1 1 0 0 0 4 A1 0 1 1 -- PhA2
0 0 1 0 1 1 1 0 0 2 1 X X 0 XX | 1 0 1 0 0 4 A1 0 0 1 -- PhB1
0 0 1 0 1 1 1 0 0 2 1 1 0 0 XX | 1 0 1 0 0 4 00 0 0 1 -- PhB2, reject
0 0 1 0 1 1 1 0 0 2 1 X X 0 XX | 1 0 0 0 0 4 00 0 0 0 -- PhB3
0 0 1 0 1 1 1 0 0 2 1 X X 0 XX | 1 1 0 0 0 4 00 0 1 1 -- PhA1
0 0 1 0 1 1 1 0 0 2 1 X X 0 XX | 1 1 0 0 0 4 00 0 1 1 -- PhA2
0 0 1 0 1 1 1 0 0 2 1 X X 0 XX | 1 0 1 0 0 4 00 0 0 1 -- PhB1
0 0 1 0 1 1 1 0 0 2 1 0 0 0 XX | 1 0 1 0 0 4 00 0 0 1 -- PhB2
0 0 1 0 1 1 1 0 0 2 1 X X 0 XX | 1 0 0 0 0 4 00 0 0 0 -- PhB3
0 0 1 0 1 1 1 0 0 2 1 X X 0 XX | 0 0 0 0 0 4 A1 0 0 0 -- Done
0 0 1 1 1 1 1 0 0 2 1 X X 0 XX | 0 0 0 0 0 4 A0 0 0 0 -- Idle
0 0 1 1 0 1 1 0 0 3 0 X X 0 XX | 1 0 0 0 0 8 C0 0 0 0 -- Initiate read cycle
0 0 1 1 0 1 1 0 0 3 0 X X 0 XX | 1 0 0 0 0 8 C0 0 0 0 -- pass 1st sync
0 0 1 1 0 1 1 0 0 3 0 X X 0 XX | 1 0 0 0 0 8 C0 0 0 0 -- pass 2nd sync
0 0 1 1 0 1 1 0 0 3 0 X X 0 XX | 1 1 0 0 0 8 C0 0 1 1 -- PhA1
0 0 1 1 0 1 1 0 0 3 0 X X 0 XX | 1 1 0 0 0 8 C0 0 1 1 -- PhA2
0 0 1 1 0 1 1 0 0 3 0 X X 0 XX | 1 0 1 0 0 8 C0 0 0 0 -- PhB1
0 0 1 1 0 1 1 0 0 3 0 0 0 0 XX | 1 0 1 0 0 8 00 1 0 0 -- PhB2
0 0 1 1 0 1 1 0 0 3 0 X X 0 XX | 1 0 0 0 0 8 00 0 0 0 -- PhB3
0 0 1 1 0 1 1 0 0 3 0 X X 0 XX | 0 0 0 0 0 8 C0 0 0 0 -- Done
0 0 1 1 1 1 1 0 0 3 0 X X 0 XX | 0 0 0 0 0 8 C0 0 0 0 -- Idle
0 0 1 1 1 0 1 0 0 0 1 X X 0 XX | 1 0 0 0 0 1 89 0 0 0 -- Initiate write cycle
0 0 1 1 1 0 1 0 0 0 1 X X 0 XX | 1 0 0 0 0 1 89 0 0 0 -- pass 1st sync
0 0 1 1 1 0 1 0 0 0 1 X X 0 XX | 1 0 0 0 0 1 89 0 0 0 -- pass 2nd sync
0 0 1 1 1 0 1 0 0 0 1 X X 0 XX | 1 1 0 0 0 1 89 0 1 1 -- PhA1
0 0 1 1 1 0 1 0 0 0 1 X X 0 XX | 1 1 0 0 0 1 89 0 1 1 -- PhA2
0 0 1 1 1 0 1 0 0 0 1 X X 0 XX | 1 0 1 0 0 1 89 0 0 1 -- PhB1
0 0 1 1 1 0 1 0 0 0 1 1 1 0 XX | 1 0 1 0 0 1 00 0 0 1 -- PhB2, reject, fault
0 0 1 1 1 0 1 0 0 0 1 X X 0 XX | 1 0 0 1 0 1 00 0 0 0 -- PhB3
0 0 1 1 1 0 1 0 0 0 1 X X 0 XX | 1 1 0 0 0 1 00 0 1 1 -- PhA1
0 0 1 1 1 0 1 0 0 0 1 X X 0 XX | 1 1 0 0 0 1 00 0 1 1 -- PhA2
0 0 1 1 1 0 1 0 0 0 1 X X 0 XX | 1 0 1 0 0 1 00 0 0 1 -- PhB1
0 0 1 1 1 0 1 0 0 0 1 0 0 0 XX | 1 0 1 0 0 1 00 0 0 1 -- PhB2
0 0 1 1 1 0 1 0 0 0 1 X X 0 XX | 1 0 0 0 0 1 00 0 0 0 -- PhB3
0 0 1 1 1 0 1 0 0 0 1 X X 0 XX | 0 0 0 0 0 1 89 0 0 0 -- Done
0 0 1 1 1 1 1 0 0 0 1 X X 0 XX | 0 0 0 0 0 1 88 0 0 0 -- Idle
0 0 0 1 1 1 0 1 0 1 0 X X 0 XX | 1 0 0 0 0 2 XX 0 0 0 -- Initiate read cycle
0 0 0 1 1 1 0 1 0 1 0 X X 0 XX | 1 0 0 0 0 2 XX 0 0 0 -- pass 1st sync
0 0 0 1 1 1 0 1 0 1 0 X X 0 XX | 1 0 0 0 0 2 XX 0 0 0 -- pass 2nd sync
0 0 0 1 1 1 0 1 0 1 0 X X 0 XX | 1 0 0 0 0 2 XX 0 0 0 -- EndOfCycle
0 0 0 1 1 1 0 1 0 1 0 X X 0 XX | 0 0 0 0 0 2 XX 0 0 0 -- Done
0 0 1 1 1 1 0 1 0 1 0 X X 0 XX | 0 0 0 0 0 2 XX 0 0 0 -- Idle
0 0 1 0 1 1 0 1 0 2 0 X X 0 XX | 1 0 0 0 0 C XX 0 0 0 -- Initiate read cycle
0 0 1 0 1 1 0 1 0 2 0 X X 0 XX | 1 0 0 0 0 C XX 0 0 0 -- pass 1st sync
0 0 1 0 1 1 0 1 0 2 0 X X 0 XX | 1 0 0 0 1 C XX 0 0 0 -- pass 2nd sync
0 0 1 0 1 1 0 1 0 2 0 X X 0 XX | 1 0 0 0 0 C XX 0 0 0 -- EndOfCycle
0 0 1 0 1 1 0 1 0 2 0 X X 0 XX | 0 0 0 0 0 C XX 0 0 0 -- Done
0 0 1 1 1 1 0 1 0 2 0 X X 0 XX | 0 0 0 0 0 C XX 0 0 0 -- Idle
0 0 1 0 1 1 0 1 0 0 1 X X 1 C5 | 1 0 0 0 0 1 C5 0 0 0 -- Initiate read cycle
0 0 1 0 1 1 0 1 0 0 1 X X 1 C5 | 1 0 0 0 0 1 C5 0 0 0 -- pass 1st sync
0 0 1 0 1 1 0 1 0 0 1 X X 1 C5 | 1 0 0 0 1 1 C5 0 0 0 -- pass 2nd sync
0 0 1 0 1 1 0 1 0 0 1 X X 1 C5 | 1 0 0 0 0 1 C5 0 0 0 -- decide PBus
0 0 1 0 1 1 0 1 0 0 1 X X 1 C5 | 1 1 0 0 0 1 C5 0 1 1 -- PhA1
0 0 1 0 1 1 0 1 0 0 1 X X 1 C5 | 1 1 0 0 0 1 C5 0 1 1 -- PhA2
0 0 1 0 1 1 0 1 0 0 1 X X 1 C5 | 1 0 1 0 0 1 C5 0 0 1 -- PhB1
0 0 1 0 1 1 0 1 0 0 1 0 0 1 C5 | 1 0 1 0 0 1 00 0 0 1 -- PhB2
0 0 1 0 1 1 0 1 0 0 1 X X 1 C5 | 1 0 0 0 0 1 00 0 0 0 -- PhB3
0 0 1 0 1 1 0 1 0 0 1 X X 1 C5 | 0 0 0 0 0 1 C5 0 0 0 -- Done
0 0 1 1 1 1 0 1 0 0 1 X X 1 C5 | 0 0 0 0 0 1 C5 0 0 0 -- Idle
0 0 1 0 1 1 0 1 0 0 0 X X 1 F2 | 1 0 0 0 0 3 F2 0 0 0 -- Initiate read cycle
0 0 1 0 1 1 0 1 0 0 0 X X 1 F2 | 1 0 0 0 0 3 F2 0 0 0 -- pass 1st sync
0 0 1 0 1 1 0 1 0 0 0 X X 1 F2 | 1 0 0 0 1 3 F2 0 0 0 -- pass 2nd sync
0 0 1 0 1 1 0 1 0 0 0 X X 1 F2 | 1 0 0 0 0 3 F2 0 0 0 -- decide PBus
0 0 1 0 1 1 0 1 0 0 0 X X 1 F2 | 1 1 0 0 0 3 F2 0 1 1 -- PhA1
0 0 1 0 1 1 0 1 0 0 0 X X 1 F2 | 1 1 0 0 0 3 F2 0 1 1 -- PhA2
0 0 1 0 1 1 0 1 0 0 0 X X 1 F2 | 1 0 1 0 0 3 F2 0 0 0 -- PhB1
0 0 1 0 1 1 0 1 0 0 0 0 0 1 F2 | 1 0 1 0 0 3 00 1 0 0 -- PhB2
0 0 1 0 1 1 0 1 0 0 0 X X 1 F2 | 1 0 0 0 0 3 00 0 0 0 -- PhB3
0 0 1 0 1 1 0 1 0 0 0 X X 1 F2 | 0 0 0 0 0 3 F2 0 0 0 -- Done
0 0 1 1 1 1 0 1 0 0 0 X X 1 F2 | 0 0 0 0 0 3 F2 0 0 0 -- Idle
0 0 1 1 1 1 0 1 1 1 0 X X X XX | 0 0 0 0 0 2 XX 0 0 0 -- Set IOCS first!
0 0 0 1 1 1 0 1 1 1 0 X X X XX | 0 0 0 0 0 2 XX 0 0 0 -- No cycle initiated
0 0 0 1 1 1 0 1 1 1 0 X X X XX | 0 0 0 0 0 2 XX 0 0 0 -- No cycle initiated
0 0 1 1 1 1 0 1 1 1 0 X X X XX | 0 0 0 0 0 2 XX 0 0 0 -- Idle
0 0 1 1 1 1 0 1 1 2 0 X X X XX | 0 0 0 0 0 C XX 0 0 0 -- Set IOCS first!
0 0 1 0 1 1 0 1 1 2 0 X X X XX | 0 0 0 0 0 C XX 0 0 0 -- No cycle initiated
0 0 1 0 1 1 0 1 1 2 0 X X X XX | 0 0 0 0 0 C XX 0 0 0 -- No cycle initiated
0 0 1 1 1 1 0 1 1 2 0 X X X XX | 0 0 0 0 0 C XX 0 0 0 -- Idle

.
ZIOBusSlaveCtl.oracle
Jean-Marc Frailong June 12, 1987 5:38:55 pm PDT
Test of the IOBus slave control.


Outputs:
HReset, Reset (0), nRD (0), nWR (0), nRDX (0), nWRX (0), nIOCS (0), nMemCS (0), nCKSlot (0), A1A0 (2), nBHE (0),  PReject (0), PFault (0), SelPBusCmd (0), IOPCmd (8)

Inputs:
Busy (0), PhA (0), PhB (0), PBusErr (0), WRPulse (0), ByteEn (4), PCmd(8), LdPResult (0), EnPAddr (0), DrvPBus (0)


HReset 
Reset 
nRD 
nWR 
nRDX 
nWRX 
nIOCS 
nMemCS 
nCKSlot 
A1A0 
nBHE 
PReject 
PFault 
SelPBusCmd 
IOPCmd | 
Busy 
PhA 
PhB 
PBusErr 
WRPulse 
ByteEn 
PCmd 
LdPResult 
EnPAddr 
DrvPBus -- 
Comment

Initialization, byte enable check
Harware reset and normal reset
Attempt memory cycle while Reset, /Hreset (No-Op)
Attempt I/O cycle while Reset, /Hreset (Effective) & remove Reset
Check byte enables
Basic memory cycles
Basic memory cycle, read, no reject, low 16-bits
Basic memory cycle, write, 1 reject cycle, lo-hi byte
Extended memory cycles
Extended memory cycle, read, no reject, hi-hi byte (msb)
Extended memory cycle, write, fault cycle, lo-lo byte (lsb)
Regular I/O cycles
Regular I/O cycle, read
Regular I/O cycle, write
PBusCmd I/O cycles
Write PBusCmd reg (lo-byte) - initiates PBus write cycle
Write PBusCmd reg (16-bits) - initiates PBus read cycle
Ignored I/O cycles
Ignored I/O cycle, read
Ignored I/O cycle, write
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