1 0 0 0 0 | X X X X X X X -- Initial state is unknown 1 0 0 0 0 | X 0 1 0 0 0 0 -- Automaton needs 5 cycles to reset itself 1 0 0 0 0 | X 0 1 0 0 0 0 -- although this is not visible from the outside... 1 0 0 0 0 | X 0 1 0 0 0 0 -- 1 0 0 0 0 | X 0 1 0 0 0 0 -- 1 0 0 0 0 | X 0 1 0 0 0 0 -- 1 0 0 0 0 | 0 0 1 0 0 0 0 -- 0 0 0 0 0 | 0 0 1 0 0 0 0 -- 0 0 1 0 0 | 0 0 1 1 0 0 0 -- Len5, SelB5 0 0 0 0 0 | 0 0 1 0 0 0 0 -- Len2, SelB5 0 0 0 0 0 | 0 0 1 0 0 0 0 -- RIdle, Len2P1 0 1 0 0 0 | 0 0 0 0 0 0 0 -- D21 0 1 0 0 0 | 0 0 1 0 0 0 0 -- Idle 0 1 1 0 0 | 0 0 0 0 0 0 0 -- D21, check Len5 insensitive 0 1 0 0 0 | 0 0 1 0 0 0 0 -- Idle 0 0 1 0 0 | 0 0 1 1 0 0 0 -- RIdle, Len5P1 0 1 1 0 0 | 0 0 0 1 0 0 0 -- D51 0 1 1 0 0 | 0 0 0 1 0 0 0 -- D52 0 1 1 0 0 | 0 0 0 1 0 0 0 -- D53 0 1 1 0 0 | 0 0 0 1 0 0 0 -- D54 0 1 1 0 0 | 0 0 1 1 0 0 0 -- Idle 0 1 0 0 0 | 0 0 0 1 0 0 0 -- D51, check Len5 insensitive 0 1 1 0 0 | 0 0 0 1 0 0 0 -- D52 0 1 0 0 0 | 0 0 0 1 0 0 0 -- D53 0 1 1 0 0 | 0 0 0 1 0 0 0 -- D54 0 1 0 0 0 | 0 0 1 0 0 0 0 -- Idle 0 0 0 1 0 | 3 0 1 0 0 0 0 -- ArmB2 0 0 0 0 0 | 0 1 1 0 1 0 0 -- Armed 0 0 1 0 0 | 0 0 1 1 1 0 0 -- Check wiggling Len affects HdrOut, not arm buffer 0 0 0 0 0 | 0 1 1 0 1 0 0 -- 0 0 1 0 0 | 0 0 1 1 1 0 0 -- 0 1 0 0 0 | 0 0 0 1 1 0 0 -- D51 0 1 0 0 0 | 0 0 0 1 1 0 0 -- D52 0 1 0 0 0 | 0 0 0 1 1 0 0 -- D53 0 1 0 0 0 | 0 0 0 1 1 0 0 -- D54 0 1 0 0 0 | 0 1 1 0 1 0 0 -- Idle, Len2 0 1 0 0 0 | 0 0 0 0 1 0 0 -- D21 0 1 0 0 0 | 0 0 1 0 0 0 0 -- Idle, arm buffer has now disarmed 0 1 0 1 0 | 3 0 0 0 0 0 0 -- ArmB2 and new cycle (D21) 0 1 0 0 0 | 0 1 1 0 1 0 0 -- Idle again, should not disarm 0 1 0 0 0 | 0 0 0 0 1 0 0 -- D21 0 1 0 0 0 | 0 0 1 0 0 0 0 -- Idle, disarm the buffer for real now 0 1 0 0 0 | 0 0 0 0 0 0 0 -- D21 0 1 0 1 0 | 3 0 1 0 0 0 0 -- Idle again, should rearm just after 0 0 0 0 0 | 0 1 1 0 1 0 0 -- Wait a little 0 0 0 0 0 | 0 1 1 0 1 0 0 -- Wait a little 0 1 0 0 0 | 0 0 0 0 1 0 0 -- D21 0 1 0 0 0 | 0 0 1 0 0 0 0 -- Idle, disarm the buffer for real now 0 0 1 0 1 | 2 0 1 1 0 0 0 -- ArmB5 0 0 1 0 0 | 0 1 1 1 0 1 0 -- Armed 0 0 0 0 0 | 0 0 1 0 0 1 0 -- Check wiggling Len affects HdrOut, not arm buffer 0 0 1 0 0 | 0 1 1 1 0 1 0 -- 0 0 0 0 0 | 0 0 1 0 0 1 0 -- 0 1 0 0 0 | 0 0 0 0 0 1 0 -- D21 0 1 1 0 0 | 0 1 1 1 0 1 0 -- Idle, Len5 0 1 1 0 0 | 0 0 0 1 0 1 1 -- D51 0 1 1 0 0 | 0 0 0 1 0 1 1 -- D52 0 1 1 0 0 | 0 0 0 1 0 1 1 -- D53 0 1 1 0 0 | 0 0 0 1 0 1 0 -- D54 0 1 1 0 0 | 0 0 1 1 0 0 0 -- Idle, arm buffer has now disarmed 0 1 1 0 1 | 2 0 0 1 0 0 0 -- ArmB2 and new cycle (D51) 0 1 1 0 0 | 0 0 0 1 0 1 0 -- D52 0 1 1 0 0 | 0 0 0 1 0 1 0 -- D53 0 1 1 0 0 | 0 0 0 1 0 1 0 -- D54 0 1 1 0 0 | 0 1 1 1 0 1 0 -- Idle again, should not disarm 0 1 1 0 0 | 0 0 0 1 0 1 1 -- D51 0 1 1 0 0 | 0 0 0 1 0 1 1 -- D52 0 1 1 0 0 | 0 0 0 1 0 1 1 -- D53 0 1 1 0 0 | 0 0 0 1 0 1 0 -- D54 0 1 1 0 0 | 0 0 1 1 0 0 0 -- Idle, disarm the buffer for real now 0 1 1 0 0 | 0 0 0 1 0 0 0 -- D51 0 1 1 0 1 | 2 0 0 1 0 0 0 -- D52 & Arm 0 1 1 0 0 | 0 0 0 1 0 1 0 -- D53 0 1 1 0 0 | 0 0 0 1 0 1 0 -- D54 0 1 1 0 0 | 0 1 1 1 0 1 0 -- Idle again, should not disarm 0 1 1 0 0 | 0 0 0 1 0 1 1 -- D51 0 1 1 0 0 | 0 0 0 1 0 1 1 -- D52 0 1 1 0 0 | 0 0 0 1 0 1 1 -- D53 0 1 1 0 0 | 0 0 0 1 0 1 0 -- D54 0 1 1 0 0 | 0 0 1 1 0 0 0 -- Idle, disarm the buffer for real now 0 1 1 0 0 | 0 0 0 1 0 0 0 -- D51 0 1 1 0 0 | 0 0 0 1 0 0 0 -- D52 0 1 1 0 1 | 2 0 0 1 0 0 0 -- D53 & Arm 0 1 1 0 0 | 0 0 0 1 0 1 0 -- D54 0 1 1 0 0 | 0 1 1 1 0 1 0 -- Idle again, should not disarm 0 1 1 0 0 | 0 0 0 1 0 1 1 -- D51 0 1 1 0 0 | 0 0 0 1 0 1 1 -- D52 0 1 1 0 0 | 0 0 0 1 0 1 1 -- D53 0 1 1 0 0 | 0 0 0 1 0 1 0 -- D54 0 1 1 0 0 | 0 0 1 1 0 0 0 -- Idle, disarm the buffer for real now 0 1 1 0 0 | 0 0 0 1 0 0 0 -- D51 0 1 1 0 0 | 0 0 0 1 0 0 0 -- D52 0 1 1 0 0 | 0 0 0 1 0 0 0 -- D53 0 1 1 0 1 | 2 0 0 1 0 0 0 -- D54 & Arm 0 1 1 0 0 | 0 1 1 1 0 1 0 -- Idle again, should not disarm 0 1 1 0 0 | 0 0 0 1 0 1 1 -- D51 0 1 1 0 0 | 0 0 0 1 0 1 1 -- D52 0 1 1 0 0 | 0 0 0 1 0 1 1 -- D53 0 1 1 0 0 | 0 0 0 1 0 1 0 -- D54 0 1 1 0 0 | 0 0 1 1 0 0 0 -- Idle, disarm the buffer for real now 0 1 1 0 0 | 0 0 0 1 0 0 0 -- D51 0 1 1 0 0 | 0 0 0 1 0 0 0 -- D52 0 1 1 0 0 | 0 0 0 1 0 0 0 -- D53 0 1 1 0 0 | 0 0 0 1 0 0 0 -- D54 & Arm 0 1 1 0 1 | 2 0 1 1 0 0 0 -- Idle again, should not disarm 0 0 1 0 0 | 0 1 1 1 0 1 0 -- Wait a bit 0 0 1 0 0 | 0 1 1 1 0 1 0 -- Wait a bit 0 1 1 0 0 | 0 0 0 1 0 1 1 -- D51 0 1 1 0 0 | 0 0 0 1 0 1 1 -- D52 0 1 1 0 0 | 0 0 0 1 0 1 1 -- D53 0 1 1 0 0 | 0 0 0 1 0 1 0 -- D54 0 1 1 0 0 | 0 0 1 1 0 0 0 -- Idle, disarm the buffer for real now 0 0 1 1 1 | 3 0 1 1 0 0 0 -- ArmB2 & ArmB5, emit 2-cycle request 0 0 1 0 0 | 2 1 1 1 1 1 0 -- Armed, emit 5 cycle request 0 0 1 0 0 | 0 1 1 1 1 1 0 -- Armed, nothing more happens . XDynaBusOutputCtl.oracle Jean-Marc Frailong June 29, 1987 3:46:18 pm PDT Outputs: Reset (0), iGrant (0), iGLength (0), ArmB2 (0), ArmB5 (0) Inputs: iRequest (2), iHeaderOut (0), SelHdr (0), SelB5 (0), B2Busy (0), B5Busy (0), AdvB5 (0) Reset iGrant iGLength ArmB2 ArmB5 | iRequest iHeaderOut SelHdr SelB5 B2Busy B5Busy AdvB5 -- Comment Test of the IOB DynaBus output controller Reset sequence Check Len5 wiggles SelB5 Check Grant automaton 2-cycle branch 5-cycle branch Check 2-cycle buffer control Check arm buffer arms and does not disarm improperly Check arm buffer does not disarm on 5-cycle reception Check arm buffer does disarm on 2-cycle reception when armed Check arm buffer is not considered when activated on GT1 Check arm buffer is not considered when activated on GT2 Check 5-cycle buffer control Check arm buffer arms and does not disarm improperly Check arm buffer does not disarm on 2-cycle reception Check arm buffer does disarm on 5-cycle reception when armed Check arm buffer is not considered when activated on GT1 Check arm buffer is not considered when activated on GT2 Check arm buffer is not considered when activated on GT3 Check arm buffer is not considered when activated on GT4 Check arm buffer is not considered when activated on GT5 Check simultaneous requests Arm both buffers and check what happens... Κ[˜šœ™Icode™/—J˜™J™9J™—™JšΠftœN™V—J™Jš3œΟfœžœžœžœžΟtŸœ žœžœžœžœžœœΟcΠct ‘™~J™head™)™JšžΟi˜5Jšž’+˜EJšž’3˜MJšž’˜Jšž’˜Jšž’˜Jšž’˜Jšž’˜—™Jšž’˜(Jšž’˜(—™™Jšž’˜*J˜Jšž’˜ Jšž’˜!J˜Jšž’˜8Jšž’˜!—™Jšž’˜*J˜Jšž’˜ Jšž’˜ Jšž’˜ Jšž’˜ Jšž’˜!J˜Jšž’˜8Jšž’˜ Jšž’˜ Jšž’˜ Jšž’˜!——™™4Jšž’˜"Jšž’˜"Jšž’4˜NJšž’˜—™5Jšž’˜Jšž’˜ Jšž’˜ Jšž’˜ Jšž’˜ Jšž’ ˜'—™—™8Jšž’˜6Jšž’ ˜:J˜Jšž’˜ Jšž’'˜A—™8Jšž’˜ Jšž’&˜@J˜Jšž’˜*Jšž’˜*J˜Jšž’˜ Jšž’'˜A—J˜—™™4Jšž’˜"Jšž’˜"Jšž’4˜NJšž’˜—™5Jšž’˜Jšž’˜ Jšž’ ˜'—™—™8Jšž’˜6Jšž’˜ Jšž’˜ Jšž’˜ Jšž’ ˜:J˜Jšž’˜ Jšž’˜ Jšž’˜ Jšž’˜ Jšž’'˜A—™8Jšž’˜ Jšž’ ˜&Jšž’˜ Jšž’˜ Jšž’ ˜:J˜Jšž’˜ Jšž’˜ Jšž’˜ Jšž’˜ Jšž’'˜A—™8Jšž’˜ Jšž’˜ Jšž’ ˜&Jšž’˜ Jšž’ ˜:J˜Jšž’˜ Jšž’˜ Jšž’˜ Jšž’˜ Jšž’'˜A—™8Jšž’˜ Jšž’˜ Jšž’˜ Jšž’ ˜&Jšž’ ˜:J˜Jšž’˜ Jšž’˜ Jšž’˜ Jšž’˜ Jšž’'˜A—™8Jšž’˜ Jšž’˜ Jšž’˜ Jšž’ ˜&Jšž’ ˜:J˜Jšž’ ˜'Jšž’ ˜'J˜Jšž’˜ Jšž’˜ Jšž’˜ Jšž’˜ Jšž’'˜A—J˜—™™*Jšž’&˜@Jšž’˜8Jšž’˜8—J˜——J˜—…—Š=