IOBridge Chip
- Bridge between DynaBus and IOBus:
DynaBus I/O space -> IOBus Mem space
DynaBus I/O space -> IOBus I/O space
IOBus Mem space -> DynaBus Mem space
- Internal peripherals:
Time management (fast clock, TODC, timer)
Interrupt management
DBus master
- Flexibility:
IOBus interface well isolated
Easily modified for 16/32 bits data bus
- Major constraints:
Latency IOBus -> DynaBus (Ethernet)
Asynchronous system
IOBus
- Extension of PC/AT bus:
16 bits bidirectional data
34 address bits (32+2)
byte/half word transactions
8/10 MHz clock
- Supports low to medium speed devices:
Hard disk/floppy controller (1-2 MB/s)
Ethernet controller (1.25 MB/s)
Odds and ends (negligible)
- IOBridge seen as 1-wait state memory
Max rate: 5.3 MB/s (8 MHz), 6.7 MB/s (10 MHz)
IOBridge internals
- No IOBus address translation support:
Disk controller supports scatter/gather
Fixed area buffers sufficient for Ethernet
- IOBus managed as Dragon processor:
Uses external Dragon cache
IOBus to PBus internal converter
- Direct DynaBus access:
I/O request queue
Allows all cache-supported transactions
Remaining problems
- Byte/Halfword swapping is an unsolved issue
- Address mappping still requires consideration
- Details of cache interface to be worked out
- DBus Freeze to be handled on IOBus side