IOBCountdown.cm
Copyright Ó 1987 by Xerox Corporation. All rights reserved.
Louis Monier October 12, 1987 11:14:55 am PDT
Jean-Marc Frailong November 17, 1987 7:38:47 pm PST
-- Goal
-- This command file captures all the operations necessary to "finish" the IOBridge before fabrication.
-- It is derived from LM's Countdown.cm
-- Assumptions
-- All libraries have been run through the DRC and Lichen (standard cells, pads, ram) and are frozen until the run goes out.
-- The design is completed, has been simulated at transistor level, and some timing estimation made (Mint, Spice...)
-- For power bus sizing, eyeball and be conservative.
-- You have a df file pertaining to this chip; the df file must verify, so that you can switch between machines rapidly.
-- You keep a daily log of your work on the chip (very useful when testing the wafers).
-- Start everything, read in the source design and extract chip
ColorDisplayModeOff
-- Saves quite a lot of time...
CDCMosB
Install IOBridge SC PadFrames
-- ← TWOps.host ← "Tregonsee"
-- Install all useful programs. Others may be added here, or later on the way (depending on RollBacks...)
← CedarProcess.SetPriority[background]
Statistics on
-- You always want to know how long it took
CDRead IOBridge
← &design ← CDViewer.FindDesign["IOBridge"]
-- Read the CD design & all its importees, then retrieve design
← &cx ← Sisyph.Create[&design,
NIL]
-- Creates a context for Sisyph
← &ct ← Sisyph.
ES["IOBridge.sch", &cx]
-- Extracts the top-level schematic
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← SafeStorage.ReclaimCollectibleObjects[TRUE, TRUE]
ForceReclaimFreePages 5; ForceReclaimFreePages 5
-- Do a trace & sweep garbage collection and recover free pages
-- Checks on the source cell type
-- Apply Static
Install Static
← Static.CountLeafConnections[&ct, Static.CheckCount, CoreFlat.CreateCutSet[labels: LIST["Logic"]]]
-- Errors can be found in the terminal
-- Apply MintCheck (analysis of incorrect electric connections) on schematic
Install Mint
← &circuit ← Mint.CreateCircuit[&ct]
← MintCmds.PrepareCircuit[&circuit, FALSE]
← Mint.CheckLibrary[&circuit]
-- Errors can be found found in the terminal
-- Make a note of this number of transistors, and write home about it
-- You also get an estimation of the total capacitance which you can use to derive an upper bound on the average power consumption.
← Mint.KillCircuit[&circuit]
← &circuit ← NIL
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← SafeStorage.ReclaimCollectibleObjects[TRUE, TRUE]
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-- Destroy circuit, do a trace & sweep garbage collection and recover free pages
-- Simulate as completely as possible, at transistor level (assuming oracle)
← &oracle ← Sisyph.ES["IOBridge.test", &cx]
-- Extracts the schematics containing the top-level cell with its oracle (assuming same design)
-- use the "log" parameter on the oracle
-- put an object property "Simulation: $Transistors" inside BICTransistorLevel.sim to be sure to simulate at transistor level; if you stay at gate level for example, your blind faith in Logic might cost you a lot.
-- when simulating at transistor level, use a separate clock for the circuit and the oracle: up𡤂 and dn𡤂 on both, but firstEdge ← 2 on the circuit clock works well and preserves the oracle file.
← Ports.CoerceNewToOld[&oracle.public]
← Rosemary.SetFixedWire[CoreOps.FindWire[&oracle.public, "Vdd"], H]
← Rosemary.SetFixedWire[CoreOps.FindWire[&oracle.public, "Gnd"], L]
← &tester ← RosemaryUser.TestProcedureViewer[cellType: &oracle, testButtons: LIST["Logic Test"], name: "IOBridge transistor level test", cutSet: NIL]
← RosemaryUser.StartTest[&tester]
-- Batch mode for oracle.
open ///Temp/InterfaceChip.bugs
The log of all bugs found during the simulation; if empty, no bugs
-- Generate Layout
← &scBlock ← Sisyph.ES["IOBInnerSC.sch", &cx]
← PWCore.Layout[&scBlock]
-- Build the layout for the SC part (this needs to be done in a first step in order to GC all)
← PWCore.Store[&scBlock,
TRUE]
-- and save it (who knows...)
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← SafeStorage.ReclaimCollectibleObjects[TRUE, TRUE]
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-- Do a trace & sweep garbage collection and recover free pages
← &ob ← PWCore.Layout[&ct]
-- Creates the CD object and attaches it to the cellType
←
PW.Draw[&ob]
-- Just a viewer; don't edit or save it
← PWCore.Store[&ct,
FALSE]
-- Saves the decorated Core under IOBridge.core, the layout under IOBridgeLayout.dale, and a view of the public pins under IOBridgeShell.dale
-- The decorated Core will be read back for future work
-- The layout will be DRCed, plotted, and turned into a Mebes file
-- The shell will be needed to check the pad position and make the probing and bonding maps
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← SafeStorage.ReclaimCollectibleObjects[TRUE, TRUE]
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-- Do a trace & sweep garbage collection and recover free pages
-- Checks on the generated layout
-- Compare layout and schematics
Install PWCoreLichen
← CoreProperties.PutCellTypeProp[on: &ct, prop: $LichenTransistorTolerances, value: "0.8, 0.8"]
That's length and width, commented out for the time being...
← PWCoreLichen.SetAutomorphismHack[TRUE]
← PWCoreLichen.Compare[&ct]
-- Compares the cellType with the extracted layout
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← SafeStorage.ReclaimCollectibleObjects[TRUE, TRUE]
ForceReclaimFreePages 5; ForceReclaimFreePages 5
-- Do a trace & sweep garbage collection and recover free pages
-- Check the connectivity
Install ConnectivityChecker
CheckConnectivity IOBridgeLayout.dale
-- Signals all disconnected internals; returns a list of disconnected publics
← RoutingCheckImpl.Check[
PW.OpenDesign["IOBridgeLayout.dale"]]
-- Checks for shorts in routing cells
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← SafeStorage.ReclaimCollectibleObjects[TRUE, TRUE]
ForceReclaimFreePages 5; ForceReclaimFreePages 5
-- Do a trace & sweep garbage collection and recover free pages
-- Check design rules
-- No programming interface right now...