<> <> <> <> <> <> <> <> DIRECTORY DragOpsCross; Dragon: CEDAR DEFINITIONS = BEGIN -- Dragon -- Word: TYPE = LONG CARDINAL; HexNibble: TYPE = [0..16); -- forces hexadecimal ViewRec HexByte: TYPE = Byte; -- forces hexadecimal ViewRec HexWord: TYPE = Word; -- forces hexadecimal ViewRec Byte: TYPE = [0..256); Opcode: TYPE = HexByte; EURegisterIndex: TYPE = [0..256); SLRange: TYPE = EURegisterIndex[0..128); Phase: TYPE = MACHINE DEPENDENT {a(0), b(1)}; Cycle: TYPE = NAT; UndefinedValue: Dragon.HexWord = 01234567H; ALUOps: TYPE = MACHINE DEPENDENT { Or(0), And(1), VAdd2(2), BndChk(3), SAdd(4), SSub(5), LAdd(6), LSub(7), Xor(8), res9(9), FOP(10), res11(11), VAdd(12), VSub(13), UAdd(14), USub(15) }; aluOpSig: ALUOps = LOOPHOLE[15]; CondSelects: TYPE = MACHINE DEPENDENT { False (DragOpsCross.TrapIndex[ ALUCondFalse ].ORD MOD 16), EZ (DragOpsCross.TrapIndex[ ALUCondEZ ].ORD MOD 16), LZ (DragOpsCross.TrapIndex[ ALUCondLZ ].ORD MOD 16), LE (DragOpsCross.TrapIndex[ ALUCondLE ].ORD MOD 16), res4 (DragOpsCross.TrapIndex[ ALUCondSpare ].ORD MOD 16), NE (DragOpsCross.TrapIndex[ ALUCondNE ].ORD MOD 16), GE (DragOpsCross.TrapIndex[ ALUCondGE ].ORD MOD 16), GZ (DragOpsCross.TrapIndex[ ALUCondGZ ].ORD MOD 16), OvFl (DragOpsCross.TrapIndex[ ALUCondOver ].ORD MOD 16), BC (DragOpsCross.TrapIndex[ ALUCondBC ].ORD MOD 16), IL (DragOpsCross.TrapIndex[ ALUCondIL ].ORD MOD 16), res11 (DragOpsCross.TrapIndex[ ALUCondDO ].ORD MOD 16), res12 (DragOpsCross.TrapIndex[ ALUCondNotOver ].ORD MOD 16), NotBC (DragOpsCross.TrapIndex[ ALUCondNB ].ORD MOD 16), NotIL (DragOpsCross.TrapIndex[ ALUCondNI ].ORD MOD 16), ModeFault (DragOpsCross.TrapIndex[ ModeFault ].ORD MOD 16) }; ALULeftSources: TYPE = MACHINE DEPENDENT {aBus(0), rBus(1), cBus(2), reserve3(3)}; ALURightSources: TYPE = MACHINE DEPENDENT {bBus(0), rBus(1), cBus(2), kBus(3), fCtlReg(4), reserve5(5), reserve6(6), reserve7(7)}; Store2ASources: TYPE = MACHINE DEPENDENT {bBus(0), rBus(1), cBus(2), reserve3(3)}; rd: [0..256) = 0; wrt: [0..256) = 1; basicCache: [0..256) = 128; io: [0..256) = 4; special: [0..256) = 2; byte0: [0..256) = 64; byte1: [0..256) = 32; byte2: [0..256) = 16; byte3: [0..256) = 8; allBytes: [0..256) = 120; cache: [0..256) = basicCache+allBytes; <> <> <> <> <> <> <> <> <> <> PBusCommands: TYPE = MACHINE DEPENDENT { NoOp(0), Fetch(cache+rd), Store(cache+wrt), FetchSpecial(cache+special+rd), IOFetch(cache+io+rd), IOStore(cache+io+wrt), IOStoreSpecial(cache+io+special+wrt) }; <> <> <> <> <> <> <> <> <> <> << AUStoreLtRt(auLtRt+wrt),>> <> <> <> <> PBusFaults: TYPE = MACHINE DEPENDENT { none (0), memAccess (8+(DragOpsCross.TrapIndex[ MemAccessFault ].ORD MOD 8)), ioAccess (8+(DragOpsCross.TrapIndex[ IOAccessFault ].ORD MOD 8)), map (8+(DragOpsCross.TrapIndex[ MapFault ].ORD MOD 8)), au (8+(DragOpsCross.TrapIndex[ AUFault ].ORD MOD 8)), timeOut (8+(DragOpsCross.TrapIndex[ DynaBusTimeOut ].ORD MOD 8)), other (8+(DragOpsCross.TrapIndex[ DynaBusOtherFault ].ORD MOD 8)) }; <> <<>> aRegKBusPos: [0..32) = 0; -- high-order 8 bits of KBus bRegKBusPos: [0..32) = 8; cRegKBusPos: [0..32) = 16; <> CacheTrans: TYPE = REF CacheTransRec; CacheTransRec: TYPE = RECORD [ instr: INT, cmd: Dragon.PBusCommands, addr, data: Dragon.Word, fault: Dragon.PBusFaults ]; RegStore: TYPE = REF RegStoreRec; RegStoreRec: TYPE = RECORD [ instr: INT, reg: DragOpsCross.ProcessorRegister, data: Dragon.Word ]; END.