How much noise can an office Dragon generate? A comparison with Daybreak may be useful. Perhaps we should build a mockup of a Dragon system which dissipates the proper amount of heat and has a fake chip that can take the place of the custom chips (IFU, EU, Data Cache, Address Cache, Map Cache, Arbiter, Memory Controller) so that we can wring out the mechanical, electrical and cooling package bugs prior to silicon availability.

We are constrained by the amount of power the room, the box the processor is wrapped up in, and the package the chips are bonded in, can each handle. We may be constrained by either air conditioning load or building wiring. We still need to discuss how power is measured, maximum power, typical power, "average" power (averaged over what?), surge power? A proposed limit is 600 watts. Could we have an office machine without forced air? Would heat sinks allow such a machine?

3/19/85 - Lee Anderson claims 400 watts is no problem, we could push him to 500 or 600 watts. Wiring is not a problem. Most system power is beyond our control. The power estimates we have so far indicate the small machine is feasible and the large one will have to be remote.

Basically we won't worry too much about this. Nonrecurring engineering costs dominate production costs for this machine. Anything that doesn't excede the space and power requirements is not likely to excede cost requirements.

We will implement the processor, memory, and display processor cards immediately with printed circuit cards, skipping the prototype step. These boards will be 4 layer, two outer signal layers so that we can reduce the capacitance and blue wire them, and two inner power layers. The bus coupler board and others will be implemented using a prototyping technology first. We have stichweld and a DA system for it already in house. Stichweld has slower turnaround for changes than wirewrap. Documentation is likely to be better with stichweld. Prototyping technology will be needed for the M bus and VME coupler boards plus whatever boards for the VME system are custom built.

We intend to use ED's 10.9" x 16" board format with 423 pin AMP HDI connector. We need rules for through hole pads, width and spacing. A specification of the baord layout with ejector and connector requirements is necessary. The size of the ZIF socket for the 144 pga's must be given. Dibbel is the vendor of choice. Gunning has a Xerox standard for PC board design.

We will assume that a single clock is distributed to the custom components and they will generate their own internal clocks from that using a calibrated delay line.

6/10/85 - Hoel has some design rules in: /Ivy/Hoel/Dragon/Packaging/PCB/ShortDesignRules.tioga

A complete printed circuit board design methodology must be put in place. We could have this contracted out. We could use Expert systems from Versatec. We could create a ChipNDale technology. How are drill tapes, photoplots, parts lists, etc. created? We could put all the layers of all the boards on a photomask and then optically blow it up, Danny Cohen at MOSIS could tell us about that. We could use platemaker. Right now, we will wait for Stever Jackson to look at the Expert 1000 system and revisit this issue later.

The PC vendor must test the boards. Should we have the garage do it also? How does ED test their boards? (New tester for 100K?) Dibbel is a possible supplier. So is Circuit Works.

The processor board will be designed to hold 20 PGAs, D bus logic, and perhaps clock distribution drivers.

The memory board will be designed assuming 1 Mbit RAMs, upgradable to 4 Mbit RAMs.

a) Because of the greater density, the Dragon system need not be designed for more than 2 memory boards.

b) The memory board will have iether 144 RAM DIPs or 288 RAM SIPs to be decided by the memory board designer.

c) Capacity of each board would be:

6/10/85 - The current plan has ED designing the memory board. It will support both narrow and wide formats. It will not interpret MHold.

This board probably contains 5 PGA's, a bunch of RAM, DACs and a little bit of ECL for seasoning.

Some people claim we should build a simple one for the masses instead of a fancy one for the few. However if we don't build the fancy one for the few the masses may never know what they are missing.

We need a remote video capability for fancy displays some day. For now the existing displays are good enough and we will defer work on this until some engineering resources are available.

We should consider using an ECL gate array for the video chain to reduce the board space and power requirements of this board. McCreight has been through the ED gate array class and is willing to act as consultant on this.

Should the IOP run Unix?

6/10/85 - ED is designing this board. Hopefully they will produce a requirements document so that we can determine if our needs will be met.

Two Dragon packages with compatible board types will be constructed. One is intended for office use and the other for installation in a machine room. Both include boards in the ED format as well as VME, at least one disk drive, and power supplies. Due to its excessive power consumption and noise, the machine room system must be installed in a machine room. Remote installation makes necessary the design for remote video transmission. The machine room version will be used for prototype debug because it is mechanically more flexible and it is electrically more difficult. Seperate fans and power supplies will be specified for each package.

We could design boards which fit into a Daybreak chassis and use the Daybreak IOP and memory boards. Then we only need design one processor board to have a machine which runs DragOps and can be mass manufactured at low cost. There may be board spacing problems with this. Peripherals may also be a problem.

The machine room package is only constrained by 19" rack format. How large is the office package? It must fit underneath standard height tables.

Office:

Machine Room:

a. Board Thickness plus Pin-Side Height:

b. Clearance between boards: say 0.2" (Card guides, slop, etc.)

c. Component Height:

d. TOTAL: looks like 1.2"

For reasons of airflow, perhaps it would be good to make the VME board spacing 1.2" as well. (The standard VME spacing is 0.8".)

There are a number of options for the mechanical arrangement of the backplane:

The VME specification limits bus length to 19 inches. The cable between backplanes either is or isn't counted as part of that length, depending upon exactly what role the cable is playing, e.g., whether signals are buffered or not.

We need to start a pin count for the backplane connector. We should include the various voltages to be supplied. At first cut we need pins for standard logic supply, nominally 5 volts, ground, ECL voltage?, bus terminating voltages for clamp diodes, bus high and low level voltages. We need to count I/O, M and D bus pins. Clock distribution?

Slot independence and slot ID's.

Two tier cache scheme cuts M bus capacitance by 30% and bus length by 16".

3/27/85 - Requirements to ED:

4/3/85 - We will take whatever IOP and memory board that ED builds for both the office and machine room versions of Dragon. In addition we will take the skins, frame, power supply, disk and backplane for the office machine. We will build a processor board and display board. We will require some modifications to the IOP. Supposedly a prototype of the C workstation with IOP, memory, and M bus is to be done by June, 1986.

The IOP has disk, ethernet, vanilla B&W display controller, keyboard and mouse interface. There may be a floppy interface and RS232 ports. We should push for one or two parallel ports as well. The board spacing is 1". There are 6 boards in the system, 1 for VME and 5 M bus. IOP, VME, and MEM take 3 leaving 3 for us.

VME M bus board has cutout to plug VME board into.

6/10/85 - We are having a PC board constructed. We plan to plug it into a Dandelion with a Multibus card cage on it.

6/10/85 - The methodology favored by Curry consists of functional simulation followed by layout followed by final simulation from extracted layout. We are not currently setup to support such a methodology.

Where does the arbiter go? On the backplane? On the coupler board? Defer until the local arbitration decision is known.

LIF sockets take less space. The extractor tool requires about 1/4" space on two sides. The additional overhead of ZIF sockets is not significant enough to consider eliminating them from the processor and memory boards. A seperate decision will be made for the display processor. The display processor could offer significant additional functionality if a few more pins were available. Power limits in 144 pin PGAs are 1.8, 2.6, 3 in convection, 200 ft./min forced air, and forced air + heat sinks respectively.

The PGA we may have made for us may have a 12mm cavity allowing for an 11mm die. It is optimal from a packaging point of view to have the die fill up the cavity. This is lousy from a die/wafer point of view.

6/10/85 - Bill Gunning has found a vendor that produces pc board like packages. He has a preliminary sketch of the layers for the package. Sealing and heat dissipation issues still have to be addressed. Currently thinking about a 200 pin array with two tier bonding.

We need an alternate to ICL. We have looked at GE. The rules they have given us so far are really for a 3 micron process. They have a 2 micron extension of those as well as a 1.25 micron process. ED has been looking at AT&T and National Semiconductor for second sources as well.