THE IOBRIDGE
THE IOBRIDGE
THE IOBRIDGE
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IOBridge Data Sheet
Interface between DynaBus & PC/AT bus
Jean-Marc Frailong and Lissy Bland
Dragon-88-05 February 3, 1988 
© Copyright 1988 Xerox Corporation. All rights reserved.
Keywords: DynaBus, IO, PC/AT, IOBridge, Address Mapping, Address Translation;
Maintained by: Jean-Marc Frailong
XEROX   Xerox Corporation
    Palo Alto Research Center
    3333 Coyote Hill Road
    Palo Alto, California 94304

For Internal Xerox Use Only
IOBridge
1.0 Brief Description
The IOBridge links the DynaBus and the PC/AT extension bus. It provides low-speed IO support and IO extensibility to DynaBus-based systems. DynaBus IO requests are translated to reads and writes on the PC/AT bus (Figure 1). The reads and writes may be 1, 2 or 4 bytes long with a choice of byte ordering. The IOBridge also maps a programmable part of the DynaBus memory into the PC/AT memory address space. Physical access to DynaBus memory from the PC/AT goes through the IOBridge and SmallCache. Finally, the IOBridge converts PC/AT interrupts into DynaBus interrupt requests.
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Figure 1: The IOBridge translates IO Requests from the Processor into reads and writes on the PC/AT bus. It maps variable length PC/AT memory addresses into 32-bit DynaBus addresses.
2.0 Pin-Out
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3.0 Block Diagram
3.1. Overall block diagram
Figure 3 is a block diagram of the IOBridge. Note that the left and right halves, that handle DynaBus->PC/AT and PC/AT->DynaBus transactions, respectively, are completely independent.
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Figure 2: Simplified block diagram of the IOBridge
3.2 DynaBus to PC/AT bus
When a command is received from the DynaBus, it is checked by the Command Recognition Block to determine if it is intended for this IOBridge. (A system may support up to 16 IOBridges.) The check is based exclusively on the header word and is a filter on the command and address fields. Only IORead, IOWrite and BIOWrite commands are supported.
The filtered commands are queued in a 16-entry FIFO. This FIFO is necessary because access time to the PC/AT bus is random, and in any case much larger than the potential IORequest throughput on the DynaBus. The FIFO holds most of the information from the header field as well as the 32, low-order bits of the data word of the IO request. Requests are processed serially. They are directed either to the PC/AT bus or to one of 3 internal IO registers visible from the DynaBus: a 32-bit free-running counter for precise timing estimates, a programmable 32-bit interrupt timer and an interrupt generator to the PC/AT bus.
When a request is for an access to the PC/AT bus, the PC/AT Master Control block first gains control of the PC/AT bus through the BReq/BAck protocol, then asserts Master to gain control of the PC/AT address bus. Transfers are done in 16-bit words, using up to two transfers if a 32-bit operation is required. The byte ordering is specified through the encoding of the address field (c.f. programming guide for details). For read operations, the response(s) are reordered in the correct byte order. The PC/AT bus is released at the completion of the request. If Fault is raised by the PC/AT during the transfer, the error bit will be set in the DynaBus reply packet.
Once a request is completed, it is queued for reply in the Reply Generation Block which provides a single pipeline stage. This is quite sufficient due to the long delay associated with taking control of the PC/AT bus. (The average latency to send the reply is much shorter than the average latency to perform an access on the PC/AT bus).
3.3 PC/AT Bus to DynaBus
The IOBridge accepts memory Read and Write commands from the PC/AT bus. The PC/AT bus receives the Wait signal as long as the cache or the IOBridge is busy. If an error is detected by the cache, the Fault signal will be raised on the PC/AT bus and fault information will be stored inside the IOBridge for retrieval, then the cycle will be terminated.
The IOBridge accepts memory Read and Write commands in two distinct areas: MemCS (Memory Chip Select) and IOCS (IO Chip Select). Only one of those areas may be selected at a time.
3.3.1 Memory
Reads and writes in the memory area are transmitted to the Small Cache via the PBus. Addresses are translated in the IOBridge using 3, 16-entry mapping RAMs (The map selected depends upon the length of the address: 20, 24 or 32 bits.) The resulting address is passed to the cache. If the cache has been loaded with ASN=-1, the address will be a physical DynaBus memory address. Otherwise, the cache will use the MapCache for further address translation. If the MapCache is used, it is the programmer's responsibility to ensure that there will be no mapping faults; PC/AT memory cycles are not retryable.
3.3.2 IO
Reads and writes in the IO area are for the PC/AT bus to access the IOBridge's internal registers and address mapping RAMs. The internal registers provided are for storing fault information and for accessing the memory cache.
1. Fault Information Registers
 The fault information registers contain the address, data and command being transmitted when the fault occured.
2. Cache Access Registers
 The cache access registers explicitly specify the address, (untranslated by the Small, Large, or Extra Map), data, and cache command to be used in accessing the cache, thus making it possible to generate DynaBus IO transactions and DynaBus ConditionalWriteSingle transactions from the PC/AT.
4.0 Programming Guide
4.1 DynaBus Requests
The IOBridge accepts three commands from the DynaBus: IORRequest, IOWRequest and BIOWRequest. Because IO transactions on the DynaBus always use a full 32-bit word while transactions on the PC/AT bus are of variable length, some extra encoding is used to specify the number and ordering of bytes when accessing the PC/AT bus from the DynaBus. Figure 3 contrasts the byte ordering and numbering used on the DynaBus and PC/AT bus. The DynaBus uses big-endian numbering with zero representing the most signifcant bit of a word. The PC/AT uses little-endian numbering; however, zero still represents the most signifcant bit of a byte. These differences in ordering require the IOBridge to implement additional logic to transmit from 1 to 4 bytes in any order.
Note: Unless otherwise specified, this section uses big-endian bit-ordering where bit 0 is the most-significant bit of a word.
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Figure 3: Numbering and ordering of bits and bytes on the DynaBus and PC/AT bus.
4.1.2 PC/AT Memory Access
Figure 4 illustrates the format for the IOBus Address Field of the IORRequest, IOWRequest and BIOWRequest commands when those commands access memory.
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Figure 4: The IOBus Address Format for DynaBus IO commands that access memory. The DeviceNo is the 4, low-order bits of the DeviceID.
There are three different Access Modes for the DynaBus IO commands that access memory: byte, half-word and word. The following explanation of the three access modes, uses a DynaBus data word (D0, D1, D2, D3) where D0 is the most significant byte and D3 is the least significant byte.
1. Byte Access (0010)
A byte is read or written at the specified 24-bit address.
2. Half-word Access (0011)
The least significant bit (bit 31) of the word is used to specify byte ordering.
a. If bit 31 = 0, then INT16 order is implemented as follows:
 D3 will be written at the 23-bit address || 0.
 D2 will be written at the 23-bit address || 1.
A read returns (0, 0, D2, D3).
b. If bit 31 = 1, then byte-stream order is implemented as follows:
 D2 will be written at the 23-bit address || 0.
 D3 will be written at the 23-bit address || 1.
A read returns (0, 0, D2, D3).
3. Word Access (0100)
The two least significant bits (bits 30 and 31) are used to specify byte ordering.
a. If bit pattern = 00, then INT32 order is implemented as follows:
 D3 will be written at the 22-bit address || 0 0.
 D2 will be written at the 22-bit address || 0 1.
 D1 will be written at the 22-bit address || 1 0.
 D0 will be written at the 22-bit address || 1 1.
 A reads returns (D0, D1, D2, D3).
b. If bit pattern = 01, then the following (probably useless) order is implemented:
 D2 will be written at the 22-bit address || 0 0.
 D3 will be written at the 22-bit address || 0 1.
 D0 will be written at the 22-bit address || 1 0.
 D1 will be written at the 22-bit address || 1 1.
 A reads returns (D0, D1, D2, D3).
c. If bit pattern = 10, then the following DOUBLEINT16 order is implemented as follows:
 D1 will be written at the 22-bit address || 0 0.  
 D0 will be written at the 22-bit address || 0 1.
 D3 will be written at the 22-bit address || 1 0.
 D2 will be written at the 22-bit address || 1 1.
 A reads returns (D0, D1, D2, D3).
d. If bit pattern = 11, then the following byte-stream order is implemented as follows:
 D0 will be written at the 22-bit address || 0 0.  
 D1 will be written at the 22-bit address || 0 1.
 D2 will be written at the 22-bit address || 1 0.
 D3 will be written at the 22-bit address || 1 1.
 A reads returns (D0, D1, D2, D3).
To summarize the most relevant information from the above:
Half-word Access Mode
If the 24, low-order bits of the IOBus Address Field are divisible by 2, a write will result in INT16 ordering. If the 24, low-order bits of the IOBus Address Field are not divisible by 2, a write will result in byte-stream ordering.
Word Access Mode
If the 24, low-order bits of the IOBus Address Field are divisible by 4, a write will result in INT32 ordering. If the (24, low-order bits of the IOBus Address Field) MOD 4 = 3, a write will result in byte-stream ordering.
4.1.3 PC/AT IO Access
Figure 5 illustrates the format for the IOBus Address Field of the IORRequest, IOWRequest and BIOWRequest commands when those commands access IO devices. Note that accesses from the DynaBus to the PC/AT IO space uses only 16 bit byte-addresses, according to Intel conventions. If write access is attempted in user mode or if the PC/AT generates a Fault signal during the cycle an error reply will be generated.
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Figure 5: IOBus Address Field of the IORRequest, IOWRequest and BIOWRequest commands that access IO devices. The DeviceNo is the 4, low-order bits of the DeviceID.
4.1.4 PC/AT Internal Registers Access
Figure 6 illustrates the format for the IOBus Address Field of the IORRequest, IOWRequest and BIOWRequest commands when those commands access Internal PC/AT Registers. Accesses from the DynaBus to the Internal PC/AT Registers use a 3-bit address. Writes are only permitted in Kernel mode. User mode writes result in an error reply.
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Figure 6: IOBus Address Field of the IORRequest, IOWRequest and BIOWRequest commands that access Internal PC/AT Registers. The DeviceNo is the 4, low-order bits of the DeviceID.
The supported values for the Address Field are:
000: PermanentClock
 Read/Write 32-bit counter. Set to 0 upon DynaBus Reset, incremented permanently at 1MHz (exact rate specified through DBus, c.f. section ). The counter automatically wraps around from 232-1 to 0 without notice. Although writing into this register is permitted to make chip testing easier, it is not expected to be written. The PermanentClock is intended to provide precise timing estimates.
001: IntervalTimer
 Read/Write 32-bit counter. Incremented permanently at 1MHz (exact rate specified through DBus, c.f. section ). When the counter wraps around from 232-1 to 0, a DynaBus interrupt is generated (if the corresponding interrupt mask bit is set) to signal expiration of the delay. The timer is not initialized during reset. It is the programmer's responsibility to initialize it at bootstrap time. There is no way to prevent the timer from interrupting except by disabling the corresponding interrupt.
010: NOT Used
 Not implemented. Writes are ignored, reads will return an unspecified value without error.
011: INTRStatus
 Read/Write 32-bit register. Reading this register will return a 1 for bit positions corresponding to pending interrupts, whether or not they are masked. Only the two most significant bits will ever be non-zero: bit 0 (MSB) if for PC/AT interrupt and bit 1 for IntervalTimer wrap-around. Writing into this register will remove interrupts corresponding to the bit positions in which a 1 is written, whereas writing a 0 does not change the interrupt status. C.f. section 4.1.6 for discussion of IOBridge interrupts.
100: INTRMask
 Read/Write 32-bit register. Only bits 0 and 1 are significant. The register is initialized to 0 upon reset. A 1 in a bit position permits the corresponding bit position in INTRStatus to generate a DynaBus interrupt. (C.f. section 4.1.6 for discussion of IOBridge interrupts.)
101: INTRReason
 Read/Write 32-bit register. Only the top 16 bits are significant (Figure 7).
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Figure 7: The Interrupt Register.
 
 The four fields of the Interrupt register are:
 Interrupt Type:
 interrupt reason to be reflected (0 to 31).
 Broadcast
 Broadcast is set to 1 for broadcast interrupts and to 0 for directed interrupts.
 DynaBusID
 This is the DynaBus ID of the processor EU cache to which the interrupt should be reflected. It should be set to all 1's when Broadcast = 1.
 Unused
 The low order 16 bits are used on writes and return 0 on reads. C.f. section 4.1.6 for discussion of IOBridge interrupts.
110: NOT Used
111: NOT Used
4.1.5 PC/AT Interrupt Acknowledge
The Application Schematic of Section VIII uses the same Intel Interrupt Controllers as those used by the PC/AT itself to reflect PC/AT interrupts to the DynaBus. This is done to limit the IOBridge pin-count. The IOBridge may generate an Interrupt Acknowledge to the Interrupt controller by using a read access with an address of the form:
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Figure 8: PC/AT interrupt acknowledge. The low-order 16 bits are ignored. The DeviceNo is the 4, low-order bits of the DeviceID.
4.1.6 IOBridge Interrupts
The IOBridge may generate DynaBus interrupts for external or internal reasons. External interrupts are initiated by the PC/AT. Internal interrupts are caused by timer wraparound. When an interrupt occurs, the corresponding bit in INTRStatus is set. Whenever the AND of INTRStatus and INTRMask has a new bit set to 1, an interrupt is sent onto the DynaBus using the specification provided by the INTRReason register.
Pin-count limitations mean that the IOBridge can only provide limited support for interrupts. More extensive support of interrupts is provided by an external interrupt controller that catches all interrupts from the PC/AT bus and presents only a summary status. Under the currently planned external hardware, a pair of Intel Interrupt Controllers are used (8259A). Managing an IOBus interrupt consists in the following steps (assuming that the 8259As have been properly initialized):
WHILE INTRStatus.bit1 DO {
INT number ← send INTA cycle -- Refer to following sections for details
Perform action for INT number -- such as signaling a condition variable
};
The programmer must be aware that no new interrupt will be signalled on the DynaBus as long as all the PC/AT interrupts have not been acknowledged. Thus, the loop outlined above must be performed until INTRStatus bit 1 is inactive.
4.2 PC/AT Requests
The PC/AT bus handles two types of requests: IO and Memory. Memory requests can access DynaBus Memory or IO Registers in the IOBridge.
4.2.1 Requests to DynaBus Memory
Requests for DynaBus Memory convert the 20, 24 or 32 bit PC/AT address, into a 32-bit DynaBus address. The conversion is done using one of the 3, 16-entry map RAMs in the IOBridge. These maps are called the Small Map, Large Map, and Extra Map. The appropriate map is selected using the address itself and examining the other signals that are asserted in conjunction with the address.
The Small Map will normally be used for 80286 CPU access. (MSDOS currently runs only in 8086 emulation mode, and generates addresses below 1M.) The Large Map will normally be used for DMA peripherals on the PC/AT bus. DMA peripherals may generate any 24-bit address. The Extra Map is intended to be used only by the disk controller, which is able to generate full 32-bit addresses. The address obtained by using the Extra Map is passed to the cache which may further remap it through the MapCache if programmed to do so.
Small Map:
If nRD or nWR is asserted in conjunction with nMemCS and the address presented on the address line is below 1M (20 bits), the Small Map is used to generate the DynaBus Address. (See Figure 9 for the precise timing relationships between the signals). When address is below 1M, only the low 16 address bits are considered (Figure 10).
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Figure 9: Timing relationships between
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Figure 10: The low-order 16 bits of the PC/AT address are used to form the DynaBus Address when the address is below one Megabyte. There are 3 subfields: page, byte offset and byte selector.
 
External hardware decodes a single 64K byte chunk of addresses in that range. Those 64K bytes are mapped in 16 pages of 4K bytes. Each page has a base address on an even 4K byte (1K, 32-bit word) boundary. The page serves as an index into the Small Map. The DynaBus address is formed by concatenating the base address retrieved by indexing Small Map[page] and the bits representing the byte offset within that page. Because the 2, low-order bits of the offset are used for byte selection, they are not used to form the DynaBus address so that for addresses below 1M, the Small Map contributes the high-order 22 bits to the DynaBus Address (Figure 11).
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Figure 11: The Use of the Small, Large and Extra Maps to generate Dynabus addresses from PC addresses.
Large Map:
If nRD or nWR is asserted in conjunction with nMemCS and the address presented on the address line is between 1M and 16 M (24 bits), all 24 address bits are used in forming the DynaBus Address (Figure 12). Those 16M bytes are mapped in 16 pages of 1M bytes.
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Figure 12: The subfields of the 24-bit PC/AT address.
 
Each page has a base address on an even 1M byte (256K 32-bit word) boundary. The page serves as an index into the Large Map. The DynaBus address is formed by concatenating the base address retrieved by indexing Large Map[page] and the bits representing the byte offset within that page. The base address is thus 14 bits long (Figure 11).
Extra Map:
The Extra Map is used for 32-bit addressing (Figure 13). It is an extension to the PC/AT addressing structure that uses its own read/write command signals, nRDX and nWRX.
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Figure 13: The subfields of the 32-bit PC/AT address.
The Extra Map is for use by IO devices with large address spaces, for example, the disk controller. All Extra Map addresses are above 16M. The address is mapped into 16 pages of 256M bytes. Each page has a base address on an even 256M byte (64M 32-bit word) boundary. The DynaBus address is formed by concatenating base address retrieved by indexing Extra Map[page] and the bits representing the byte offset within that page. The base address is thus 6 bits long (Figure 11).
4.2.1.1 Byte Selection
The low 2 IOBus address bits and nBHE act as byte selectors and allow byte or aligned half-word accesses. Unaligned half-word transactions are not permited on the PC/AT bus. The byte ordering maintains consistency for byte-streams; that is, the MSB of a DynaBus word is mapped to an IOBus address of the form 4*n and the LSB to an address of the form 4*n+3. This means that it is necessary to swap bytes when accessing half-word or word integers on the DynaBus.
4.2.1.2 DynaBus Memory Faults
If a DynaBus reference fails, a flag will be set in the PBusFault register (c.f. next section(s)) and an interrupt will be raised on the IOBus. When a reference fails, random data will be returned for a read. The issuer of the command should read the cache fault register to get the exact reason for the fault.
4.2.2 Requests to IOBridge Registers
An access to IOBridge registers is initiated when the IOBridge receives nRD or nWR while nIOCS is asserted. nIOCS is issued by an external PAL that decodes the address presented on the PC/AT backpanel to determine to what range of memory-space addresses the IO registers of the IOBridge should respond.
Only the low-order 8 bits of the address are decoded within the IOBridge. The corresponding 256-byte space is separated in 4 areas of 64 bytes each.
Byte Addr Reg Name R/W Description
00-03 PBusData R/W (0 is LSB, 3 is MSB). The contents of this register are used when PBusCmd is written.
04-07 PBusAddr   (0 is LSB, 3 is MSB). The contents of this register are used when PBusCmd is written.
08-0B PBusResult R (0 is LSB, 3 is MSB). This result is setup as a side-effect of writing into PBusCmd. It can only be read. (Writes to these addresses are ignored).
0C PBusCmd  W When this 8-bit register is written, a PBus cache transaction is initiated with the address contained in PBusAddr, the data contained in PBusData, and the 8-bit command written into PCmd. The PBusAddr must be a DynaBus 32-bit word address, no translation provided by the IOBridge. When the transaction is completed, the results returned by the cache are stored in PBusResult for later processing and the PC/AT bus cycle is finished. Refer to Cache specification for the encoding of PBusCmd. If the transaction fails, fault information is stored in PBusErrData, PBusErrAddr, PBusErrCmd, and PBusFault. Reading this register will return random information.
0D IOBusInt R This register contains the 8-bit interrupt information to be presented to the PC/AT bus. It is automatically cleared on Reset. Bits in this register are set/cleared by writing into IOBusSetInt/IOBusClrInt respectively. The IntOut wire is asserted as long as this register is non-zero. This mechanism makes it possible to raise a single interrupt on the PC/AT bus and submultiplex it using the 8 information bits. The IOBusInt register is initialized to 0 by reset.
0E IOBusSetInt W Addresses 0D, 0E, and 0F are 3 different paths to the same physical register. The first path, 0D, is read only. The other 2 paths, 0E and 0F are write only. Because IOBusInt may not be written directly, an alternate path (0E) is used to set bits in IOBusInt to one. Writing into the IOBusSetInt register performs an OR of IOBusInt and IOBusSetInt: IOBusInt ← IOBusInt OR DataIOBusSetInt). Reading this registers returns random results.
   
0F IOBusClrInt  W Addresses 0D, 0E, and 0F are 3 different paths to the same physical register. The first path, 0D, is read only. The other 2 paths, 0E and 0F are write only. Because IOBusInt may not be written directly, an alternate path (0F) is used to set bits in IOBusInt to zero. Writing into the IOBusClrInt register performs a AND NOT of IOBusInt and IOBusClrInt, so that it sets to zero the bit positions of IOBusInt that are one in IOBusClrInt: IOBusInt ← IOBusInt AND NOT DataIOBusClrInt). Reading this registers returns random results. 
10-13 PBusErrData R (10 is LSB, 13 is MSB). This register contains the data that was being written when the cache returns an error.
14-17 PBusErrAddr R (14 is LSB, 17 is MSB). This register contains the address (after IOBridge translation) that was being written when the cache returns an error.
18 PBusErrCmd R This register contains the command that was being issued when the cache returns an error.
19 PBusFault RW This register will be non-zero whenever the cache has returned a fault. The low-order bit of the register is output by the IOBridge on the nITFault line. Writing into the register will clear the fault condition. The PBusFault register is initialized to 0 by reset.
1A-1B DynaBus ID RO (1A is LSB, 1B is MSB). This register contains the DynaBus DeviceID (setup through the DBus) of the IOBridge. The DynaBus DeviceID is 10 bits, zero-extended to 16 bits.
1C-1E Unused   Reads will return random values, writes will be ignored.
1F DynaBusStopCtl RW When writing into this register, the msb of data is stored in a flip-flop that drives the SStopOut DynaBus signal. When read, this register returns as msb the value of this flip-flop, and as next significant bit, the value of the SStopIn, DynaBus signal. The other 6 bits are ignored on writes and return 0 on reads.
20-3F Unused   Reads will return random values, writes will be ignored.
40-7F Small Map Access  Each entry of the small map uses 4 bytes of that space. Entry 0 is at 40 and entry 15 at 7C. For each entry, the LSB is at the lowest address and the MSB at the highest address. When writing, only the high-order 22 bits of data are taken in account. Thus, for example, byte 40 is never written. Those 22 bits specify the 22 high-order bits that will be output as PBus address when this entry is used. On reads, the 22 bits are returned as MSBs and the low-order 10 bits are returned as zeroes. The map is not initialized at Reset and must be initialized before accessing DynaBus memory through the IOBridge.
80H-BFH Large Map Access  Each entry of the large map uses 4 bytes of that space. Entry 0 is at 80 and entry 15 at BC. For each entry, the LSB is at the lowest address and the MSB at the highest address. When writing, only the high-order 14 bits of data are taken in account Thus, for example, bytes 80 and 81 are never written. Those 14 bits specify the 14 high-order bits that will be output as PBus address when this entry is used. On reads, the 14 bits are returned as MSBs and the low-order 18 bits are returned as zeroes. The map is not initialized at Reset and must be initialized before accessing DynaBus memory through through the IOBridge.
C0H-FFH Extra Map Access  Each entry of the extra map uses 4 bytes of that space. Entry 0 is at C0 and entry 15 at FC. For each entry, the LSB is at the lowest address and the MSB at the highest address. When writing, only the high-order 6 bits of data are taken in account Thus, for example, bytes C0, C1, and C2 are never written. Those 6 bits specify the 6 high-order bits that will be output as PBus address when this entry is used. On reads, the 6 bits are returned as MSBs and the low-order 26 bits are returned as zeroes. The map is not initialized at Reset and must be initialized before accessing DynaBus memory through the IOBridge.
4.3 DBus Parameterization
The IOBridge has 4 registers that may be initialized and/or read by the DBus. Their addresses (path numbers) are as follows:
0: Chip Identification
 16 bits, RO. Indicates the type and version of the IOBridge. With the current version (IOBNOV87A). This register should always read 0101000111000000, i.e. type 7 version 0.
1: DeviceID
 10 bits, R/W. Specifies the DynaBus Device ID for the IOBridge. Note that the DeviceNo, that is 4 low-order bits of the Device ID, should be different for all IOBridges, because the DeviceNo is also used to specify the IO address range to which the IOBridge responds.
2: AddINT
 5 bits, R/W. Specifies the register offset within the cache IO address space to which interrupts should be sent.
3: MHz
 6 bits, R/W. Indicates the division factor of the DynaBus clock used to provide the 1MHz signal that increments the timing registers. The number is in 2's complement format: 3FH specifies 1, 00H specifies 63.
5.0 Detailed Description of Each Pin
5.1 DynaBus Pins
The following table describes the DynaBus pins of the IOBridge:
Pin Name I/O Pin Description
RequestOut O 2 bits, indicates arbiter request code. The IOBridge behaves as a memory device on the DynaBus. The following values are used:
  00: No allocation
  01: Bus lock (FIFO close to overflow)
  11: 2-cycle bus request
SpareOut O 2 bits, driven to 0 when DataOut is driven, floated otherwise. Present only for compatibility
SStopOut O DynaBus synchronous stop request (stops arbitration). Driven according to the status of an internal FF loaded by the PC/AT bus. This line is normally used for bootstrap and debug only.
SharedOut O Always driven to 0. Present only for compatibility
OwnerOut O Always driven to 0. Present only for compatibility
HeaderCycleOut O Driven high when the header cycle of a packet is emitted on DataOut, driven low when data cycles are emitted on DataOut, floated when DataOut is floated.
ParityOut O Parity of DataOut. Not yet implemented, always driven to 0.
DataOut O 64-bit wide DynaBus data output. Floated except when Grant is assserted (with 1 cycle of pipeline delay)
Grant I Packet grant from the arbiter. Will be high for 2 or 5 cycles (as indicated by previous LongGrant). Data emission on DataOut starts on the next clcok edge.
HiPGrant I Ignored, present only for compatibility
LongGrant I Indication by arbiter that packet granted on the next clock edge will be for 2 cycles (low) or 5 cycles (high). Valid only on the cycle preceding the beginning of a new Grant.
SpareIn I 2 bits, ignored, present only for compatibility
SStopIn I Synchronous stop line from DynaBus. Buffered internally to be accessible from the PC/AT.
SharedIn I Ignored, present only for compatibility
OwnerIn I Ignored, present only for compatibility
HeaderCycleIn I Asserted (high) on header cycles coming from the DynaBus
ParityIn I Parity on DataIn. Not yet implemented.
DataIn I 64-bit wide DynaBus data input.
Clock I DynaBus clock input. This is also the basic clock used inside the IOBridge.
CkOut O Clock feedback output. Used to adjust the clock skew based on internal clock buffering delay.
5.2 DBus Pins
The following table describes the DBus pins of the IOBridge. The reader is referred to the DBus specification for details.
Pin Name I/O Pin Description
DSelect I DBus selection. This line is asserted (high) when the IOBridge should listen to the DBus.
DSerialOut O Data emitted serially on the DBus by the IOBridge. This line is floated except when DSelect is asserted.
DSerialIn I DBus serial input data and address
nDReset I System reset (active low)
nDFreeze I Ignored by IOBridge
DExecute I Not used by IOBridge
DAddress I When high, address bit is present on DSerialIn
DShiftCK I DBus shift clock
5.3 PC/AT Pins
The following table describes the PC/AT pins of the IOBridge. Unless otherwise specified, those pins use little endian bit-ordering (bit 0 is LSB).
Pin Name I/O Pin Description
PCLK I PC/AT bus clock. This clock is used to derive the timings on the PC/AT bus when the IOBridge is the bus master.
Reset I PC/AT bus reset. This signal resets the internal PC/AT related automata. It should always be asserted together with the DBus DReset and should be rescinded before it.
BAck I Acknowledge of PC/AT bus allocation. Asserted by PC/AT bus allocator after BReq has been asserted by the IOBridge. Signal should not be rescinded before BReq is rescinded.
BReq I Allocation request for PC/AT bus.
nFault I/O Input when IOBridge is PC/AT bus master (BAck high), output when IOBridge is PC/AT bus slave. When the IOBridge is master, the DynaBus transaction will return in error if nFault is asserted at the end of the PC/AT cycle. When the IOBridge is slave, nFault will be asserted if the request cannot be completed properly (DynaBus error detected by the cache).
nWRXnIOW I/O Input when IOBridge is PC/AT bus slave, output when IOBridge is PC/AT bus master. When the IOBridge is PC/AT bus master, nWRXnIOW is asserted to indicate an IOWrite cycle on the PC/AT bus. When the IOBridge is PC/AT bus slave, nWRXnIOW asserted means that an extended address memory write cycle is active (as nWRX, except that 32 bit addresses are used and nMemCS/nIOCS are ignored)
nRDXnIOR I/O Input when IOBridge is PC/AT bus slave, output when IOBridge is PC/AT bus master. When the IOBridge is PC/AT bus master, nRDXnIOR is asserted to indicate an IORead cycle on the PC/AT bus. When the IOBridge is PC/AT bus slave, nRDXnIOR asserted means that an extended address memory read cycle is active (as nRDX, except that 32 bit addresses are used and nMemCS/nIOCS are ignored)
nReady I/O Input when IOBridge is PC/AT bus master, output when IOBridge is PC/AT bus slave. When the IOBridge is PC/AT bus master, nReady prevents completion of the PC/AT bus cycle as long as it is active. When the IOBridge is PC/AT bus slave, nReady is asserted as long as the IOBridge has not provided/sampled the data on the PC/AT bus.
nIOCS I When active (low), indicates that nWR/nRD cycle is for access to IOBridge registers.
nMemCS I When active (low), indicates that nWR/nRD cycle is for access to DynaBus memory.
nWR I/O Input when IOBridge is PC/AT bus slave, output when IOBridge is PC/AT bus master. When the IOBridge is PC/AT bus master, nWR is asserted to indicate a memory write cycle on the PC/AT bus. When the IOBridge is PC/AT bus slave, nWR asserted means that a write cycle is active. The cycle is ignored if neither nMemCS or nIOCS is active.
nRD I/O Input when IOBridge is PC/AT bus slave, output when IOBridge is PC/AT bus master. When the IOBridge is PC/AT bus master, nRD is asserted to indicate a memory read cycle on the PC/AT bus. When the IOBridge is PC/AT bus slave, nWR asserted means that a read cycle is active. The cycle is ignored if neither nMemCS nor nIOCS is active.
nBHE I/O Input when IOBridge is PC/AT bus slave, output when IOBridge is PC/AT bus master. Indicates that data high order byte takes part in transaction (when low).
A31nDEN I/O Input when IOBridge is PC/AT bus slave, output when IOBridge is PC/AT bus master. When IOBridge is PC/AT bus master, asserted (low) when data transceivers should be enabled. When IOBridge is PC/AT bus slave, this signal is the extended address bit 31 (msb).
A30DTnR I/O Input when IOBridge is PC/AT bus slave, output when IOBridge is PC/AT bus master. When IOBridge is PC/AT bus master, asserted (low) when data transceivers should transmit towards the IOBridge. When IOBridge is PC/AT bus slave, this signal is the extended address bit 30 (next to msb).
A29nINTA I/O Input when IOBridge is PC/AT bus slave, output when IOBridge is PC/AT bus master. When IOBridge is PC/AT bus master, asserted (low) to acknowledge PC/AT bus interrupt when using 8259 interrupt controllers. When IOBridge is PC/AT bus slave, this signal is the extended address bit 29.
A28-A24 I 5 bits, extended address bits 28 to 24.
Address I/O 24 bits. Input when IOBridge is PC/AT bus slave, output when IOBridge is PC/AT bus master. Full PC/AT bus address.
DATA I/O 16 bits. Direction defined by master/slave and read/write in the obvious fashion. Represents the data bus of the PC/AT.
IntOut O Driven when the DynaBus requests an interrupt on the PC/AT bus.
INTR I Driven to indicate that an interrupt should be passed on to the DynaBus. Logical acknowledge provided by A29nINTA.
5.4 PBus Pins
The following table describes the PBus pins (interface to SmallCache) of the IOBridge. Refer to the Cache specification for details. Bit ordering is big endian (0 is MSB).
Pin Name I/O Pin Description
PData I/O 32-bit Data and address bus between IOBridge and SmallCache. Direction is out during PhA, in or out during PhB according to read/write command.
PhA O High to indicate address transfer from IOBridge to SmallCache.
PhB O High to indicate data transfer between IOBridge and SmallCache. PhA and PhB must be non-overlapping.
PReject I If high at end of PhB, retry cycle (wait state)
PFault I If high at end of PhB (PReject also high at same time), cycle has failed.
PCmd O 4-bit command.
PByteSel O 4-bit byte selection for writes (most significant bit enables most significant byte).
5.5 Miscellaneous Pins
The following table describes miscellaneous pins of the IOBridge.
Pin Name I/O Pin Description
Test I This signal is used to reduce the number of pins that need to be contacted for testing purposes. It relates only to the operation of the Dynabus Data lines. When de-asserted the DynabusIn and DynabusOut pins are uni-directional. When asserted, the DynabusIn pins become active outputs and drive the level currently on the DynabusOut pins.
Spare N.A. 3 unused pins (not connected on PGA).
6.0 DC Characteristics
This section lists the Direct Current characteristics of each signal. Pins are grouped when they have a common DC behavior.
Pin Name Signal Type Voltage  Current
Group Out 5V output L 0.5 2 ma
  H 4.0 0
Group TSOut 5V tri-state output L 0.5 2 ma
  H 4.0 0
Group In 5V input L 0.5 2 ma
  H 4.5 2 ma
Group InOut 5V input/output L 0.5 2 ma
  H 4.5 2 ma
Group D Unbuffered input L 0.5 2 ma
  H 4.5 2 ma
Pin Type Pin Name
Group Out BReq, CkOut, IntOut, OwnerOut, PByteSel, PCmd, PhA, PhB, RequestOut, SharedOut, SpareOut, SStopOut
Group TSOut DataOut, DSerialOut, HeaderCycleOut, ParityOut
Group In A28-A24, BAck, DAddress, DataIn, DExecute, DSelect, DSerialIn, DShiftCK, Grant, HeaderCycleIn, HiPGrant, INTR, LongGrant, nDFreeze, nDReset, nIOCS, nMemCS, OwnerIn, ParityIn, PCLK, PFault, PReject, Reset, SharedIn, SpareIn, SStopIn, Test
Group InOut A29nINTA, A30DTnR, A31nDEN, Address, DATA, nBHE, nFault, nRD, nRDXnIOR, nReady, nWR, nWRXnIOW, PData
Group D PCLK
7.0. AC Characteristics
A. Definitions
[Artwork node; type 'Artwork on' to command tool]
Figure 14: Input Signal Characteristics
Ts (setup time) = the mimimum time a signal must be stable before the rising edge of the clock.
Th (hold time) = the mimimum time a signal must be stable after the rising edge of the clock.
[Artwork node; type 'Artwork on' to command tool]
Figure 15: Output Signal Characteristics
Tcycle = the time interval between successive rising edges of the clock
Tpd (propagation delay) = the waiting time after the clock is high until an output becomes valid.
Tm (maintenance of old data) = the time after rising edge of next clock cycle that old data remains valid.
B. Values
Qualififed Pin Name Tmin Ttypical Tmax
Tcycle 20ns 25ns 27ns
Ts.Dynabus In (setup.Dynabus In)  3ns 
Th.Dynabus In (hold.Dynabus In)  1ns
Tpd.Dynabus Out (propagation delay.Dynabus Out)  5ns
Tm.Dynabus Out (maintain.Dynabus Out)  2ns
   
   
8.0 Application Schematics of the Circuit
[Artwork node; type 'Artwork on' to command tool]
9.0 Physical Pin-Out For Each Package
9.1 Physical die pin-out
This section indicates the pin-out of the IOBridge at the die level. In the following table, each colums describes a single side of the chip. Pads are numbered from left to right and top to bottom, from 1 to 67. The IOBridge uses the standard June87 padframe with signals pins on a single row inside and power supplies on the outside.
No Top No Bottom No Left No Right
1 DataIn[0] 1 DataIn[32] 1 Reset 1 HeaderCycleIn
2 DataOut[0] 2 DataOut[32] 2 nReady 2 HeaderCycleOut
3 DataIn[1] 3 DataIn[33] 3 nFault 3 OwnerIn
4 DataOut[1] 4 DataOut[33] 4 nWRXnIOW 4 OwnerOut
5 DataIn[2] 5 DataIn[34] 5 nRDXnIOR 5 SharedIn
6 DataOut[2] 6 DataOut[34] 6 nWR 6 SharedOut
7 DataIn[3] 7 DataIn[35] 7 nRD 7 SStopIn
8 DataOut[3] 8 DataOut[35] 8 nMemCS 8 SStopOut
9 DataIn[4] 9 DataIn[36] 9 nIOCS 9 Grant
10 DataOut[4] 10 DataOut[36] 10 nBHE 10 LongGrant
11 DataIn[5] 11 DataIn[37] 11 Address[23] 11 HiPGrant
12 DataOut[5] 12 DataOut[37] 12 Address[22] 12 RequestOut[1]
13 DataIn[6] 13 DataIn[38] 13 Address[21] 13 RequestOut[0]
14 DataOut[6] 14 DataOut[38] 14 Address[20] 14 DShiftCK
15 DataIn[7] 15 DataIn[39] 15 Address[19] 15 DAddress
16 DataOut[7] 16 DataOut[39] 16 Address[18] 16 DExecute
17 DataIn[8] 17 DataIn[40] 17 Address[17] 17 nDFreeze
18 DataOut[8] 18 DataOut[40] 18 Address[16] 18 nDReset
19 DataIn[9] 19 DataIn[41] 19 Address[15] 19 DSerialIn
20 DataOut[9] 20 DataOut[41] 20 Address[14] 20 DBusOut
21 DataIn[10] 21 DataIn[42] 21 Address[13] 21 DSelect
22 DataOut[10] 22 DataOut[42] 22 Address[12] 22 Clock
23 DataIn[11] 23 DataIn[43] 23 Address[11] 23 CkOut
24 DataOut[11] 24 DataOut[43] 24 Address[10] 24 PhA
25 DataIn[12] 25 DataIn[44] 25 Address[9] 25 PhB
26 DataOut[12] 26 DataOut[44] 26 Address[8] 26 PByteSel[3]
27 DataIn[13] 27 DataIn[45] 27 Address[7] 27 PByteSel[2]
28 DataOut[13] 28 DataOut[45] 28 Address[6] 28 PByteSel[1]
29 DataIn[14] 29 DataIn[46] 29 Address[5] 29 PByteSel[0]
30 DataOut[14] 30 DataOut[46] 30 Address[4] 30 PCmd[3]
31 DataIn[15] 31 DataIn[47] 31 Address[3] 31 PCmd[2]
32 DataOut[15] 32 DataOut[47] 32 Address[2] 32 PCmd[1]
33 DataIn[16] 33 DataIn[48] 33 Address[1] 33 PCmd[0]
34 DataOut[16] 34 DataOut[48] 34 Address[0] 34 PFault
35 DataIn[17] 35 DataIn[49] 35 A28-A24[4] 35 PReject
36 DataOut[17] 36 DataOut[49] 36 A28-A24[3] 36 PData[31]
37 DataIn[18] 37 DataIn[50] 37 A28-A24[2] 37 PData[30]
38 DataOut[18] 38 DataOut[50] 38 A28-A24[1] 38 PData[29]
39 DataIn[19] 39 DataIn[51] 39 A28-A24[0] 39 PData[28]
40 DataOut[19] 40 DataOut[51] 40 A29nINTA 40 PData[27]
41 DataIn[20] 41 DataIn[52] 41 A30DTnR 41 PData[26]
42 DataOut[20] 42 DataOut[52] 42 A31nDEN 42 PData[25]
43 DataIn[21] 43 DataIn[53] 43 DATA[15] 43 PData[24]
44 DataOut[21] 44 DataOut[53] 44 DATA[14] 44 PData[23]
45 DataIn[22] 45 DataIn[54] 45 DATA[13] 45 PData[22]
46 DataOut[22] 46 DataOut[54] 46 DATA[12] 46 PData[21]
47 DataIn[23] 47 DataIn[55] 47 DATA[11] 47 PData[20]
48 DataOut[23] 48 DataOut[55] 48 DATA[10] 48 PData[19]
49 DataIn[24] 49 DataIn[56] 49 DATA[9] 49 PData[18]
50 DataOut[24] 50 DataOut[56] 50 DATA[8] 50 PData[17]
51 DataIn[25] 51 DataIn[57] 51 DATA[7] 51 PData[16]
52 DataOut[25] 52 DataOut[57] 52 DATA[6] 52 PData[15]
53 DataIn[26] 53 DataIn[58] 53 DATA[5] 53 PData[14]
54 DataOut[26] 54 DataOut[58] 54 DATA[4] 54 PData[13]
55 DataIn[27] 55 DataIn[59] 55 DATA[3] 55 PData[12]
56 DataOut[27] 56 DataOut[59] 56 DATA[2] 56 PData[11]
57 DataIn[28] 57 DataIn[60] 57 DATA[1] 57 PData[10]
58 DataOut[28] 58 DataOut[60] 58 DATA[0] 58 PData[9]
59 DataIn[29] 59 DataIn[61] 59 PCLK 59 PData[8]
60 DataOut[29] 60 DataOut[61] 60 BAck 60 PData[7]
61 DataIn[30] 61 DataIn[62] 61 BReq 61 PData[6]
62 DataOut[30] 62 DataOut[62] 62 INTR 62 PData[5]
63 DataIn[31] 63 DataIn[63] 63 IntOut 63 PData[4]
64 DataOut[31] 64 DataOut[63] 64 Spare[2] 64 PData[3]
65 ParityIn 65 SpareIn[1] 65 Spare[1] 65 PData[2]
66 ParityOut 66 SpareOut[0] 66 Spare[0] 66 PData[1]
67 SpareIn[0] 67 SpareOut[1] 67 Test 67 PData[0]
Here is a diagram indicating the range of pins that are located on each side of the PGA:
[Artwork node; type 'Artwork on' to command tool]