Presentation of BIC Early 1988 1 Bus Interface Chip: BIC Decouples electrically the hybrid from the bus · Bit-sliced bidirectionnal register (24 bits) · Fast low-voltage drivers and receivers · Clock distribution and skew control · Reduces number of bus taps · DBus amplification and decoding, ... · Working prototype since August 1987 Block Diagram <<[Artwork node; type 'ArtworkInterpress on' to command tool]>> Pinout Mounted in a large PGA (cavity size) · Power: +5V, Gnd, separate Gnd for high-speed bus · Bias voltages: for data and clock 2V receivers · Clocks: 7 clock-related wires · Debug bus: DBus (8), DCS, DOEn, Name · DBus amplification: 3 pairs · Arbiter: 4 Grant wires and SStop · Dynabus: 24 data (I/O), 2 requests, 1 Or4 · Hybrid bus: 24 data (I/O), 2 requests, 4 Or4 Bit Slice Data in hybrid: two mono-directional buses · Data: 24 bits, bidir., grant, scan path · Request: 2 bits, out only, no grant, scan path · Or4: 1 bit, out only, no grant, no scan path <<[Artwork node; type 'ArtworkInterpress on' to command tool]>> · Hybrid layout explains the aspect ratio of BIC · Standard pad frame for slaves Grant Arbiter issues separate grants for slaves <<[Artwork node; type 'ArtworkInterpress on' to command tool]>> Debug Bus · Asynchronous bus Hybrid select -> chip select Address (access to address register) Reset, Freeze, Shift, Execute (step-by-step) DBusIn, DBusOut · Scan paths Chip ID [16]: pattern[4], type[6], version[6] Data path [52]: Internal Clock Skew register [4] External Clock Skew register [4] DBus distribution Decoding DBus address register -> Chip Select · 2 bits -> BIC itself + 3 slaves · Up to 12 slaves possible <<[Artwork node; type 'ArtworkInterpress on' to command tool]>> Clock Distribution Reference clock is carefully distributed · BIC adjusts its clock and one slave's clock · Adjustment done through DBus at power-up <<[Artwork node; type 'ArtworkInterpress on' to command tool]>> Skew control Completely digital logic; two copies / BIC · Maximum allowable skew: 1.7 ns · Variations on clock load, buffer size, temperature, supply voltage, processing · Processing variation is dominant · 16 taps, 0.7ns increment <<[Artwork node; type 'ArtworkInterpress on' to command tool]>> Layout Generation Layout through schematics annotations · Complete description by schematics · High-power latchup-resistant cells for drivers DIrect connection from/to pads Large transistors · Standard cells for control Status · First design Feb-May 1987, R. Bruce and L. Monier (part-time) Style: large high-power SC + regular SC · Status of BIC1 Tested August 1987 100% functional yield >> 50% used on hybrid prototypes expected 15ns min period on hybrid · Second design Specs drifted a tad Submitted December 1987