MapCache.rose
Last Edited by: Sindhu, March 6, 1985 11:33:14 pm PST
Imports Dragon;
MapCache: CELL [
Signal names obey the following convention: If a signal x is computed during PhA and remains valid throughout the following PhB, it is denoted as xAB. If x is computed during PhA and can change during the following PhB (as, for example, in precharged logic), it is denoted as xA. In this latter case, a client wanting to use x during PhB must receive it in his own latch open during PhA. xBA and xB are defined symmetrically. Positive logic is assumed (asserted = TRUE = 1 = more positive logic voltage); negative-logic signals have an extra "N" at or very near the beginning of the signal name (e.g., PNPError for PBus Negative-TRUE Parity Error).
Utilities interface
PhA, PhB<BOOL,
Vdd, Gnd<BOOL,
PadVdd, PadGnd<BOOL,
Reset<BOOL,
MBus interface
MDataBA=INT[32],
MCmdBA=EnumType["Dragon.MBusCommands"],
MGnt<BOOL,
Arbiter interface
MGntOR<BOOL,
Master<[0..32),
DBus interface
All the following signals change during PhA and propagate during the remainder of PhA and PhB, giving an entire clock cycle for them to propagate throughout the machine. Each user must receive them into a latch open during PhB. The effects of changes are intended to happen throughout the following PhA, PhB pair.
ResetAB<BOOL,
DHoldAB<BOOL, -- must be high before testing
DShiftAB<BOOL, -- shift the shift register by 1 bit if ~DNSelect
DExecuteAB<BOOL, -- interpret the content of the shift register if ~DNSelect
DNSelectAB<BOOL, -- if high, hold but don't Execute or Shift
DDataInAB<BOOL, -- sampled during each PhB following a PhB that DShift is asserted
DDataOutAB>BOOL -- changes during each PhA following a PhB that DShift is asserted, continues to be driven through the PhB following the PhA it changes
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