DIRECTORY Core, CoreBlock, CoreFrame, CoreInstCell, CoreLibrary, CoreName, CoreOps, HashTable, IFUCoreCells, IFUSrc, IO, Rope; IFUSrcStackBuf: CEDAR PROGRAM IMPORTS CoreBlock, CoreFrame, CoreInstCell, CoreLibrary, CoreName, CoreOps, HashTable, IFUCoreCells, IO, Rope EXPORTS IFUSrc = BEGIN ROPE: TYPE = Core.ROPE; pha: ROPE _ CoreName.RopeNm["PhA"]; phb: ROPE _ CoreName.RopeNm["PhB"]; notpha: ROPE _ CoreName.RopeNm["NotPhA"]; notphb: ROPE _ CoreName.RopeNm["NotPhB"]; vbb: ROPE _ CoreName.RopeNm["VBB"]; GND: ROPE _ CoreName.RopeNm["GND"]; VDD: ROPE _ CoreName.RopeNm["VDD"]; Signal: SIGNAL = CODE; StackBuf: PUBLIC PROC RETURNS[cellType: Core.CellType] = { name: ROPE _ CoreName.RopeNm["IFUStackBuf"]; IF (cellType _ CoreFrame.ReadFrameCache[name])=NIL THEN { cellType _ StackBufMain[name]; CoreFrame.WriteFrameCache[cellType]}}; StackBufMain: PROC [name: ROPE] RETURNS[cellType: Core.CellType] = { OPEN CL: CoreLibrary; Rename: CoreInstCell.RenameProc = {RETURN[TranslateGenericSignal[old, sec, row, byte, bit]]}; sec, row, byte, bit: INT _ 0; -- must be here for Rename library: CL.Library _ IFUCoreCells.library; genBit, genTop, genMid, genBot: Core.CellType; genBitV, genTopV, genMidV, genBotV: Core.CellType; frame, section, secRow: CoreFrame.Frame; generic: ARRAY [0..5) OF ARRAY [0..4) OF Core.CellType; genBit _ CL.Get[library, "DpStackBit", FALSE, LIST["Body" ]]; genBitV _ CL.Get[library, "DpStackBit", FALSE, LIST["Body", "ExtraVWire" ]]; genTop _ CL.Get[library, "DpStackBitTop", FALSE, LIST["Body" ]]; genTopV _ CL.Get[library, "DpStackBitTop", FALSE, LIST["Body", "ExtraVWire" ]]; genMid _ CL.Get[library, "DpStackBitSeparation", FALSE, LIST["Body" ]]; genMidV _ CL.Get[library, "DpStackBitSeparation", FALSE, LIST["Body", "ExtraVWire" ]]; genBot _ CL.Get[library, "DpStackBitBot", FALSE, LIST["Body" ]]; genBotV _ CL.Get[library, "DpStackBitBot", FALSE, LIST["Body", "ExtraVWire" ]]; generic[4] _ [genTopV, genTop, genTopV, genTopV]; generic[3] _ [genBitV, genBit, genBitV, genBitV]; generic[2] _ [genMidV, genMid, genMidV, genMidV]; generic[1] _ [genBitV, genBit, genBitV, genBitV]; generic[0] _ [genBotV, genBot, genBotV, genBotV]; cellType _ CoreFrame.NewFrameCell[5, name, [first: bottom]]; frame _ CoreFrame.FCT[cellType]; frame.seq[4] _ CoreFrame.NewFrameCell[1, "Top", [first: bottom]]; frame.seq[3] _ CoreFrame.NewFrameCell[16, "PC", [first: bottom]]; frame.seq[2] _ CoreFrame.NewFrameCell[1, "Mid", [first: bottom]]; frame.seq[1] _ CoreFrame.NewFrameCell[16, "Stat", [first: bottom]]; frame.seq[0] _ CoreFrame.NewFrameCell[1, "Bot", [first: bottom]]; FOR sec IN [0..5) DO section _ CoreFrame.FCT[frame.seq[sec]]; FOR row IN [0..section.seq.size) DO section.seq[row] _ CoreFrame.NewFrameCell[32, NIL, [first: left]]; secRow _ CoreFrame.FCT[section.seq[row]]; FOR phyI: INT IN [0..32) DO temp: Core.CellType; bit _ phyI / 4; byte _ phyI MOD 4; temp _ CoreInstCell.SpecificGeneric[generic[sec][byte], Rename]; secRow.seq[phyI] _ CoreFrame.NewFrameCell[0, NIL, [first: left, cell: temp] ]; ENDLOOP; ENDLOOP; ENDLOOP; frame.cell _ CoreFrame.RecastFrameHard[cellType]; frame.seq _ NEW[CoreFrame.FrameSeq[0]]; [ ] _ CoreOps.VisitWire[frame.cell.public, BlockRightStkSignals]}; BlockRightStkSignals: CoreOps.EachWireProc = { name: ROPE _ CoreName.WireNm[wire].n; IF Rope.Equal["Stk", Rope.Substr[name, 0, 3]] THEN [] _ CoreBlock.DelWireSide[wire, right]}; TranslateGenericSignal: PROC[aName: ROPE, sec, row, byte, bit: INT] RETURNS[ROPE]= { sig: Sig _ NARROW[HashTable.Fetch[xlateTable, aName].value]; IF sig = NIL THEN Signal[]; RETURN[ SELECT sig^ FROM hpass => hPasses[sec][row], rd => IO.PutFR["StkRdAc.%g", IO.int[row]], wt => IO.PutFR["StkLd%gAc.%g", IO.rope[secC[sec]], IO.int[row]], in => IO.PutFR["%gStackWtDataA.%g%g", IO.rope[secD[sec]], IO.int[byte], IO.int[bit]], out => IO.PutFR["Not%gStackRdDataA.%g%g", IO.rope[secD[sec]], IO.int[byte], IO.int[bit]], vpass0 => IO.PutFR["%g%01b", IO.rope[vPasses[0][byte]], IO.int[bit]], vpass1 => IO.PutFR["%g%01b", IO.rope[vPasses[1][byte]], IO.int[bit]], vdd => aName, gnd => aName, ENDCASE => ERROR]}; secC: ARRAY [0..5) OF ROPE = ["L", "L", "ERROR", "P", "P"]; secD: ARRAY [0..5) OF ROPE = ["Stat", "Stat", "ERROR", "PC", "PC"]; vPasses: ARRAY [0..2) OF ARRAY [0..4) OF ROPE =[ ["XBus.0", "XBus.1", "XBus.2", "XBus.3"], ["OpBA.", NIL, "AlphaBA.", "BetaBA."] ]; hPasses: ARRAY [0..5) OF ARRAY [0..16) OF ROPE =[ ALL[ NIL], [ "NextMacroGetBA", "NextMacroJumpBA", "NextMacroHoldBA", "ProtMicroCycleBA", "X1ASrcStackBA", "X1ADstStackBA", "XBusStackEldestBA", "XBusStackLBA", "InstReadyAB", "DShLeftOut", Dummy[], Dummy[], "DPFaultBA.0", "DPRejectBA", "Stage3ANormalBA", "EUCondition2BA" ], ALL[ NIL], [ Dummy[], Dummy[], Dummy[], Dummy[], Dummy[], Dummy[], Dummy[], Dummy[], Dummy[], Dummy[], Dummy[], vbb, pha, notpha, phb, notphb ], ALL[ NIL] ]; Dummy: PROC RETURNS[ROPE] = {RETURN[GND]}; Sig: TYPE = REF SigType; SigType: TYPE = {hpass, vpass0, vpass1, rd, wt, in, out, gnd, vdd}; xlateTable: HashTable.Table; InitXlateTable: PROC = { Store: PROC[refName: ROPE, sigType: SigType] = { refName _ CoreName.RopeNm[refName]; [] _ HashTable.Store[xlateTable, refName, NEW[SigType _ sigType]]}; xlateTable _ HashTable.Create[equal: HashTable.RopeEqual, hash: HashTable.HashRope]; Store[ "hPass", hpass]; Store[ "rd", rd]; Store[ "wt", wt]; Store[ "bus0", vpass0]; Store[ "bus1", vpass1]; Store[ "in0", in]; Store[ "out0", out]; Store[ "GND", gnd]; Store[ "VDD", vdd] }; InitXlateTable[]; END. ���¢��IFUSrcStackBuf.mesa Copyright c 1985 by Xerox Corporation. All rights reserved. Last Edited by Curry October 21, 1986 7:10:55 pm PDT It's just too painful to change the key name of the bottom section from 'L' to 'Stat' all the way back through the PLA's so this is the spot where it happens. Control signals refer to L and the data uses Stat. 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