DIRECTORY
RoseTypes, IFUStack, RoseCreate, Dragon, DragOpsCross, BitOps, IFUPLAStackControl, SwitchTypes, NumTypes;

IFUStackImpl: CEDAR PROGRAM
IMPORTS RoseCreate, BitOps, IFUPLAStackControl, NumTypes
EXPORTS IFUStack

= BEGIN OPEN
RoseTypes, IFUStack;



RegisterCells: PROC =
BEGIN
StackControl _ RoseCreate.RegisterCellType[name: "StackControl",
expandProc: NIL,
ioCreator: CreateStackControlIO, driveCreator: CreateStackControlDrive, initializer: InitializeStackControl,
evals: [EvalSimple: StackControlEvalSimple],
tests: LIST[],
ports: CreateStackControlPorts[]
];
StackPtrs _ RoseCreate.RegisterCellType[name: "StackPtrs",
expandProc: NIL,
ioCreator: CreateStackPtrsIO, driveCreator: CreateStackPtrsDrive, initializer: InitializeStackPtrs,
evals: [EvalSimple: StackPtrsEvalSimple],
tests: LIST[],
ports: CreateStackPtrsPorts[]
];
StackBuffer _ RoseCreate.RegisterCellType[name: "StackBuffer",
expandProc: NIL,
ioCreator: CreateStackBufferIO, driveCreator: CreateStackBufferDrive, initializer: InitializeStackBuffer,
evals: [EvalSimple: StackBufferEvalSimple],
tests: LIST[],
ports: CreateStackBufferPorts[]
];
Stack _ RoseCreate.RegisterCellType[name: "Stack",
expandProc: StackExpand,
ioCreator: CreateStackIO, driveCreator: CreateStackDrive, 
evals: [],
tests: LIST[],
ports: CreateStackPorts[]
];
END;
otherss: SymbolTable _ RoseCreate.GetOtherss["IFUStack.partsAssertions"];
StackControl: PUBLIC CellType;

CreateStackControlPorts: PROC RETURNS [ports: Ports] = {ports _ RoseCreate.PortsFromFile["IFUStack.StackControl.rosePorts"]};

StackControlSwitchIORef: TYPE = REF StackControlSwitchIORec;
StackControlSwitchIORec: TYPE = RECORD [
Push3BA: SwitchTypes.SwitchVal
,Pop3BA: SwitchTypes.SwitchVal
,X1ASrcStackBA: SwitchTypes.SwitchVal
,X1ADstStackBA: SwitchTypes.SwitchVal
,XBusStackEldestBA: SwitchTypes.SwitchVal
,XBusStackLBA: SwitchTypes.SwitchVal
,TosAB: PACKED ARRAY [0 .. 5) OF SwitchTypes.SwitchVal
,BosAB: PACKED ARRAY [0 .. 5) OF SwitchTypes.SwitchVal
,DifBA: PACKED ARRAY [0 .. 5) OF SwitchTypes.SwitchVal
,IStkNearlyFullBA: SwitchTypes.SwitchVal
,AdjTosA: SwitchTypes.SwitchVal
,AddendIsOnesA: SwitchTypes.SwitchVal
,CarryIsOneA: SwitchTypes.SwitchVal
,StkLdLAc: PACKED ARRAY [0 .. 16) OF SwitchTypes.SwitchVal
,StkLdPAc: PACKED ARRAY [0 .. 16) OF SwitchTypes.SwitchVal
,StkRdAc: PACKED ARRAY [0 .. 16) OF SwitchTypes.SwitchVal
,PhA: SwitchTypes.SwitchVal
,PhB: SwitchTypes.SwitchVal
];

StackControlSimpleIORef: TYPE = REF StackControlSimpleIORec;
StackControlSimpleIORec: TYPE = RECORD [
fill0: [0 .. 32767],
Push3BA: BOOLEAN
,fill1: [0 .. 32767],
Pop3BA: BOOLEAN
,fill2: [0 .. 32767],
X1ASrcStackBA: BOOLEAN
,fill3: [0 .. 32767],
X1ADstStackBA: BOOLEAN
,fill4: [0 .. 32767],
XBusStackEldestBA: BOOLEAN
,fill5: [0 .. 32767],
XBusStackLBA: BOOLEAN
,fill6: [0 .. 2047],
TosAB: [0..31]
,fill7: [0 .. 2047],
BosAB: [0..31]
,fill8: [0 .. 2047],
DifBA: [0..31]
,fill9: [0 .. 32767],
IStkNearlyFullBA: BOOLEAN
,fill10: [0 .. 32767],
AdjTosA: BOOLEAN
,fill11: [0 .. 32767],
AddendIsOnesA: BOOLEAN
,fill12: [0 .. 32767],
CarryIsOneA: BOOLEAN
,StkLdLAc: CARDINAL
,StkLdPAc: CARDINAL
,StkRdAc: CARDINAL
,fill16: [0 .. 32767],
PhA: BOOLEAN
,fill17: [0 .. 32767],
PhB: BOOLEAN
];

StackControlDriveRef: TYPE = REF StackControlDriveRec;
StackControlDriveRec: TYPE = RECORD [driveRecordInitialPadding: DriveTagType, drive: PACKED ARRAY StackControlPort OF DriveLevel];
StackControlPort: TYPE = {
Push3BA, Pop3BA, X1ASrcStackBA, X1ADstStackBA, XBusStackEldestBA, XBusStackLBA, TosAB, BosAB, DifBA, IStkNearlyFullBA, AdjTosA, AddendIsOnesA, CarryIsOneA, StkLdLAc, StkLdPAc, StkRdAc, PhA, PhB, StackControlPortTypePad18, StackControlPortTypePad19};

CreateStackControlIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = {
ioAsAny _ IF switch THEN NEW[StackControlSwitchIORec] ELSE NEW[StackControlSimpleIORec];
};

CreateStackControlDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = {
driveAsAny _ NEW[StackControlDriveRec];
};

StackControlStateRef: TYPE = REF StackControlStateRec;
StackControlStateRec: TYPE = RECORD [
stkLdPBA: IFUPLAStackControl.SixteenBits,
stkLdLBA: IFUPLAStackControl.SixteenBits,
stkRdBA: IFUPLAStackControl.SixteenBits

];

InitializeStackControl: Initializer = {
state: StackControlStateRef _ NEW[StackControlStateRec];
cell.realCellStuff.state _ state;
};

StackControlEvalSimple: SimpleEval =
BEGIN
drive: StackControlDriveRef _ NARROW[cell.realCellStuff.newDriveAsAny];
sw: StackControlSwitchIORef _ NARROW[cell.realCellStuff.switchIO];
newIO: StackControlSimpleIORef _ NARROW[cell.realCellStuff.newIO];
state: StackControlStateRef _ NARROW[cell.realCellStuff.state];
BEGIN OPEN drive, newIO, state;

IF PhA THEN {
[[
adjTos: AdjTosA,
addendIsOnes: AddendIsOnesA,
carryIsOne: CarryIsOneA
]] _ IFUPLAStackControl.StackAControlProc[[
diff: DifBA, -- unused
x1ASrcStack: X1ASrcStackBA,
x1ADstStack: X1ADstStackBA,
xBusStackEldest: XBusStackEldestBA,
xBusStackL: XBusStackLBA,
push3: Push3BA,
pop3: Pop3BA
]];
StkLdLAc _ stkLdLBA;
StkLdPAc _ stkLdPBA;
StkRdAc _ stkRdBA;
}
ELSE {StkLdLAc _ StkLdPAc _ StkRdAc _ 0};

IF PhB THEN {
[[
iStkNearlyFull: IStkNearlyFullBA
]] _ IFUPLAStackControl.StackBControlProc[[
diff: DifBA,
x1ASrcStack: X1ASrcStackBA, -- unused
x1ADstStack: X1ADstStackBA, -- unused
xBusStackEldest: XBusStackEldestBA, -- unused
xBusStackL: XBusStackLBA, -- unused
push3: Push3BA,
pop3: Pop3BA -- unused
]];

[[
stkLdP: stkLdPBA,
stkLdL: stkLdLBA,
stkRd: stkRdBA
]] _ IFUPLAStackControl.StackDecodeProc[[
tos: TosAB,
bos: BosAB,
diff: DifBA, -- unused
x1ASrcStack: X1ASrcStackBA,
x1ADstStack: X1ADstStackBA,
xBusStackEldest: XBusStackEldestBA,
xBusStackL: XBusStackLBA,
push3: Push3BA,
pop3: Pop3BA
]];
};

END;
END;
StackPtrs: PUBLIC CellType;

CreateStackPtrsPorts: PROC RETURNS [ports: Ports] = {ports _ RoseCreate.PortsFromFile["IFUStack.StackPtrs.rosePorts"]};

StackPtrsSwitchIORef: TYPE = REF StackPtrsSwitchIORec;
StackPtrsSwitchIORec: TYPE = RECORD [
AdjTosA: SwitchTypes.SwitchVal
,AddendIsOnesA: SwitchTypes.SwitchVal
,CarryIsOneA: SwitchTypes.SwitchVal
,TosAB: PACKED ARRAY [0 .. 5) OF SwitchTypes.SwitchVal
,BosAB: PACKED ARRAY [0 .. 5) OF SwitchTypes.SwitchVal
,DifBA: PACKED ARRAY [0 .. 5) OF SwitchTypes.SwitchVal
,ResetBA: SwitchTypes.SwitchVal
,PhA: SwitchTypes.SwitchVal
,PhB: SwitchTypes.SwitchVal
];

StackPtrsSimpleIORef: TYPE = REF StackPtrsSimpleIORec;
StackPtrsSimpleIORec: TYPE = RECORD [
fill0: [0 .. 32767],
AdjTosA: BOOLEAN
,fill1: [0 .. 32767],
AddendIsOnesA: BOOLEAN
,fill2: [0 .. 32767],
CarryIsOneA: BOOLEAN
,fill3: [0 .. 2047],
TosAB: [0..31]
,fill4: [0 .. 2047],
BosAB: [0..31]
,fill5: [0 .. 2047],
DifBA: [0..31]
,fill6: [0 .. 32767],
ResetBA: BOOLEAN
,fill7: [0 .. 32767],
PhA: BOOLEAN
,fill8: [0 .. 32767],
PhB: BOOLEAN
];

StackPtrsDriveRef: TYPE = REF StackPtrsDriveRec;
StackPtrsDriveRec: TYPE = RECORD [driveRecordInitialPadding: DriveTagType, drive: PACKED ARRAY StackPtrsPort OF DriveLevel];
StackPtrsPort: TYPE = {
AdjTosA, AddendIsOnesA, CarryIsOneA, TosAB, BosAB, DifBA, ResetBA, PhA, PhB, StackPtrsPortTypePad9, StackPtrsPortTypePad10, StackPtrsPortTypePad11};

CreateStackPtrsIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = {
ioAsAny _ IF switch THEN NEW[StackPtrsSwitchIORec] ELSE NEW[StackPtrsSimpleIORec];
};

CreateStackPtrsDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = {
driveAsAny _ NEW[StackPtrsDriveRec];
};

StackPtrsStateRef: TYPE = REF StackPtrsStateRec;
StackPtrsStateRec: TYPE = RECORD [
tosAB, tosBA: [0..32),
bosAB, bosBA: [0..32),
difBA: [0..32)
];

InitializeStackPtrs: Initializer = {
state: StackPtrsStateRef _ NEW[StackPtrsStateRec];
cell.realCellStuff.state _ state;
};

StackPtrsEvalSimple: SimpleEval =
BEGIN
drive: StackPtrsDriveRef _ NARROW[cell.realCellStuff.newDriveAsAny];
sw: StackPtrsSwitchIORef _ NARROW[cell.realCellStuff.switchIO];
newIO: StackPtrsSimpleIORef _ NARROW[cell.realCellStuff.newIO];
state: StackPtrsStateRef _ NARROW[cell.realCellStuff.state];
BEGIN OPEN drive, newIO, state;

IF PhA THEN {
adderMuxA: [0..32) = IF AdjTosA THEN tosBA ELSE bosBA;
addendA: [0..32) = IF AddendIsOnesA THEN 31 ELSE 0;
carryA: [0..1] = IF CarryIsOneA THEN 1 ELSE 0;
sumA: [0..32) = (adderMuxA+addendA+carryA) MOD 32;

TosAB _ tosAB _ SELECT TRUE FROM
ResetBA => 0,
AdjTosA => sumA,
ENDCASE => tosBA; -- needed because AdjTosA might glitch

BosAB _ bosAB _ SELECT TRUE FROM
ResetBA => 1,
NOT AdjTosA => sumA,
ENDCASE => bosBA; -- needed because AdjTosA might glitch
};

IF PhB THEN {
DifBA _ difBA _ (32+tosAB-bosAB) MOD 32;
tosBA _ tosAB;
bosBA _ bosAB;
};

END;
END;
StackBuffer: PUBLIC CellType;

CreateStackBufferPorts: PROC RETURNS [ports: Ports] = {ports _ RoseCreate.PortsFromFile["IFUStack.StackBuffer.rosePorts"]};

StackBufferSwitchIORef: TYPE = REF StackBufferSwitchIORec;
StackBufferSwitchIORec: TYPE = RECORD [
XBus: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,PCPipe3BA: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,PCStkTopAB: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,LPipe3BA: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,LStkTopAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,X1ASrcStackBA: SwitchTypes.SwitchVal
,X1ADstStackBA: SwitchTypes.SwitchVal
,XBusStackEldestBA: SwitchTypes.SwitchVal
,XBusStackLBA: SwitchTypes.SwitchVal
,StkRdAc: PACKED ARRAY [0 .. 16) OF SwitchTypes.SwitchVal
,StkLdLAc: PACKED ARRAY [0 .. 16) OF SwitchTypes.SwitchVal
,StkLdPAc: PACKED ARRAY [0 .. 16) OF SwitchTypes.SwitchVal
,Push3BA: SwitchTypes.SwitchVal
,PhA: SwitchTypes.SwitchVal
,PhB: SwitchTypes.SwitchVal
];

StackBufferSimpleIORef: TYPE = REF StackBufferSimpleIORec;
StackBufferSimpleIORec: TYPE = RECORD [
XBus: ARRAY [0..2) OF CARDINAL
,PCPipe3BA: ARRAY [0..2) OF CARDINAL
,PCStkTopAB: ARRAY [0..2) OF CARDINAL
,fill3: [0 .. 255],
LPipe3BA: [0..255]
,fill4: [0 .. 255],
LStkTopAB: [0..255]
,fill5: [0 .. 32767],
X1ASrcStackBA: BOOLEAN
,fill6: [0 .. 32767],
X1ADstStackBA: BOOLEAN
,fill7: [0 .. 32767],
XBusStackEldestBA: BOOLEAN
,fill8: [0 .. 32767],
XBusStackLBA: BOOLEAN
,StkRdAc: CARDINAL
,StkLdLAc: CARDINAL
,StkLdPAc: CARDINAL
,fill12: [0 .. 32767],
Push3BA: BOOLEAN
,fill13: [0 .. 32767],
PhA: BOOLEAN
,fill14: [0 .. 32767],
PhB: BOOLEAN
];

StackBufferDriveRef: TYPE = REF StackBufferDriveRec;
StackBufferDriveRec: TYPE = RECORD [driveRecordInitialPadding: DriveTagType, drive: PACKED ARRAY StackBufferPort OF DriveLevel];
StackBufferPort: TYPE = {
XBus, PCPipe3BA, PCStkTopAB, LPipe3BA, LStkTopAB, X1ASrcStackBA, X1ADstStackBA, XBusStackEldestBA, XBusStackLBA, StkRdAc, StkLdLAc, StkLdPAc, Push3BA, PhA, PhB, StackBufferPortTypePad15};

CreateStackBufferIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = {
ioAsAny _ IF switch THEN NEW[StackBufferSwitchIORec] ELSE NEW[StackBufferSimpleIORec];
};

CreateStackBufferDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = {
driveAsAny _ NEW[StackBufferDriveRec];
};

StackBufferStateRef: TYPE = REF StackBufferStateRec;
StackBufferStateRec: TYPE = RECORD [
pStack:					ARRAY [0..16) OF Dragon.HexWord,
pRdBufA, pWrtBufA:	Dragon.HexWord,
lStack:					ARRAY [0..16) OF Dragon.HexByte,
lRdBufA, lWrtBufA:	Dragon.HexByte


];

InitializeStackBuffer: Initializer = {
state: StackBufferStateRef _ NEW[StackBufferStateRec];
cell.realCellStuff.state _ state;
};

StackBufferEvalSimple: SimpleEval =
BEGIN
drive: StackBufferDriveRef _ NARROW[cell.realCellStuff.newDriveAsAny];
sw: StackBufferSwitchIORef _ NARROW[cell.realCellStuff.switchIO];
newIO: StackBufferSimpleIORef _ NARROW[cell.realCellStuff.newIO];
state: StackBufferStateRef _ NARROW[cell.realCellStuff.state];
BEGIN OPEN drive, newIO, state;

IF X1ADstStackBA THEN {
pWrtBufA _ BitOps.ELFD[XBus, 32, 0, 32];
lWrtBufA _ BitOps.ELFD[XBus, 32, 24, 8];
}
ELSE {
pWrtBufA _ BitOps.ELFD[PCPipe3BA, 32, 0, 32];
lWrtBufA _ LPipe3BA;
};

FOR index: NAT IN [0..16) DO
EB: PROC[w: BitOps.BitWord] RETURNS[BOOL] =
{TRUSTED{RETURN[LOOPHOLE[w, PACKED ARRAY [0..16) OF BOOL][index]]}};
IF EB[StkRdAc]	THEN {lRdBufA _ lStack[index]; pRdBufA _ pStack[index]};
IF EB[StkLdLAc] THEN lStack[index] _ lWrtBufA;
IF EB[StkLdPAc] THEN pStack[index] _ pWrtBufA;
ENDLOOP;

IF Push3BA THEN {pRdBufA _ pWrtBufA; lRdBufA _ lWrtBufA}; -- bypass

IF PhA AND X1ASrcStackBA THEN {
drive[XBus] _ drive;
XBus _ BitOps.ILID[(IF XBusStackLBA THEN lRdBufA ELSE pRdBufA), XBus, 32, 0, 32];
} ELSE drive[XBus] _ ignore;
IF PhA THEN {PCStkTopAB _ BitOps.ILID[pRdBufA, PCStkTopAB, 32, 0, 32]; LStkTopAB _ lRdBufA};

END;
END;
Stack: PUBLIC CellType;

CreateStackPorts: PROC RETURNS [ports: Ports] = {ports _ RoseCreate.PortsFromFile["IFUStack.Stack.rosePorts"]};

StackSwitchIORef: TYPE = REF StackSwitchIORec;
StackSwitchIORec: TYPE = RECORD [
XBus: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,PCPipe3BA: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,PCStkTopAB: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,LPipe3BA: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,LStkTopAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,LBusB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,Push3BA: SwitchTypes.SwitchVal
,Pop3BA: SwitchTypes.SwitchVal
,X1ASrcStackBA: SwitchTypes.SwitchVal
,X1ADstStackBA: SwitchTypes.SwitchVal
,XBusStackEldestBA: SwitchTypes.SwitchVal
,XBusStackLBA: SwitchTypes.SwitchVal
,IStkNearlyFullBA: SwitchTypes.SwitchVal
,ResetBA: SwitchTypes.SwitchVal
,PhA: SwitchTypes.SwitchVal
,PhB: SwitchTypes.SwitchVal
];

StackSimpleIORef: TYPE = REF StackSimpleIORec;
StackSimpleIORec: TYPE = RECORD [
XBus: ARRAY [0..2) OF CARDINAL
,PCPipe3BA: ARRAY [0..2) OF CARDINAL
,PCStkTopAB: ARRAY [0..2) OF CARDINAL
,fill3: [0 .. 255],
LPipe3BA: [0..255]
,fill4: [0 .. 255],
LStkTopAB: [0..255]
,fill5: [0 .. 255],
LBusB: [0..255]
,fill6: [0 .. 32767],
Push3BA: BOOLEAN
,fill7: [0 .. 32767],
Pop3BA: BOOLEAN
,fill8: [0 .. 32767],
X1ASrcStackBA: BOOLEAN
,fill9: [0 .. 32767],
X1ADstStackBA: BOOLEAN
,fill10: [0 .. 32767],
XBusStackEldestBA: BOOLEAN
,fill11: [0 .. 32767],
XBusStackLBA: BOOLEAN
,fill12: [0 .. 32767],
IStkNearlyFullBA: BOOLEAN
,fill13: [0 .. 32767],
ResetBA: BOOLEAN
,fill14: [0 .. 32767],
PhA: BOOLEAN
,fill15: [0 .. 32767],
PhB: BOOLEAN
];

StackDriveRef: TYPE = REF StackDriveRec;
StackDriveRec: TYPE = RECORD [driveRecordInitialPadding: DriveTagType, drive: PACKED ARRAY StackPort OF DriveLevel];
StackPort: TYPE = {
XBus, PCPipe3BA, PCStkTopAB, LPipe3BA, LStkTopAB, LBusB, Push3BA, Pop3BA, X1ASrcStackBA, X1ADstStackBA, XBusStackEldestBA, XBusStackLBA, IStkNearlyFullBA, ResetBA, PhA, PhB};

CreateStackIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = {
ioAsAny _ IF switch THEN NEW[StackSwitchIORec] ELSE NEW[StackSimpleIORec];
};

CreateStackDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = {
driveAsAny _ NEW[StackDriveRec];
};

StackExpand: PROC [thisCell: Cell, to: ExpansionReceiver] --ExpandProc-- = {
PrivateLookupNode: PROC [name: ROPE] RETURNS [node: Node] = {node _ RoseCreate.LookupNode[from: thisCell, path: LIST[name]]};
XBus: Node _ PrivateLookupNode["XBus"];
PCPipe3BA: Node _ PrivateLookupNode["PCPipe3BA"];
PCStkTopAB: Node _ PrivateLookupNode["PCStkTopAB"];
LPipe3BA: Node _ PrivateLookupNode["LPipe3BA"];
LStkTopAB: Node _ PrivateLookupNode["LStkTopAB"];
LBusB: Node _ PrivateLookupNode["LBusB"];
Push3BA: Node _ PrivateLookupNode["Push3BA"];
Pop3BA: Node _ PrivateLookupNode["Pop3BA"];
X1ASrcStackBA: Node _ PrivateLookupNode["X1ASrcStackBA"];
X1ADstStackBA: Node _ PrivateLookupNode["X1ADstStackBA"];
XBusStackEldestBA: Node _ PrivateLookupNode["XBusStackEldestBA"];
XBusStackLBA: Node _ PrivateLookupNode["XBusStackLBA"];
IStkNearlyFullBA: Node _ PrivateLookupNode["IStkNearlyFullBA"];
ResetBA: Node _ PrivateLookupNode["ResetBA"];
PhA: Node _ PrivateLookupNode["PhA"];
PhB: Node _ PrivateLookupNode["PhB"];
others: SymbolTable _ RoseCreate.GetOthers[otherss, "Stack"];
NodeCreateHack1: PROC [name: ROPE] RETURNS [node: Node] = {node _ to.class.NodeInstance[erInstance: to.instance, name: name, type: NumTypes.NumType[5], other: RoseCreate.GetOther[others, name]]};
DifBA: Node _ NodeCreateHack1["DifBA"];
NodeCreateHack2: PROC [name: ROPE] RETURNS [node: Node] = {node _ to.class.NodeInstance[erInstance: to.instance, name: name, type: NumTypes.boolType, other: RoseCreate.GetOther[others, name]]};
AdjTosA: Node _ NodeCreateHack2["AdjTosA"];
AddendIsOnesA: Node _ NodeCreateHack2["AddendIsOnesA"];
CarryIsOneA: Node _ NodeCreateHack2["CarryIsOneA"];
TosAB: Node _ NodeCreateHack1["TosAB"];
BosAB: Node _ NodeCreateHack1["BosAB"];
NodeCreateHack3: PROC [name: ROPE] RETURNS [node: Node] = {node _ to.class.NodeInstance[erInstance: to.instance, name: name, type: NumTypes.NumType[16], other: RoseCreate.GetOther[others, name]]};
StkLdPAc: Node _ NodeCreateHack3["StkLdPAc"];
StkLdLAc: Node _ NodeCreateHack3["StkLdLAc"];
StkRdAc: Node _ NodeCreateHack3["StkRdAc"];
[] _ to.class.CellInstance[erInstance: to.instance, instanceName: "stackControl", typeName: "StackControl", other: RoseCreate.GetOther[others, "stackControl"], interfaceNodes: ""];
[] _ to.class.CellInstance[erInstance: to.instance, instanceName: "stackPtrs", typeName: "StackPtrs", other: RoseCreate.GetOther[others, "stackPtrs"], interfaceNodes: ""];
[] _ to.class.CellInstance[erInstance: to.instance, instanceName: "stackBuffer", typeName: "StackBuffer", other: RoseCreate.GetOther[others, "stackBuffer"], interfaceNodes: ""];
};

RegisterCells[];

END.
îIFUStackImpl.Mesa
created by RoseTranslate 3.1.3 of September 5, 1985 12:14:34 pm PDT
created from IFUStack.Rose of March 11, 1986 11:50:41 am PST
created for McCreight.pa
created at March 11, 1986 11:51:40 am PST
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