DIRECTORY
RoseTypes, IFUMainControl, RoseCreate, Dragon, IFUPLAInstrDecode, IFUPLAMainControl, SwitchTypes;

IFUMainControlImpl: CEDAR PROGRAM
IMPORTS RoseCreate, IFUPLAMainControl
EXPORTS IFUMainControl

= BEGIN OPEN
RoseTypes, IFUMainControl;

PBusFaults: TYPE = Dragon.PBusFaults;
CondEffect: TYPE = IFUPLAMainControl.CondEffect;
MicroCycleNext: TYPE = IFUPLAInstrDecode.MicroCycleNext;
MicroExcptJmp: TYPE = IFUPLAMainControl.MicroExcptJmp;
ExceptionCode: TYPE = IFUPLAMainControl.ExceptionCode;


RegisterCells: PROC =
BEGIN
MainControl _ RoseCreate.RegisterCellType[name: "MainControl",
expandProc: NIL,
ioCreator: CreateMainControlIO, driveCreator: CreateMainControlDrive, initializer: InitializeMainControl,
evals: [EvalSimple: MainControlEvalSimple],
tests: LIST[],
ports: CreateMainControlPorts[]
];
MicroCycle _ RoseCreate.RegisterCellType[name: "MicroCycle",
expandProc: NIL,
ioCreator: CreateMicroCycleIO, driveCreator: CreateMicroCycleDrive, initializer: InitializeMicroCycle,
evals: [EvalSimple: MicroCycleEvalSimple],
tests: LIST[],
ports: CreateMicroCyclePorts[]
];
END;
otherss: SymbolTable _ RoseCreate.GetOtherss["IFUMainControl.partsAssertions"];
MainControl: PUBLIC CellType;

CreateMainControlPorts: PROC RETURNS [ports: Ports] = {ports _ RoseCreate.PortsFromFile["IFUMainControl.MainControl.rosePorts"]};

MainControlSwitchIORef: TYPE = REF MainControlSwitchIORec;
MainControlSwitchIORec: TYPE = RECORD [
ResetBA: SwitchTypes.SwitchVal
,DPRejectedBA: SwitchTypes.SwitchVal
,DPFaultB: PACKED ARRAY [0 .. 4) OF SwitchTypes.SwitchVal
,EUCondition2B: SwitchTypes.SwitchVal
,EUCondEffect1BA: PACKED ARRAY [0 .. 2) OF SwitchTypes.SwitchVal
,EUCondEffect2BA: PACKED ARRAY [0 .. 2) OF SwitchTypes.SwitchVal
,Stage1BHoldBA: SwitchTypes.SwitchVal
,InstStarting2BA: SwitchTypes.SwitchVal
,IPFaulted2BA: SwitchTypes.SwitchVal
,TrapsEnbled2BA: SwitchTypes.SwitchVal
,RschWaiting2BA: SwitchTypes.SwitchVal
,IStkNearlyFullBA: SwitchTypes.SwitchVal
,EStkOverflow2BA: SwitchTypes.SwitchVal
,Push2BA: SwitchTypes.SwitchVal
,MicroCycleAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,MicroCycleNextBA: PACKED ARRAY [0 .. 3) OF SwitchTypes.SwitchVal
,MicroExcptJmpAB: PACKED ARRAY [0 .. 4) OF SwitchTypes.SwitchVal
,ExceptionCodeAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,LoadStage1Ac: SwitchTypes.SwitchVal
,LoadStage1Bc: SwitchTypes.SwitchVal
,LoadStage2Ac: SwitchTypes.SwitchVal
,BubbleStage2A1BA: SwitchTypes.SwitchVal
,NormalStage2A1BA: SwitchTypes.SwitchVal
,AbortStage2B2AB: SwitchTypes.SwitchVal
,NormalStage2B2AB: SwitchTypes.SwitchVal
,LoadStage3Ac: SwitchTypes.SwitchVal
,AbortStage3A2BA: SwitchTypes.SwitchVal
,NormalStage3A2BA: SwitchTypes.SwitchVal
,PhA: SwitchTypes.SwitchVal
,PhB: SwitchTypes.SwitchVal
];

MainControlSimpleIORef: TYPE = REF MainControlSimpleIORec;
MainControlSimpleIORec: TYPE = RECORD [
fill0: [0 .. 32767],
ResetBA: BOOLEAN
,fill1: [0 .. 32767],
DPRejectedBA: BOOLEAN
,fill2: [0 .. 4095],
DPFaultB: PBusFaults
,fill3: [0 .. 32767],
EUCondition2B: BOOLEAN
,fill4: [0 .. 16383],
EUCondEffect1BA: CondEffect
,fill5: [0 .. 16383],
EUCondEffect2BA: CondEffect
,fill6: [0 .. 32767],
Stage1BHoldBA: BOOLEAN
,fill7: [0 .. 32767],
InstStarting2BA: BOOLEAN
,fill8: [0 .. 32767],
IPFaulted2BA: BOOLEAN
,fill9: [0 .. 32767],
TrapsEnbled2BA: BOOLEAN
,fill10: [0 .. 32767],
RschWaiting2BA: BOOLEAN
,fill11: [0 .. 32767],
IStkNearlyFullBA: BOOLEAN
,fill12: [0 .. 32767],
EStkOverflow2BA: BOOLEAN
,fill13: [0 .. 32767],
Push2BA: BOOLEAN
,fill14: [0 .. 255],
MicroCycleAB: [0..255]
,fill15: [0 .. 8191],
MicroCycleNextBA: MicroCycleNext
,fill16: [0 .. 4095],
MicroExcptJmpAB: MicroExcptJmp
,fill17: [0 .. 255],
ExceptionCodeAB: ExceptionCode
,fill18: [0 .. 32767],
LoadStage1Ac: BOOLEAN
,fill19: [0 .. 32767],
LoadStage1Bc: BOOLEAN
,fill20: [0 .. 32767],
LoadStage2Ac: BOOLEAN
,fill21: [0 .. 32767],
BubbleStage2A1BA: BOOLEAN
,fill22: [0 .. 32767],
NormalStage2A1BA: BOOLEAN
,fill23: [0 .. 32767],
AbortStage2B2AB: BOOLEAN
,fill24: [0 .. 32767],
NormalStage2B2AB: BOOLEAN
,fill25: [0 .. 32767],
LoadStage3Ac: BOOLEAN
,fill26: [0 .. 32767],
AbortStage3A2BA: BOOLEAN
,fill27: [0 .. 32767],
NormalStage3A2BA: BOOLEAN
,fill28: [0 .. 32767],
PhA: BOOLEAN
,fill29: [0 .. 32767],
PhB: BOOLEAN
];

MainControlDriveRef: TYPE = REF MainControlDriveRec;
MainControlDriveRec: TYPE = RECORD [driveRecordInitialPadding: DriveTagType, drive: PACKED ARRAY MainControlPort OF DriveLevel];
MainControlPort: TYPE = {
ResetBA, DPRejectedBA, DPFaultB, EUCondition2B, EUCondEffect1BA, EUCondEffect2BA, Stage1BHoldBA, InstStarting2BA, IPFaulted2BA, TrapsEnbled2BA, RschWaiting2BA, IStkNearlyFullBA, EStkOverflow2BA, Push2BA, MicroCycleAB, MicroCycleNextBA, MicroExcptJmpAB, ExceptionCodeAB, LoadStage1Ac, LoadStage1Bc, LoadStage2Ac, BubbleStage2A1BA, NormalStage2A1BA, AbortStage2B2AB, NormalStage2B2AB, LoadStage3Ac, AbortStage3A2BA, NormalStage3A2BA, PhA, PhB, MainControlPortTypePad30, MainControlPortTypePad31};

CreateMainControlIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = {
ioAsAny _ IF switch THEN NEW[MainControlSwitchIORec] ELSE NEW[MainControlSimpleIORec];
};

CreateMainControlDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = {
driveAsAny _ NEW[MainControlDriveRec];
};

MainControlStateRef: TYPE = REF MainControlStateRec;
MainControlStateRec: TYPE = RECORD [
wantNewMicro0AB, wantNewMicro0BA: BOOL,
stage1BHoldingAB: BOOL,
wereResetAB, wereResetBA: BOOL,
abortPipeAB, abortPipeBA: BOOL,
dpFaultedBA: BOOL,
euCondition2BA: BOOL,
stage2FailedBA: BOOL,
willBeProtMicroCycBA: BOOL

];

InitializeMainControl: Initializer = {
state: MainControlStateRef _ NEW[MainControlStateRec];
cell.realCellStuff.state _ state;
};

MainControlEvalSimple: SimpleEval =
BEGIN
drive: MainControlDriveRef _ NARROW[cell.realCellStuff.newDriveAsAny];
sw: MainControlSwitchIORef _ NARROW[cell.realCellStuff.switchIO];
newIO: MainControlSimpleIORef _ NARROW[cell.realCellStuff.newIO];
state: MainControlStateRef _ NARROW[cell.realCellStuff.state];
BEGIN OPEN drive, newIO, state;

IF PhA THEN {
[ [
abortPipe:				abortPipeAB,
microExcptJmp:		MicroExcptJmpAB,
exceptionCode:		ExceptionCodeAB
] ] _ IFUPLAMainControl.MainControlProc[ [
reseting:				ResetBA,
protMicroCyc:		willBeProtMicroCycBA,
dpFaulted:			dpFaultedBA,
dpRejected:			DPRejectedBA,
euCondition2:		euCondition2BA,
euCondEffect2:		EUCondEffect2BA,
stage1Hold:			Stage1BHoldBA,
condEffect1:			EUCondEffect1BA,
instStarting2:			InstStarting2BA,
ipFaulted2:			IPFaulted2BA,
trapsEnbled2:		TrapsEnbled2BA,
rschlWaiting2:		RschWaiting2BA,
eStkOverflow2:		EStkOverflow2BA,
iStkNearlyFull2:		IStkNearlyFullBA,
push2:				Push2BA
 ] ];

wantNewMicro0AB _ MicroExcptJmpAB # bubble;
stage1BHoldingAB _ EUCondEffect1BA # bubble AND (Stage1BHoldBA OR (DPRejectedBA -- AND Stage1BHoldIfRejectBA -- ));
wereResetAB	_ ResetBA;
};

IF PhB THEN {
wantNewMicro0BA _ wantNewMicro0AB;
dpFaultedBA _ DPFaultB # none;
euCondition2BA _ EUCondition2B;
wereResetBA _ wereResetAB;
abortPipeBA _ abortPipeAB;
willBeProtMicroCycBA _ MicroCycleAB>=112 AND (MicroCycleNextBA = next);
};

stage2FailedBA _ ResetBA
OR abortPipeBA
OR (EUCondEffect2BA=macroTrap AND euCondition2BA)
OR IPFaulted2BA
OR (TrapsEnbled2BA AND
(EStkOverflow2BA
OR (InstStarting2BA AND RschWaiting2BA)
OR (Push2BA AND IStkNearlyFullBA)
));

LoadStage1Ac _ PhA AND wantNewMicro0BA;
LoadStage1Bc _ PhB AND (NOT stage1BHoldingAB OR ResetBA);
LoadStage2Ac _ PhA AND (NOT (DPRejectedBA -- AND Stage1BHoldIfRejectBA -- ) OR ResetBA);
BubbleStage2A1BA _ Stage1BHoldBA OR stage2FailedBA;
NormalStage2A1BA _ NOT BubbleStage2A1BA;
AbortStage2B2AB _ abortPipeAB;
NormalStage2B2AB _ NOT AbortStage2B2AB;
LoadStage3Ac _ PhA AND (NOT DPRejectedBA OR ResetBA);
AbortStage3A2BA _ stage2FailedBA;
NormalStage3A2BA _ NOT AbortStage3A2BA;

END;
END;
MicroCycle: PUBLIC CellType;

CreateMicroCyclePorts: PROC RETURNS [ports: Ports] = {ports _ RoseCreate.PortsFromFile["IFUMainControl.MicroCycle.rosePorts"]};

MicroCycleSwitchIORef: TYPE = REF MicroCycleSwitchIORec;
MicroCycleSwitchIORec: TYPE = RECORD [
MicroCycleAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,MicroCycleNextBA: PACKED ARRAY [0 .. 3) OF SwitchTypes.SwitchVal
,MicroExcptJmpAB: PACKED ARRAY [0 .. 4) OF SwitchTypes.SwitchVal
,ExceptionCodeAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,PhA: SwitchTypes.SwitchVal
,PhB: SwitchTypes.SwitchVal
];

MicroCycleSimpleIORef: TYPE = REF MicroCycleSimpleIORec;
MicroCycleSimpleIORec: TYPE = RECORD [
fill0: [0 .. 255],
MicroCycleAB: [0..255]
,fill1: [0 .. 8191],
MicroCycleNextBA: MicroCycleNext
,fill2: [0 .. 4095],
MicroExcptJmpAB: MicroExcptJmp
,fill3: [0 .. 255],
ExceptionCodeAB: ExceptionCode
,fill4: [0 .. 32767],
PhA: BOOLEAN
,fill5: [0 .. 32767],
PhB: BOOLEAN
];

MicroCycleDriveRef: TYPE = REF MicroCycleDriveRec;
MicroCycleDriveRec: TYPE = RECORD [driveRecordInitialPadding: DriveTagType, drive: PACKED ARRAY MicroCyclePort OF DriveLevel];
MicroCyclePort: TYPE = {
MicroCycleAB, MicroCycleNextBA, MicroExcptJmpAB, ExceptionCodeAB, PhA, PhB, MicroCyclePortTypePad6, MicroCyclePortTypePad7};

CreateMicroCycleIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = {
ioAsAny _ IF switch THEN NEW[MicroCycleSwitchIORec] ELSE NEW[MicroCycleSimpleIORec];
};

CreateMicroCycleDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = {
driveAsAny _ NEW[MicroCycleDriveRec];
};

MicroCycleStateRef: TYPE = REF MicroCycleStateRec;
MicroCycleStateRec: TYPE = RECORD [
microCycleAB, microCycleBA: Dragon.HexByte
];

InitializeMicroCycle: Initializer = {
state: MicroCycleStateRef _ NEW[MicroCycleStateRec];
cell.realCellStuff.state _ state;
};

MicroCycleEvalSimple: SimpleEval =
BEGIN
drive: MicroCycleDriveRef _ NARROW[cell.realCellStuff.newDriveAsAny];
sw: MicroCycleSwitchIORef _ NARROW[cell.realCellStuff.switchIO];
newIO: MicroCycleSimpleIORef _ NARROW[cell.realCellStuff.newIO];
state: MicroCycleStateRef _ NARROW[cell.realCellStuff.state];
BEGIN OPEN drive, newIO, state;
IF PhA THEN {
microCycleAB _ microCycleBA;
MicroCycleAB _ SELECT MicroExcptJmpAB FROM
<microJump	=> microCycleBA,
microJump	=> 64,
ENDCASE	=> 112+4*(MicroExcptJmpAB.ORD-IFUPLAMainControl.MicroExcptJmp[bubble].ORD);
};
IF PhB THEN microCycleBA _ SELECT MicroCycleNextBA FROM
 clear			=> 0,
 hold 			=> microCycleAB,
 next			=> MicroCycleAB +1,
 ENDCASE	=> ERROR;
END;
END;

RegisterCells[];

END.

ZIFUMainControlImpl.Mesa
created by RoseTranslate 3.1.3 of September 5, 1985 12:14:34 pm PDT
created from IFUMainControl.Rose of February 13, 1986 6:37:31 pm PST
created for McCreight.pa
created at March 10, 1986 7:07:36 pm PST
Signal Type decls
stage1HoldIfReject:	Stage1BHoldIfRejectBA,
maybe we should break this out as a separate wire 
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