IFUInterlock.rose
Herrmann, September 12, 1985 10:43:29 am PDT
Curry, September 8, 1985 12:10:11 pm PDT
McCreight, February 27, 1986 2:21:36 pm PST
Copyright © 1984 by Xerox Corporation. All rights reserved.
Last edited by: McCreight, October 3, 1984 3:20:54 pm PDT
Last edited by: Curry, January 15, 1985 10:27:34 am PST
TranslationNeeds Dragon, IFUPLAInterlock;
Imports Basics, IFUPLAInterlock;
CELLTYPE "Interlock"
PORTS [
EUCondEffect2AB  < EnumType["IFUPLAMainControl.CondEffect"],
KIsRtOp1BA    < BOOL,
FCtlIsRtOp1BA   < BOOL,
C2IsFieldCtlAB   < BOOL,
C3IsFieldCtlAB   < BOOL,
DPCmndRd2BA   < BOOL,
DPCmndRd3BA   < BOOL,
ARegIsC2BA    < BOOL,
ARegIsC3BA    < BOOL,
BRegIsC2BA    < BOOL,
BRegIsC3BA    < BOOL,
Stage1BHoldBA   > BOOL,
Stage1BHoldIfRejectBA > BOOL,
EUAluLeftSrc1B   = EnumType["Dragon.ALULeftSources"],
EUAluRightSrc1B  = EnumType["Dragon.ALURightSources"],
EUStore2ASrc1B   = EnumType["Dragon.Store2ASources"],
EUSt3AisCBus1BA  > BOOL,
PhA     < BOOL,
PhB     < BOOL
]
EvalSimple
IF PhB THEN {
[ [
stage1BHold:   Stage1BHoldBA,
stage1BHoldIfReject: Stage1BHoldIfRejectBA,
aluLt:     EUAluLeftSrc1B,
aluRt:     EUAluRightSrc1B,
st2A:     EUStore2ASrc1B,
st3AIsCbus:   EUSt3AisCBus1BA
] ] ← IFUPLAInterlock.InterlockProc[ [
condEffect2:   EUCondEffect2AB,
kIsRtOp:    KIsRtOp1BA,
fCtlIsRtOp:   FCtlIsRtOp1BA,
c2IsFieldCtl:   C2IsFieldCtlAB,
c3IsFieldCtl:   C3IsFieldCtlAB,
dpCmndRd2:   DPCmndRd2BA,
dpCmndRd3:   DPCmndRd3BA,
a1IsC2:    ARegIsC2BA,
a1IsC3:    ARegIsC3BA,
b1IsC2:    BRegIsC2BA,
b1IsC3:    BRegIsC3BA ] ];
drive[EUAluLeftSrc1B] ← drive;
drive[EUAluRightSrc1B] ← drive;
drive[EUStore2ASrc1B] ← drive;
}
ELSE {
drive[EUAluLeftSrc1B] ← ignore;
drive[EUAluRightSrc1B] ← ignore;
drive[EUStore2ASrc1B] ← ignore};
ENDCELLTYPE;
CEDAR
PCmdBitsOn: PROC [pcmd: Dragon.PBusCommands, bits: [0..256) ] RETURNS [ BOOL ] =
{RETURN[Basics.BITAND[pcmd.ORD, bits] = bits]};
;
CELLTYPE "ControlPipe"
PORTS [
X2ASrcLit0BA  < BOOL,
X2ASrcLit1BA  > BOOL,
KIsRtOp0BA   < BOOL,
KIsRtOp1BA   > BOOL,
KPadsIn0BA   < BOOL,
KPadsIn3BA   > BOOL,
Push0BA    < BOOL,
Push2BA    > BOOL,
Push3BA    > BOOL,
Pop0BA    < BOOL,
Pop3BA    > BOOL,
PushPendingAB  > BOOL,
PopPendingAB  > BOOL,
FCtlIsRtOp0BA  < BOOL,
FCtlIsRtOp1BA  > BOOL,
C0IsFieldCtlBA  < BOOL,
C2IsFieldCtlAB  > BOOL,
C3IsFieldCtlAB  > BOOL,
CRegIsField3B  = BOOL, -- alias of XBus[24]
DPCmnd0BA   < EnumType["Dragon.PBusCommands"],
DPCmnd3A   > EnumType["Dragon.PBusCommands"],
EUWriteToPBus3AB > BOOL,
EURes3BisPBus3AB > BOOL,
DPCmndRd0BA  < BOOL,
DPCmndRd2BA  > BOOL,
DPCmndRd3BA  > BOOL,
EUCondSel0BA  < EnumType["Dragon.CondSelects"],
EUCondSel2AB  > EnumType["Dragon.CondSelects"],
EUCondSel3AB  > EnumType["Dragon.CondSelects"],
EUSt3AisCBus1BA < BOOL,
EUSt3AisCBus2BA > BOOL,
EUCondEffect0BA < EnumType["IFUPLAMainControl.CondEffect"],
EUCondEffect1BA > EnumType["IFUPLAMainControl.CondEffect"],
EUCondEffect2AB > EnumType["IFUPLAMainControl.CondEffect"],
EUCondEffect2BA > EnumType["IFUPLAMainControl.CondEffect"],
EStkOverflow1BA < BOOL,
EStkOverflow2BA > BOOL,
EUAluOp0BA  < EnumType["Dragon.ALUOps"],
EUAluOp2AB  > EnumType["Dragon.ALUOps"],
DPRejectedBA  < BOOL,
IPFaulted0BA  < BOOL,
IPFaulted2BA  > BOOL,
InstReadyAB   < BOOL,
InstStarting0BA  < BOOL,
InstStarting2BA  > BOOL,
LoadStage1Ac  < BOOL, -- Pipe Controls
LoadStage1Bc  < BOOL,
LoadStage2Ac  < BOOL,
BubbleStage2A1BA  < BOOL,
NormalStage2A1BA  < BOOL,
AbortStage2B2AB  < BOOL,
NormalStage2B2AB  < BOOL,
LoadStage3Ac  < BOOL,
AbortStage3A2BA  < BOOL,
NormalStage3A2BA  < BOOL,
MicroExcptJmpAB < EnumType["IFUPLAMainControl.MicroExcptJmp"],
PhA     < BOOL,
PhB     < BOOL
]
State
ctlPipe0BA: RECORD [
instReady:  BOOL
],
ctlPipe1AB: RECORD [
x2ASrcLit:  BOOL,
push:    BOOL,
pop:    BOOL,
kPadsIn:   BOOL,
dpCmnd:   Dragon.PBusCommands,
aluOp:   Dragon.ALUOps,
kIsRtOp:   BOOL,
condSel:   Dragon.CondSelects,
condEffect:  IFUPLAMainControl.CondEffect,
fCtlIsRtOp:   BOOL,
cBusIsFieldReg: BOOL,
res3BisPBus:  BOOL,
writeToPBus:  BOOL,
instFault:   BOOL,
firstMicro:  BOOL
],
ctlPipe1BA: RECORD [
x2ASrcLit:  BOOL,
push:    BOOL,
pop:    BOOL,
kPadsIn:   BOOL,
dpCmnd:   Dragon.PBusCommands,
aluOp:   Dragon.ALUOps,
kIsRtOp:   BOOL,
condSel:   Dragon.CondSelects,
condEffect:  IFUPLAMainControl.CondEffect,
fCtlIsRtOp:   BOOL,
cBusIsFieldReg: BOOL,
res3BisPBus:  BOOL,
writeToPBus:  BOOL,
instFault:   BOOL,
firstMicro:  BOOL
],
ctlPipe2AB: RECORD [
x2ASrcLit:  BOOL,
push:    BOOL,
pop:    BOOL,
kPadsIn:   BOOL,
dpCmnd:   Dragon.PBusCommands,
aluOp:   Dragon.ALUOps,
condSel:   Dragon.CondSelects,
condEffect:  IFUPLAMainControl.CondEffect,
cBusIsFieldReg: BOOL,
res3BisPBus:  BOOL,
writeToPBus:  BOOL,
eStkOverflow: BOOL,
st3AisCBus:  BOOL,
instFault:   BOOL,
firstMicro:  BOOL
],
ctlPipe2BA: RECORD [
push:    BOOL,
pop:    BOOL,
kPadsIn:   BOOL,
dpCmnd:   Dragon.PBusCommands,
condSel:   Dragon.CondSelects,
condEffect:  IFUPLAMainControl.CondEffect,
cBusIsFieldReg: BOOL,
res3BisPBus:  BOOL,
writeToPBus:  BOOL,
eStkOverflow: BOOL,
st3AisCBus:  BOOL,
instFault:   BOOL,
firstMicro:  BOOL
],
ctlPipe3AB: RECORD [
push:    BOOL,
pop:    BOOL,
kPadsIn:   BOOL,
dpCmnd:   Dragon.PBusCommands,
condSel:   Dragon.CondSelects,
cBusIsFieldReg: BOOL,
res3BisPBus:  BOOL,
writeToPBus:  BOOL
],
ctlPipe3BA: RECORD [
push:    BOOL,
pop:    BOOL,
kPadsIn:   BOOL,
cBusIsFieldReg: BOOL,
res3BisPBus:  BOOL
]
EvalSimple
Advance Pipeline
IF PhB THEN ctlPipe0BA ← [
instReady: InstReadyAB
];
IF LoadStage1Ac THEN ctlPipe1AB ← [
x2ASrcLit:  X2ASrcLit0BA,
push:    Push0BA,
pop:    Pop0BA,
kPadsIn:   KPadsIn0BA,
dpCmnd:   DPCmnd0BA,
aluOp:   EUAluOp0BA,
kIsRtOp:   KIsRtOp0BA,
condSel:   EUCondSel0BA,
condEffect:  EUCondEffect0BA,
fCtlIsRtOp:   FCtlIsRtOp0BA,
cBusIsFieldReg: C0IsFieldCtlBA,
res3BisPBus:  DPCmndRd0BA,
writeToPBus:  PCmdBitsOn[DPCmnd0BA, Dragon.wrt],
instFault:   IPFaulted0BA AND NOT ctlPipe0BA.instReady,
firstMicro:  InstStarting0BA
];
IF LoadStage1Bc THEN ctlPipe1BA ← [
x2ASrcLit:  ctlPipe1AB.x2ASrcLit,
push:    ctlPipe1AB.push,
pop:    ctlPipe1AB.pop,
kIsRtOp:   ctlPipe1AB.kIsRtOp,
dpCmnd:   ctlPipe1AB.dpCmnd,
aluOp:   ctlPipe1AB.aluOp,
kPadsIn:   ctlPipe1AB.kPadsIn,
condSel:   ctlPipe1AB.condSel,
condEffect:  ctlPipe1AB.condEffect,
fCtlIsRtOp:  ctlPipe1AB.fCtlIsRtOp,
cBusIsFieldReg: ctlPipe1AB.cBusIsFieldReg,
res3BisPBus:  ctlPipe1AB.res3BisPBus,
writeToPBus:  ctlPipe1AB.writeToPBus,
instFault:   ctlPipe1AB.instFault,
firstMicro:  ctlPipe1AB.firstMicro
];
IF LoadStage2Ac THEN ctlPipe2AB ← (SELECT TRUE FROM
NormalStage2A1BA => [
x2ASrcLit:  ctlPipe1BA.x2ASrcLit,
push:    ctlPipe1BA.push,
pop:    ctlPipe1BA.pop,
kPadsIn:   ctlPipe1BA.kPadsIn,
dpCmnd:   ctlPipe1BA.dpCmnd,
aluOp:   ctlPipe1BA.aluOp,
condSel:   ctlPipe1BA.condSel,
condEffect:  ctlPipe1BA.condEffect,
cBusIsFieldReg: ctlPipe1BA.cBusIsFieldReg,
res3BisPBus:  ctlPipe1BA.res3BisPBus,
writeToPBus:  ctlPipe1BA.writeToPBus,
eStkOverflow: EStkOverflow1BA,
st3AisCBus:  EUSt3AisCBus1BA,
instFault:   ctlPipe1BA.instFault,
firstMicro:  ctlPipe1BA.firstMicro
],
BubbleStage2A1BA => [
x2ASrcLit:  FALSE,
push:    FALSE,
pop:    FALSE,
kPadsIn:   FALSE,
dpCmnd:   NoOp,
aluOp:   Or,
condSel:   False,
condEffect:  bubble,
cBusIsFieldReg: FALSE,
res3BisPBus:  FALSE,
writeToPBus:  FALSE,
eStkOverflow: FALSE,
st3AisCBus:  FALSE,
instFault:   FALSE,
firstMicro:  FALSE
],
ENDCASE => ERROR);
IF PhB THEN ctlPipe2BA ← (SELECT TRUE FROM
NormalStage2B2AB =>
[
push:    ctlPipe2AB.push,
pop:    ctlPipe2AB.pop,
kPadsIn:   ctlPipe2AB.kPadsIn,
dpCmnd:   ctlPipe2AB.dpCmnd,
condSel:   ctlPipe2AB.condSel,
condEffect:  ctlPipe2AB.condEffect,
cBusIsFieldReg: ctlPipe2AB.cBusIsFieldReg,
res3BisPBus:  ctlPipe2AB.res3BisPBus,
writeToPBus:  ctlPipe2AB.writeToPBus,
eStkOverflow: ctlPipe2AB.eStkOverflow,
st3AisCBus:  ctlPipe2AB.st3AisCBus,
instFault:   ctlPipe2AB.instFault,
firstMicro:  ctlPipe2AB.firstMicro
],
AbortStage2B2AB => [
push:    FALSE,
pop:    FALSE,
kPadsIn:   FALSE,
dpCmnd:   NoOp,
condSel:   False,
condEffect:  bubble,
cBusIsFieldReg: FALSE,
res3BisPBus:  FALSE,
writeToPBus:  FALSE,
eStkOverflow: FALSE,
st3AisCBus:  FALSE,
instFault:   FALSE,
firstMicro:  FALSE
],
ENDCASE => ERROR);
IF LoadStage3Ac THEN ctlPipe3AB ← (SELECT TRUE FROM
NormalStage3A2BA => [
push:    ctlPipe2BA.push,
pop:    ctlPipe2BA.pop,
kPadsIn:   ctlPipe2BA.kPadsIn,
dpCmnd:   ctlPipe2BA.dpCmnd,
condSel:   ctlPipe2BA.condSel,
cBusIsFieldReg: ctlPipe2BA.cBusIsFieldReg,
res3BisPBus:  ctlPipe2BA.res3BisPBus,
writeToPBus:  ctlPipe2BA.writeToPBus
],
AbortStage3A2BA => [
push:    FALSE,
pop:    FALSE,
kPadsIn:   FALSE,
dpCmnd:   NoOp,
condSel:   ctlPipe2BA.condSel,
cBusIsFieldReg: FALSE,
res3BisPBus:  FALSE,
writeToPBus:  FALSE
],
ENDCASE => ERROR);
IF PhB THEN ctlPipe3BA ← [
push:    ctlPipe3AB.push OR (MicroExcptJmpAB = trap),
pop:    ctlPipe3AB.pop,
kPadsIn:   ctlPipe3AB.kPadsIn,
cBusIsFieldReg: ctlPipe3AB.cBusIsFieldReg,
res3BisPBus:  ctlPipe3AB.res3BisPBus
];
PushPendingAB ← ctlPipe1AB.push OR ctlPipe2AB.push OR ctlPipe3AB.push;
PopPendingAB ← ctlPipe1AB.pop OR ctlPipe2AB.pop OR ctlPipe3AB.pop;
Drive Outputs
KIsRtOp1BA    ← ctlPipe1BA.kIsRtOp;
FCtlIsRtOp1BA   ← ctlPipe1BA.fCtlIsRtOp;
EUCondEffect1BA  ← ctlPipe1BA.condEffect;
X2ASrcLit1BA   ← ctlPipe2AB.x2ASrcLit;
EUAluOp2AB   ← ctlPipe2AB.aluOp;
EUCondSel2AB   ← ctlPipe2AB.condSel;
EUCondEffect2AB  ← ctlPipe2AB.condEffect;
C2IsFieldCtlAB   ← ctlPipe2AB.cBusIsFieldReg;
DPCmndRd2BA   ← ctlPipe2BA.res3BisPBus;
Push2BA     ← ctlPipe2BA.push;
EUCondEffect2BA  ← ctlPipe2BA.condEffect;
EStkOverflow2BA  ← ctlPipe2BA.eStkOverflow;
EUSt3AisCBus2BA  ← ctlPipe2BA.st3AisCBus;
IPFaulted2BA   ← ctlPipe2BA.instFault;
InstStarting2BA   ← ctlPipe2BA.firstMicro;
EUCondSel3AB   ← ctlPipe3AB.condSel;
DPCmnd3A    ← IF DPRejectedBA THEN NoOp ELSE ctlPipe3AB.dpCmnd;
EURes3BisPBus3AB  ← ctlPipe3AB.res3BisPBus;
EUWriteToPBus3AB  ← ctlPipe3AB.writeToPBus;
C3IsFieldCtlAB   ← ctlPipe3AB.cBusIsFieldReg;
DPCmndRd3BA   ← ctlPipe3BA.res3BisPBus;
Push3BA     ← ctlPipe3BA.push;
Pop3BA     ← ctlPipe3BA.pop;
KPadsIn3BA    ← ctlPipe3BA.kPadsIn;
drive[CRegIsField3B] ← IF PhB THEN drive ELSE ignore;
CRegIsField3B   ← ctlPipe3BA.cBusIsFieldReg;
ENDCELLTYPE