IFUData3Impl.Mesa
created by RoseTranslate 3.1.3 of September 5, 1985 12:14:34 pm PDT
created from IFUData3.Rose of March 11, 1986 11:41:03 am PST
created for McCreight.pa
created at March 11, 1986 11:53:01 am PST
DIRECTORY
RoseTypes, IFUData3, RoseCreate, IFUPLAMainControl, DragOpsCross, IFUPLAInstrDecode, DragonRosemary, DragonRoseExtras, ClusterParams, LizardRosemary, Rope, IO, SwitchTypes, PrintTV, AMBridge, Dragon;
IFUData3Impl: CEDAR PROGRAM
IMPORTS RoseCreate, DragonRosemary, DragonRoseExtras, ClusterParams, LizardRosemary, Rope, IO, PrintTV, AMBridge
EXPORTS IFUData3
= BEGIN OPEN
RoseTypes, IFUData3;
Signal Type decls
ExceptionCode: TYPE = IFUPLAMainControl.ExceptionCode;
MicroCycleNext: TYPE = IFUPLAInstrDecode.MicroCycleNext;
PCBusSrc: TYPE = IFUPLAInstrDecode.PCBusSrc;
PBusCommands: TYPE = Dragon.PBusCommands;
PBusFaults: TYPE = Dragon.PBusFaults;
RegisterCells: PROC =
BEGIN
IFUStatus ← RoseCreate.RegisterCellType[name: "IFUStatus",
expandProc: NIL,
ioCreator: CreateIFUStatusIO, driveCreator: CreateIFUStatusDrive, initializer: InitializeIFUStatus,
evals: [EvalSimple: IFUStatusEvalSimple],
tests: LIST[],
ports: CreateIFUStatusPorts[]
];
KBusPads ← RoseCreate.RegisterCellType[name: "KBusPads",
expandProc: NIL,
ioCreator: CreateKBusPadsIO, driveCreator: CreateKBusPadsDrive,
evals: [EvalSimple: KBusPadsEvalSimple],
tests: LIST[],
ports: CreateKBusPadsPorts[]
];
Misc ← RoseCreate.RegisterCellType[name: "Misc",
expandProc: NIL,
ioCreator: CreateMiscIO, driveCreator: CreateMiscDrive,
evals: [EvalSimple: MiscEvalSimple],
tests: LIST[],
ports: CreateMiscPorts[]
];
END;
otherss: SymbolTable ← RoseCreate.GetOtherss["IFUData3.partsAssertions"];
explicitly requested CEDAR:
defaultStatus: DragOpsCross.IFUStatusRec = [
userMode: FALSE,
trapsEnabled: FALSE,
reschedule: FALSE];
IFUStatus: PUBLIC CellType;
CreateIFUStatusPorts: PROC RETURNS [ports: Ports] = {ports ← RoseCreate.PortsFromFile["IFUData3.IFUStatus.rosePorts"]};
IFUStatusSwitchIORef: TYPE = REF IFUStatusSwitchIORec;
IFUStatusSwitchIORec: TYPE = RECORD [
XBus: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,RescheduleBA: SwitchTypes.SwitchVal
,ClearTrapsEnbledBA: SwitchTypes.SwitchVal
,ClearUserModeBA: SwitchTypes.SwitchVal
,RschWaiting2BA: SwitchTypes.SwitchVal
,TrapsEnbled2BA: SwitchTypes.SwitchVal
,UserMode0AB: SwitchTypes.SwitchVal
,LoadStage1Ac: SwitchTypes.SwitchVal
,LoadStage1Bc: SwitchTypes.SwitchVal
,LoadStage2Ac: SwitchTypes.SwitchVal
,LoadStage3Ac: SwitchTypes.SwitchVal
,X2ASrcStatusBA: SwitchTypes.SwitchVal
,X1ADstStatusBA: SwitchTypes.SwitchVal
,PhA: SwitchTypes.SwitchVal
,PhB: SwitchTypes.SwitchVal
];
IFUStatusSimpleIORef: TYPE = REF IFUStatusSimpleIORec;
IFUStatusSimpleIORec: TYPE = RECORD [
XBus: ARRAY [0..2) OF CARDINAL
,fill1: [0 .. 32767],
RescheduleBA: BOOLEAN
,fill2: [0 .. 32767],
ClearTrapsEnbledBA: BOOLEAN
,fill3: [0 .. 32767],
ClearUserModeBA: BOOLEAN
,fill4: [0 .. 32767],
RschWaiting2BA: BOOLEAN
,fill5: [0 .. 32767],
TrapsEnbled2BA: BOOLEAN
,fill6: [0 .. 32767],
UserMode0AB: BOOLEAN
,fill7: [0 .. 32767],
LoadStage1Ac: BOOLEAN
,fill8: [0 .. 32767],
LoadStage1Bc: BOOLEAN
,fill9: [0 .. 32767],
LoadStage2Ac: BOOLEAN
,fill10: [0 .. 32767],
LoadStage3Ac: BOOLEAN
,fill11: [0 .. 32767],
X2ASrcStatusBA: BOOLEAN
,fill12: [0 .. 32767],
X1ADstStatusBA: BOOLEAN
,fill13: [0 .. 32767],
PhA: BOOLEAN
,fill14: [0 .. 32767],
PhB: BOOLEAN
];
IFUStatusDriveRef: TYPE = REF IFUStatusDriveRec;
IFUStatusDriveRec: TYPE = RECORD [driveRecordInitialPadding: DriveTagType, drive: PACKED ARRAY IFUStatusPort OF DriveLevel];
IFUStatusPort: TYPE = {
XBus, RescheduleBA, ClearTrapsEnbledBA, ClearUserModeBA, RschWaiting2BA, TrapsEnbled2BA, UserMode0AB, LoadStage1Ac, LoadStage1Bc, LoadStage2Ac, LoadStage3Ac, X2ASrcStatusBA, X1ADstStatusBA, PhA, PhB, IFUStatusPortTypePad15};
CreateIFUStatusIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = {
ioAsAny ← IF switch THEN NEW[IFUStatusSwitchIORec] ELSE NEW[IFUStatusSimpleIORec];
};
CreateIFUStatusDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = {
driveAsAny ← NEW[IFUStatusDriveRec];
};
IFUStatusStateRef: TYPE = REF IFUStatusStateRec;
IFUStatusStateRec: TYPE = RECORD [
status: ARRAY Dragon.Phase OF DragOpsCross.IFUStatusRec,
rsPipe: ARRAY Dragon.Phase OF BOOL,
x2ASrcStatus: ARRAY Dragon.Phase OF BOOL,
statPipe: ARRAY Dragon.Phase OF DragOpsCross.IFUStatusRec
];
InitializeIFUStatus: Initializer = {
state: IFUStatusStateRef ← NEW[IFUStatusStateRec];
cell.realCellStuff.state ← state;
};
IFUStatusEvalSimple: SimpleEval =
BEGIN
drive: IFUStatusDriveRef ← NARROW[cell.realCellStuff.newDriveAsAny];
sw: IFUStatusSwitchIORef ← NARROW[cell.realCellStuff.switchIO];
newIO: IFUStatusSimpleIORef ← NARROW[cell.realCellStuff.newIO];
state: IFUStatusStateRef ← NARROW[cell.realCellStuff.state];
BEGIN OPEN drive, newIO, state;
IF PhA THEN {
newstatusRec: DragOpsCross.IFUStatusRec ← LOOPHOLE[XBus];
rsPipe[a] ← RescheduleBA;
status[a] ← [rescheduleKeep: TRUE];
status[a].reschedule ← (NOT X1ADstStatusBA AND status[b].reschedule)
OR (X1ADstStatusBA AND newstatusRec.rescheduleKeep AND status[b].reschedule)
OR (X1ADstStatusBA AND NOT newstatusRec.rescheduleKeep AND newstatusRec.reschedule)
OR (RescheduleBA AND NOT rsPipe[b]);
status[a].userMode ← (NOT ClearUserModeBA AND NOT X1ADstStatusBA AND status[b].userMode)
OR (NOT ClearUserModeBA AND X1ADstStatusBA AND newstatusRec.userModeKeep AND status[b].userMode)
OR (NOT ClearUserModeBA AND X1ADstStatusBA AND NOT newstatusRec.userModeKeep AND newstatusRec.userMode);
status[a].trapsEnabled ← (NOT ClearTrapsEnbledBA AND NOT X1ADstStatusBA AND status[b].trapsEnabled)
OR (NOT ClearTrapsEnbledBA AND X1ADstStatusBA AND newstatusRec.trapsEnabledKeep AND status[b].trapsEnabled)
OR (NOT ClearTrapsEnbledBA AND X1ADstStatusBA AND NOT newstatusRec.trapsEnabledKeep AND newstatusRec.trapsEnabled);
};
IF PhB THEN {
status[b] ← status[a];
rsPipe[b] ← rsPipe[a];
};
Pipe
IF LoadStage1Ac THEN {x2ASrcStatus[a] ← X2ASrcStatusBA; statPipe[a] ← status[b]};
IF LoadStage1Bc THEN {x2ASrcStatus[b] ← x2ASrcStatus[a]; statPipe[b] ← statPipe[a]};
IF PhA AND x2ASrcStatus[b] THEN {
drive[XBus] ← drive;
XBus ← LOOPHOLE[statPipe[b]];
}
ELSE drive[XBus] ← ignore;
UserMode0AB  ← status[a].userMode;
RschWaiting2BA ← status[b].reschedule AND NOT X1ADstStatusBA; -- just in case
TrapsEnbled2BA  ← status[b].trapsEnabled AND NOT ClearTrapsEnbledBA;
END;
END;
KBusPads: PUBLIC CellType;
CreateKBusPadsPorts: PROC RETURNS [ports: Ports] = {ports ← RoseCreate.PortsFromFile["IFUData3.KBusPads.rosePorts"]};
KBusPadsSwitchIORef: TYPE = REF KBusPadsSwitchIORec;
KBusPadsSwitchIORec: TYPE = RECORD [
KBus: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,XBus: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,KPadsIn3BA: SwitchTypes.SwitchVal
,PhA: SwitchTypes.SwitchVal
,PhB: SwitchTypes.SwitchVal
];
KBusPadsSimpleIORef: TYPE = REF KBusPadsSimpleIORec;
KBusPadsSimpleIORec: TYPE = RECORD [
KBus: ARRAY [0..2) OF CARDINAL
,XBus: ARRAY [0..2) OF CARDINAL
,fill2: [0 .. 32767],
KPadsIn3BA: BOOLEAN
,fill3: [0 .. 32767],
PhA: BOOLEAN
,fill4: [0 .. 32767],
PhB: BOOLEAN
];
KBusPadsDriveRef: TYPE = REF KBusPadsDriveRec;
KBusPadsDriveRec: TYPE = RECORD [driveRecordInitialPadding: DriveTagType, drive: PACKED ARRAY KBusPadsPort OF DriveLevel];
KBusPadsPort: TYPE = {
KBus, XBus, KPadsIn3BA, PhA, PhB, KBusPadsPortTypePad5, KBusPadsPortTypePad6, KBusPadsPortTypePad7};
CreateKBusPadsIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = {
ioAsAny ← IF switch THEN NEW[KBusPadsSwitchIORec] ELSE NEW[KBusPadsSimpleIORec];
};
CreateKBusPadsDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = {
driveAsAny ← NEW[KBusPadsDriveRec];
};
KBusPadsEvalSimple: SimpleEval =
BEGIN
drive: KBusPadsDriveRef ← NARROW[cell.realCellStuff.newDriveAsAny];
sw: KBusPadsSwitchIORef ← NARROW[cell.realCellStuff.switchIO];
newIO: KBusPadsSimpleIORef ← NARROW[cell.realCellStuff.newIO];
BEGIN OPEN drive, newIO;
SELECT TRUE FROM
PhB =>
{drive[KBus] ← drive; drive[XBus] ← ignore; KBus ← XBus};
PhA AND NOT KPadsIn3BA =>
{drive[KBus] ← drive; drive[XBus] ← ignore; KBus ← XBus};
PhA -- AND KPadsIn3BA AND NOT PhB -- =>
{drive[KBus] ← ignore; drive[XBus] ← drive; XBus ← KBus};
ENDCASE -- NOT PhA AND NOT PhB -- =>
{drive[KBus] ← drive[XBus] ← ignore};
END;
END;
Misc: PUBLIC CellType;
CreateMiscPorts: PROC RETURNS [ports: Ports] = {ports ← RoseCreate.PortsFromFile["IFUData3.Misc.rosePorts"]};
MiscSwitchIORef: TYPE = REF MiscSwitchIORec;
MiscSwitchIORec: TYPE = RECORD [
ResetAB: SwitchTypes.SwitchVal
,ResetBA: SwitchTypes.SwitchVal
,RescheduleAB: SwitchTypes.SwitchVal
,RescheduleBA: SwitchTypes.SwitchVal
,DHoldAB: SwitchTypes.SwitchVal
,DHold0BA: SwitchTypes.SwitchVal
,DHold1AB: SwitchTypes.SwitchVal
,DPRejectB: SwitchTypes.SwitchVal
,DPRejectedBA: SwitchTypes.SwitchVal
,PhA: SwitchTypes.SwitchVal
,PhB: SwitchTypes.SwitchVal
];
MiscSimpleIORef: TYPE = REF MiscSimpleIORec;
MiscSimpleIORec: TYPE = RECORD [
fill0: [0 .. 32767],
ResetAB: BOOLEAN
,fill1: [0 .. 32767],
ResetBA: BOOLEAN
,fill2: [0 .. 32767],
RescheduleAB: BOOLEAN
,fill3: [0 .. 32767],
RescheduleBA: BOOLEAN
,fill4: [0 .. 32767],
DHoldAB: BOOLEAN
,fill5: [0 .. 32767],
DHold0BA: BOOLEAN
,fill6: [0 .. 32767],
DHold1AB: BOOLEAN
,fill7: [0 .. 32767],
DPRejectB: BOOLEAN
,fill8: [0 .. 32767],
DPRejectedBA: BOOLEAN
,fill9: [0 .. 32767],
PhA: BOOLEAN
,fill10: [0 .. 32767],
PhB: BOOLEAN
];
MiscDriveRef: TYPE = REF MiscDriveRec;
MiscDriveRec: TYPE = RECORD [driveRecordInitialPadding: DriveTagType, drive: PACKED ARRAY MiscPort OF DriveLevel];
MiscPort: TYPE = {
ResetAB, ResetBA, RescheduleAB, RescheduleBA, DHoldAB, DHold0BA, DHold1AB, DPRejectB, DPRejectedBA, PhA, PhB, MiscPortTypePad11};
CreateMiscIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = {
ioAsAny ← IF switch THEN NEW[MiscSwitchIORec] ELSE NEW[MiscSimpleIORec];
};
CreateMiscDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = {
driveAsAny ← NEW[MiscDriveRec];
};
MiscEvalSimple: SimpleEval =
BEGIN
drive: MiscDriveRef ← NARROW[cell.realCellStuff.newDriveAsAny];
sw: MiscSwitchIORef ← NARROW[cell.realCellStuff.switchIO];
newIO: MiscSimpleIORef ← NARROW[cell.realCellStuff.newIO];
BEGIN OPEN drive, newIO;
IF PhA THEN {DHold1AB  ← DHold0BA};
IF PhB THEN {
DHold0BA ← DHoldAB;
ResetBA ← ResetAB;
RescheduleBA ← RescheduleAB;
DPRejectedBA ← DPRejectB;
};
END;
END;
explicitly requested CEDAR:
MicroInstDisposition: TYPE = {unready, valid, interlocked, killed2b, killed3a, killed3b};
LogPipeState: TYPE = RECORD [
pc: Dragon.HexWord,
op: DragOpsCross.Inst ← x374B,
alpha, beta, gamma, delta: Dragon.HexByte ← 0,
microCyc: NAT ← 0,
disposition: MicroInstDisposition ← unready
];
OldIFULogger: TYPE = RECORD [args: IFULoggerArgs, ct: CellType];
oldIFULogger: LIST OF OldIFULogger ← NIL;
IFULogger: PUBLIC PROC [args: IFULoggerArgs] RETURNS [ct: CellType]
= BEGIN
FOR old: LIST OF OldIFULogger ← oldIFULogger, old.rest WHILE old # NIL DO
IF old.first.args = args THEN RETURN [old.first.ct]
ENDLOOP;
ct ← RoseCreate.RegisterCellType[name: IFULoggerName[args],
expandProc: NIL,
ioCreator: CreateIFULoggerIO, driveCreator: CreateIFULoggerDrive, initializer: InitializeIFULogger,
evals: [EvalSimple: IFULoggerEvalSimple],
tests: LIST[],
ports: CreateIFULoggerPorts[args]
,
typeData: NEW [IFULoggerArgs ← args]];
oldIFULogger ← CONS[[args, ct], oldIFULogger];
END;
IFULoggerName: PROC [args: IFULoggerArgs] RETURNS [name: ROPE] = {
to: IO.STREAM ← IO.ROS[]; to.PutRope["IFULogger"];
TRUSTED {PrintTV.Print[tv: AMBridge.TVForReferent[NEW [IFULoggerArgs ← args]], put: to, depth: 2]};
name ← IO.RopeFromROS[to]};
CreateIFULoggerPorts: PROC [args: IFULoggerArgs] RETURNS [ports: Ports] = {ports ← RoseCreate.PortsFromFile["IFUData3.IFULogger.rosePorts"]};
IFULoggerSwitchIORef: TYPE = REF IFULoggerSwitchIORec;
IFULoggerSwitchIORec: TYPE = RECORD [
XBus: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,DPRejectedBA: SwitchTypes.SwitchVal
,OpAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,AlphaAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,BetaAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,GammaAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,DeltaAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,OpLengthBA: PACKED ARRAY [0 .. 3) OF SwitchTypes.SwitchVal
,InstReadyAB: SwitchTypes.SwitchVal
,ExceptionCodeAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,MicroCycleAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,MicroCycleNextBA: PACKED ARRAY [0 .. 3) OF SwitchTypes.SwitchVal
,MacroJumpBA: SwitchTypes.SwitchVal
,PCBusSrcB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,PCForLogAB: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,LAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,SAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,AReg0BA: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,BReg0BA: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,CReg0BA: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,DPCmnd3A: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,DPData: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,DPRejectB: SwitchTypes.SwitchVal
,DPFaultB: PACKED ARRAY [0 .. 4) OF SwitchTypes.SwitchVal
,LoadStage1Ac: SwitchTypes.SwitchVal
,LoadStage1Bc: SwitchTypes.SwitchVal
,LoadStage2Ac: SwitchTypes.SwitchVal
,BubbleStage2A1BA: SwitchTypes.SwitchVal
,NormalStage2A1BA: SwitchTypes.SwitchVal
,AbortStage2B2AB: SwitchTypes.SwitchVal
,NormalStage2B2AB: SwitchTypes.SwitchVal
,LoadStage3Ac: SwitchTypes.SwitchVal
,AbortStage3A2BA: SwitchTypes.SwitchVal
,NormalStage3A2BA: SwitchTypes.SwitchVal
,PhA: SwitchTypes.SwitchVal
,PhB: SwitchTypes.SwitchVal
];
IFULoggerSimpleIORef: TYPE = REF IFULoggerSimpleIORec;
IFULoggerSimpleIORec: TYPE = RECORD [
XBus: ARRAY [0..2) OF CARDINAL
,fill1: [0 .. 32767],
DPRejectedBA: BOOLEAN
,fill2: [0 .. 255],
OpAB: [0..255]
,fill3: [0 .. 255],
AlphaAB: [0..255]
,fill4: [0 .. 255],
BetaAB: [0..255]
,fill5: [0 .. 255],
GammaAB: [0..255]
,fill6: [0 .. 255],
DeltaAB: [0..255]
,fill7: [0 .. 8191],
OpLengthBA: [0..7]
,fill8: [0 .. 32767],
InstReadyAB: BOOLEAN
,fill9: [0 .. 255],
ExceptionCodeAB: ExceptionCode
,fill10: [0 .. 255],
MicroCycleAB: [0..255]
,fill11: [0 .. 8191],
MicroCycleNextBA: MicroCycleNext
,fill12: [0 .. 32767],
MacroJumpBA: BOOLEAN
,fill13: [0 .. 255],
PCBusSrcB: PCBusSrc
,PCForLogAB: ARRAY [0..2) OF CARDINAL
,fill15: [0 .. 255],
LAB: [0..255]
,fill16: [0 .. 255],
SAB: [0..255]
,fill17: [0 .. 255],
AReg0BA: [0..255]
,fill18: [0 .. 255],
BReg0BA: [0..255]
,fill19: [0 .. 255],
CReg0BA: [0..255]
,fill20: [0 .. 255],
DPCmnd3A: PBusCommands
,DPData: ARRAY [0..2) OF CARDINAL
,fill22: [0 .. 32767],
DPRejectB: BOOLEAN
,fill23: [0 .. 4095],
DPFaultB: PBusFaults
,fill24: [0 .. 32767],
LoadStage1Ac: BOOLEAN
,fill25: [0 .. 32767],
LoadStage1Bc: BOOLEAN
,fill26: [0 .. 32767],
LoadStage2Ac: BOOLEAN
,fill27: [0 .. 32767],
BubbleStage2A1BA: BOOLEAN
,fill28: [0 .. 32767],
NormalStage2A1BA: BOOLEAN
,fill29: [0 .. 32767],
AbortStage2B2AB: BOOLEAN
,fill30: [0 .. 32767],
NormalStage2B2AB: BOOLEAN
,fill31: [0 .. 32767],
LoadStage3Ac: BOOLEAN
,fill32: [0 .. 32767],
AbortStage3A2BA: BOOLEAN
,fill33: [0 .. 32767],
NormalStage3A2BA: BOOLEAN
,fill34: [0 .. 32767],
PhA: BOOLEAN
,fill35: [0 .. 32767],
PhB: BOOLEAN
];
IFULoggerDriveRef: TYPE = REF IFULoggerDriveRec;
IFULoggerDriveRec: TYPE = RECORD [driveRecordInitialPadding: DriveTagType, drive: PACKED ARRAY IFULoggerPort OF DriveLevel];
IFULoggerPort: TYPE = {
XBus, DPRejectedBA, OpAB, AlphaAB, BetaAB, GammaAB, DeltaAB, OpLengthBA, InstReadyAB, ExceptionCodeAB, MicroCycleAB, MicroCycleNextBA, MacroJumpBA, PCBusSrcB, PCForLogAB, LAB, SAB, AReg0BA, BReg0BA, CReg0BA, DPCmnd3A, DPData, DPRejectB, DPFaultB, LoadStage1Ac, LoadStage1Bc, LoadStage2Ac, BubbleStage2A1BA, NormalStage2A1BA, AbortStage2B2AB, NormalStage2B2AB, LoadStage3Ac, AbortStage3A2BA, NormalStage3A2BA, PhA, PhB};
CreateIFULoggerIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = {
args: REF IFULoggerArgs ← NARROW[ct.typeData];
{OPEN args;
ioAsAny ← IF switch THEN NEW[IFULoggerSwitchIORec] ELSE NEW[IFULoggerSimpleIORec];
};
};
CreateIFULoggerDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = {
args: REF IFULoggerArgs ← NARROW[ct.typeData];
{OPEN args;
driveAsAny ← NEW[IFULoggerDriveRec];
};
};
IFULoggerStateRef: TYPE = REF IFULoggerStateRec;
IFULoggerStateRec: TYPE = RECORD [
opPipe: ARRAY [0..3] OF ARRAY Dragon.Phase OF LogPipeState,
last:       {a,ab,b,ba},
firstMicroOfMacro:  LogPipeState,
dpRejectedAB:   BOOL,
dpFaultedBA:   BOOL,
dpFaultedAB:   BOOL,
doTrap3BA:    BOOL,
xbusBCopy:    Dragon.HexWord,
logRegistersB:   BOOL,
interruptPending:  BOOL,
trapped:     BOOL
];
InitializeIFULogger: Initializer = {
args: REF IFULoggerArgs ← NARROW [cell.type.typeData];
{OPEN args;
state: IFULoggerStateRef ← NEW[IFULoggerStateRec];
cell.realCellStuff.state ← state;
};
};
IFULoggerEvalSimple: SimpleEval =
BEGIN
args: REF IFULoggerArgs ← NARROW[cell.type.typeData];
drive: IFULoggerDriveRef ← NARROW[cell.realCellStuff.newDriveAsAny];
sw: IFULoggerSwitchIORef ← NARROW[cell.realCellStuff.switchIO];
newIO: IFULoggerSimpleIORef ← NARROW[cell.realCellStuff.newIO];
state: IFULoggerStateRef ← NARROW[cell.realCellStuff.state];
BEGIN OPEN drive, newIO, args, state;
NewDisposition: PROC [ pipeState: LogPipeState, disp: MicroInstDisposition ] RETURNS [ newPipeState: LogPipeState ] = {
newPipeState ← pipeState;
newPipeState.disposition ← disp;
};
log: IO.STREAM;
IF NOT PhB AND last=b THEN {
last ← ba;
IF logRegistersB AND (log ← logRef^) # IO.noWhereStream THEN {
log.PutF[" a:%02x", IO.card[AReg0BA]];
log.PutF[ " b:%02x", IO.card[BReg0BA]];
log.PutF[ " c:%02x", IO.card[CReg0BA]];
};
logRegistersB ← FALSE;
SELECT opPipe[3][b].microCyc FROM
117 => { -- Reset finished
ClusterParams.clusterPanel.instrCount ← -1;
trapped ← FALSE;
};
120 => { -- first cycle of trap
trapped ← TRUE;
};
0 => IF NOT DPRejectedBA AND (SELECT opPipe[3][b].disposition FROM
valid => TRUE,
killed3a, killed3b =>
(MicroCycleAB = 120 -- trap that will apply to the new instruction -- ),
ENDCASE => FALSE) THEN {
The first microinstruction of a new macroinstruction instrCount+1 is now committed to retire, either in victory or defeat (as in "trapped"). This means that all register stores for the macroinstruction instrCount are completed, and none for macroinstruction instrCount+1 have yet occurred.
ClusterParams.clusterPanel.instrCount ← ClusterParams.clusterPanel.instrCount+
LizardRosemary.CheckSynch[
lizardSimRef: lizardSimRef,
clusterInst: [ -- the completed instruction
cycle:    ClusterParams.clusterPanel.cycle,
instr:    ClusterParams.clusterPanel.instrCount,
trapped:   trapped,
trapPC:   IF trapped THEN opPipe[3][b].pc ELSE 0,
pc:    firstMicroOfMacro.pc,
op:    firstMicroOfMacro.op,
alpha:    firstMicroOfMacro.alpha,
beta:    firstMicroOfMacro.beta,
gamma:   firstMicroOfMacro.gamma,
delta:    firstMicroOfMacro.delta
]
].deltaInstrCount;
firstMicroOfMacro ← opPipe[3][b];
trapped ← FALSE;
};
ENDCASE => NULL;
};
IF PhA THEN {dpRejectedAB ← DPRejectedBA; dpFaultedAB ← dpFaultedBA};
Pipe
IF PhB THEN opPipe[0][b] ← [
pc: DragonRoseExtras.LFD[PCForLogAB],
op: LOOPHOLE[OpAB],
alpha: AlphaAB,
beta: BetaAB,
gamma: GammaAB,
delta: DeltaAB,
microCyc: MicroCycleAB,
disposition: IF InstReadyAB THEN valid ELSE unready
];
IF LoadStage1Ac THEN opPipe[1][a] ← opPipe[0][b];
IF LoadStage1Bc THEN opPipe[1][b] ← opPipe[1][a];
IF LoadStage2Ac THEN opPipe[2][a] ← (SELECT TRUE FROM
NormalStage2A1BA => opPipe[1][b],
BubbleStage2A1BA => NewDisposition[opPipe[1][b], interlocked],
ENDCASE => ERROR);
IF PhB THEN opPipe[2][b] ← (SELECT TRUE FROM
NormalStage2B2AB => opPipe[2][a],
AbortStage2B2AB => NewDisposition[opPipe[2][a], killed2b],
ENDCASE => ERROR);
IF LoadStage3Ac THEN opPipe[3][a] ← (SELECT TRUE FROM
NormalStage3A2BA => opPipe[2][b],
AbortStage3A2BA => NewDisposition[opPipe[2][b], killed3a],
ENDCASE => ERROR);
IF PhB THEN
{opPipe[3][b] ← opPipe[3][a]; IF dpFaultedAB THEN opPipe[3][b].disposition ← killed3b};
IF PhB THEN {
xbusBCopy ← DragonRoseExtras.LFD[XBus];
dpFaultedBA ← DPFaultB # none;
doTrap3BA ← SELECT ExceptionCodeAB FROM
none, cJump => FALSE,
ENDCASE => TRUE;
IF last#b THEN {
last ← b;
Log instruction at the beginning of Ph0B.
IF ((log ← logRef^) # IO.noWhereStream) AND (ExceptionCodeAB # reset) THEN {
IF (ExceptionCodeAB # none) OR InstReadyAB THEN {
log.PutF["\n%5g%5g", IO.int[ClusterParams.clusterPanel.cycle], IO.int[ClusterParams.clusterPanel.instrCount] ];
SELECT TRUE FROM
ExceptionCodeAB=reseting
=> log.PutF["**Reseting "];
ExceptionCodeAB=reset
=> log.PutF["**Reset "];
ExceptionCodeAB=dpFault
=> log.PutF["**DPFault "];
dpRejectedAB
=> log.PutF["**DPReject "];
ExceptionCodeAB=cTrap
=> log.PutF["**EUCC "];
ExceptionCodeAB=bubble
=> log.PutF["**Bubble "];
ExceptionCodeAB=cJump
=> log.PutF["**CJRestrt "];
ExceptionCodeAB=rschlWait
=> log.PutF["**Reschdl "];
ExceptionCodeAB=iStkOFlow
=> log.PutF["**IStkOver "];
ExceptionCodeAB=eStkOFlow
=> log.PutF["**EStkOver "];
ExceptionCodeAB=ipFault
=> log.PutF["**IPgFault "];
ExceptionCodeAB=none
=> log.PutRope[" "];
ENDCASE
=> log.PutF[" cy: %2g ", IO.card[ExceptionCodeAB.ORD]];
log.PutF["pc:%08x", IO.card[DragonRoseExtras.LFD[PCForLogAB]] ];
SELECT TRUE FROM
dpRejectedAB => log.PutF[" --EU reject delay..."];
NOT InstReadyAB => log.PutF[" --IFetch delay..."];
ENDCASE => {
opLength: [0..5] = DragonRosemary.OpLength[OpAB];
log.PutF[" %-7g", IO.rope[Rope.Cat[DragonRosemary.OpName[OpAB],
(IF MicroCycleAB=0 THEN "" ELSE IO.PutFR["-%g", IO.int[MicroCycleAB]])]]];
IF opLength > 1
THEN log.PutF[" %02x", IO.card[AlphaAB]] ELSE log.PutF[" "];
IF opLength > 2
THEN log.PutF["%02x", IO.card[BetaAB]] ELSE log.PutF[" "];
IF opLength > 3
THEN log.PutF["%02x%02x", IO.card[GammaAB], IO.card[DeltaAB]]
ELSE log.PutF[" "];
log.PutF[" l:%02x", IO.card[LAB]]; -- at beginning of instruction
log.PutF[ " s:%02x", IO.card[SAB]]; -- at beginning of instruction
logRegistersB ← TRUE;
};
};
};
IF ExceptionCodeAB=reset THEN
ClusterParams.clusterPanel.instrCount ← -1;
};
};
END;
END;
RegisterCells[];
END.