IFUData2LS.rose
Herrmann, September 12, 1985 2:51:24 pm PDT
Curry, September 24, 1985 8:03:57 pm PDT
McCreight, December 31, 1985 1:54:06 pm PST
Copyright © 1984 by Xerox Corporation. All rights reserved.
Last edited by: McCreight, September 11, 1984 3:49:30 pm PDT
Last edited by: Curry, January 10, 1985 4:18:48 pm PST
Directory Dragon, DragOpsCross;
TranslationNeeds IFUPLAInstrDecode;
Imports BitOps;
CELLTYPE "LFormation"
PORTS [
AlphaBA    < INT[8],
SAB     < INT[8],
LStkTopAB    < INT[8], -- sometimes from Stack
LAB     > INT[8], -- to several places (S,A,B,C)
LPipe3BA   > INT[8], -- to Stack
LSourceLtBA   < EnumType["IFUPLAInstrDecode.LSourceLt"],
LSourceRtBA   < EnumType["IFUPLAInstrDecode.LSourceRt"],
LoadStage1Ac   < BOOL,
LoadStage1Bc   < BOOL,
LoadStage2Ac   < BOOL,
LoadStage3Ac   < BOOL,
PhA     < BOOL,
PhB     < BOOL
]
State
lBA, lAB: Dragon.HexByte,
lPipe: ARRAY [0..3] OF ARRAY Dragon.Phase OF Dragon.HexByte
lPipe[i] is the value of the L register to be recovered if the microinstruction at pipeline level i "fails". This assumes that each microinstruction can "fail" in only one way, and that that way is known as the microinstruction enters the pipeline.
EvalSimple
lBusLtB, lBusRtB: [0..256);
IF PhA THEN LAB ← lAB ← lBA;
IF PhB THEN {
lPipe[0][b] ← lAB;
lBusLtB ← SELECT LSourceLtBA FROM
l   => LAB,
s   => SAB,
zero  => 0,
l3   => lPipe[3][a],
ENDCASE => ERROR;
lBusRtB ← SELECT LSourceRtBA FROM
zero  => 0,
alpha  => AlphaBA,
stack  => LStkTopAB,
one  => 1,
ENDCASE => ERROR;
lBA ← (lBusLtB + lBusRtB) MOD 128;
};
Pipe
IF LoadStage1Ac THEN lPipe[1][a] ← lPipe[0][b];
IF LoadStage1Bc THEN lPipe[1][b] ← lPipe[1][a];
IF LoadStage2Ac THEN lPipe[2][a] ← lPipe[1][b];
IF PhB THEN lPipe[2][b] ← lPipe[2][a];
IF LoadStage3Ac THEN lPipe[3][a] ← lPipe[2][b];
IF PhB THEN lPipe[3][b] ← lPipe[3][a];
LPipe3BA ← lPipe[3][b];
ENDCELLTYPE;
CELLTYPE "SDelta" -- static logic
PORTS [
PopSa0BA < BOOL,
PopSb0BA < BOOL,
PushSc0BA < BOOL,
DeltaSBA  > INT[8]
]
EvalSimple
sum: INT;
sum  ← 0  + (IF PushSc0BA THEN 1 ELSE 0);
sum  ← sum - (IF PopSa0BA THEN 1 ELSE 0);
sum  ← sum - (IF PopSb0BA THEN 1 ELSE 0);
DeltaSBA ← (sum + 256) MOD 256;
ENDCELLTYPE;
CELLTYPE "SFormation"
PORTS [
AlphaBA   < INT[8],
LAB    < INT[8],
SAB    > INT[8],
DeltaSBA   < INT[8],
SSourceLtBA  < EnumType["IFUPLAInstrDecode.SSourceLt"],
SSourceRtBA  < EnumType["IFUPLAInstrDecode.SSourceRt"],
LoadStage1Ac   < BOOL,
LoadStage1Bc   < BOOL,
LoadStage2Ac   < BOOL,
LoadStage3Ac   < BOOL,
PhA    < BOOL,
PhB    < BOOL
]
State
sBA, sAB: Dragon.HexByte,
sPipe: ARRAY [0..3] OF ARRAY Dragon.Phase OF Dragon.HexByte
sPipe[i] is the value of the S register to be recovered if the microinstruction at pipeline level i "fails". This assumes that each microinstruction can "fail" in only one way, and that that way is known as the microinstruction enters the pipeline.
EvalSimple
sBusLt, sBusRt: Dragon.HexByte;
IF PhA THEN SAB ← sAB ← sBA;
IF PhB THEN {
sPipe[0][b] ← sAB;
sBusLt ← SELECT SSourceLtBA FROM
s   => SAB,
l   => LAB,
s2   => sPipe[2][a],
s3   => sPipe[3][a],
ENDCASE => ERROR;
sBusRt ← SELECT SSourceRtBA FROM
deltaS  => DeltaSBA,
alpha  => AlphaBA,
zero  => 0,
one  => 1,
ENDCASE => ERROR;
sBA ← (sBusLt+sBusRt+256) MOD 128;
};
Pipe
IF LoadStage1Ac THEN sPipe[1][a] ← sPipe[0][b];
IF LoadStage1Bc THEN sPipe[1][b] ← sPipe[1][a];
IF LoadStage2Ac THEN sPipe[2][a] ← sPipe[1][b];
IF PhB THEN sPipe[2][b] ← sPipe[2][a];
IF LoadStage3Ac THEN sPipe[3][a] ← sPipe[2][b];
ENDCELLTYPE;
CELLTYPE "SLimitTest"
PORTS [
XBus     = INT[32],
SAB     < INT[8],
EStkOverflow1BA > BOOL,
X1ASrcSLimitAc < BOOL,
X1ADstSLimitAc < BOOL,
PhA     < BOOL,
PhB     < BOOL
]
State
sLimitAB:    Dragon.HexByte,
sLimitFromXBusBA:  BOOL,
sLimitToXBusBA: BOOL,
eStkOverflow1BA:  BOOL
EvalSimple
IF X1ASrcSLimitAc THEN {drive[XBus] ← drive; XBus ← BitOps.ICID[sLimitAB, [0,0], 32, 24, 8]}
ELSE drive[XBus] ← ignore;
IF X1ADstSLimitAc THEN sLimitAB ← BitOps.ECFD[XBus, 32, 24, 8];
IF PhB THEN {
eStkOverflow1BA ← ((SAB+(255-sLimitAB --NOT sLimitAB-- )+1) MOD 128) IN [0..16);
};
EStkOverflow1BA ← eStkOverflow1BA;
ENDCELLTYPE