IFUData2ABC.rose
Herrmann, September 12, 1985 2:51:24 pm PDT
Curry, September 24, 1985 8:03:57 pm PDT
McCreight, March 10, 1986 6:49:08 pm PST
Copyright © 1984 by Xerox Corporation. All rights reserved.
Last edited by: McCreight, September 11, 1984 3:49:30 pm PDT
Last edited by: Curry, January 10, 1985 4:18:48 pm PST
Directory DragOpsCross;
TranslationNeeds Dragon, IFUPLAInstrDecode;
Imports DragonRoseExtras;
CELLTYPE "AFormation"
PORTS [
ARegAddr   = INT[8],
OpBA    < INT[8],
AlphaBA   < INT[8],
BetaBA   < INT[8],
LAB    < INT[8],
SAB    < INT[8],
AReg0BA   > INT[8], -- for the logger
AReg1BA   > INT[8],
ASourceLtBA < EnumType["IFUPLAInstrDecode.ABCSourceLt"],
ASourceRtBA < EnumType["IFUPLAInstrDecode.ABCSourceRt"],
ASourceOffBA < EnumType["IFUPLAInstrDecode.PlusOffset"],
LoadStage1Ac < BOOL,
LoadStage1Bc < BOOL,
PhA    < BOOL,
PhB    < BOOL
]
State
aPipe: ARRAY [0..1] OF ARRAY Dragon.Phase OF Dragon.HexByte
EvalSimple
IF PhB THEN {
aBusLt, aBusRt, sum: Dragon.HexByte;
aBusLt ← SELECT ASourceLtBA FROM
cBase => DragonRoseExtras.PRtoByte[euConstant],
aBase => DragonRoseExtras.PRtoByte[euAux],
s  => SAB,
l  => LAB,
zero => 0,
ENDCASE => ERROR;
aBusRt ← SELECT ASourceRtBA FROM
alpha  => AlphaBA,
alpha03 => AlphaBA/16,
alpha47 => AlphaBA MOD 16,
op47  => OpBA MOD 16,
beta  => BetaBA,
beta03  => BetaBA/16,
beta47  => BetaBA MOD 16,
ENDCASE => SELECT ASourceOffBA FROM
zero  => 0,
one  => 1,
two  => 2,
three  => 3,
minus4 => 256-4,
minus3 => 256-3,
minus2 => 256-2,
minus1 => 256-1,
ENDCASE => ERROR;
sum ← SELECT ASourceLtBA FROM
s, l  => (aBusLt + aBusRt) MOD 128,
ENDCASE => (aBusLt + aBusRt) MOD 256;
aPipe[0][b] ← sum;
};
IF LoadStage1Ac THEN aPipe[1][a] ← aPipe[0][b];
IF LoadStage1Bc THEN aPipe[1][b] ← aPipe[1][a];
AReg0BA ← aPipe[0][b];
AReg1BA ← aPipe[1][b];
XBus ← BitOps.ICID[aPipe[1][b], XBus, 32, Dragon.aRegKBusPos, 8] };
drive[ARegAddr] ← IF PhB THEN drive ELSE ignore;
ARegAddr ← aPipe[1][b];
ENDCELLTYPE;
CELLTYPE "BFormation"
PORTS [
BRegAddr   = INT[8],
OpBA    < INT[8],
AlphaBA   < INT[8],
BetaBA   < INT[8],
LAB    < INT[8],
SAB    < INT[8],
BReg0BA   > INT[8], -- for the logger
BReg1BA   > INT[8],
BSourceLtBA  < EnumType["IFUPLAInstrDecode.ABCSourceLt"],
BSourceRtBA  < EnumType["IFUPLAInstrDecode.ABCSourceRt"],
BSourceOffBA < EnumType["IFUPLAInstrDecode.PlusOffset"],
LoadStage1Ac < BOOL,
LoadStage1Bc < BOOL,
PhA    < BOOL,
PhB    < BOOL
]
State
bPipe: ARRAY [0..1] OF ARRAY Dragon.Phase OF Dragon.HexByte
EvalSimple
IF PhB THEN {
bBusLt, bBusRt, sum: Dragon.HexByte;
bBusLt ← SELECT BSourceLtBA FROM
cBase => DragonRoseExtras.PRtoByte[euConstant],
aBase => DragonRoseExtras.PRtoByte[euAux],
s  => SAB,
l  => LAB,
zero => 0,
ENDCASE => ERROR;
bBusRt ← SELECT BSourceRtBA FROM
op47  => OpBA MOD 16,
alpha  => AlphaBA,
alpha03 => AlphaBA/16,
alpha47 => AlphaBA MOD 16,
beta  => BetaBA,
beta03  => BetaBA/16,
beta47  => BetaBA MOD 16,
ENDCASE => SELECT BSourceOffBA FROM
zero  => 0,
one  => 1,
two  => 2,
three  => 3,
minus4 => 256-4,
minus3 => 256-3,
minus2 => 256-2,
minus1 => 256-1,
ENDCASE => ERROR;
sum ← SELECT BSourceLtBA FROM
s, l  => (bBusLt + bBusRt) MOD 128,
ENDCASE => (bBusLt + bBusRt) MOD 256;
bPipe[0][b] ← sum;
};
IF LoadStage1Ac THEN bPipe[1][a] ← bPipe[0][b];
IF LoadStage1Bc THEN bPipe[1][b] ← bPipe[1][a];
BReg0BA ← bPipe[0][b];
BReg1BA ← bPipe[1][b];
XBus ← BitOps.ICID[bPipe[1][b], XBus, 32, Dragon.bRegKBusPos, 8] };
drive[BRegAddr] ← IF PhB THEN drive ELSE ignore;
BRegAddr ← bPipe[1][b];
ENDCELLTYPE;
CELLTYPE "CFormation"
PORTS [
CRegAddr   = INT[8],
OpBA    < INT[8],
AlphaBA   < INT[8],
BetaBA   < INT[8],
LAB    < INT[8],
SAB    < INT[8],
CSourceLtBA  < EnumType["IFUPLAInstrDecode.ABCSourceLt"],
CSourceRtBA  < EnumType["IFUPLAInstrDecode.ABCSourceRt"],
CSourceOffBA < EnumType["IFUPLAInstrDecode.MinusOffset"],
AReg1BA   < INT[8],
BReg1BA   < INT[8],
CReg0BA   > INT[8], -- for the logger
ARegIsC2BA > BOOL,
ARegIsC3BA > BOOL,
BRegIsC2BA > BOOL,
BRegIsC3BA > BOOL,
LoadStage1Ac  < BOOL,
LoadStage1Bc  < BOOL,
LoadStage2Ac  < BOOL,
BubbleStage2A1BA  < BOOL,
NormalStage2A1BA  < BOOL,
AbortStage2B2AB  < BOOL,
NormalStage2B2AB  < BOOL,
LoadStage3Ac  < BOOL,
AbortStage3A2BA  < BOOL,
NormalStage3A2BA  < BOOL,
DPFaultB    < EnumType["Dragon.PBusFaults"],
PhA    < BOOL,
PhB    < BOOL
]
State
cPipe: ARRAY [0..3] OF ARRAY Dragon.Phase OF Dragon.HexByte,
dpFaultedAB, dpFaultedBA: BOOL
EvalSimple
noStore: Dragon.HexByte = DragonRoseExtras.PRtoByte[euJunk];
IF PhB THEN {
cBusLt, cBusRt, sum: Dragon.HexByte;
cBusLt ← SELECT CSourceLtBA FROM
aBase => DragonRoseExtras.PRtoByte[euAux],
cBase => DragonRoseExtras.PRtoByte[euConstant],
l  => LAB,
s  => SAB,
zero => 0,
ENDCASE => ERROR;
cBusRt ← SELECT CSourceRtBA FROM
beta  => BetaBA,
beta03  => BetaBA/16,
beta47  => BetaBA MOD 16,
op47  => OpBA MOD 16,
alpha  => AlphaBA,
alpha03 => AlphaBA/16,
alpha47 => AlphaBA MOD 16,
ENDCASE => SELECT CSourceOffBA FROM
minus4 => 256-4,
minus3 => 256-3,
minus2 => 256-2,
minus1 => 256-1,
zero  => 0,
one  => 1,
two  => 2,
three  => 3,
ENDCASE => ERROR;
sum ← (cBusLt + cBusRt) MOD 256;
sum ← SELECT CSourceLtBA FROM s, l => sum MOD 128 ENDCASE => sum;
cPipe[0][b] ← sum;
};
IF PhA THEN dpFaultedAB ← dpFaultedBA;
IF PhB THEN dpFaultedBA ← DPFaultB # none;
Pipe
IF LoadStage1Ac THEN cPipe[1][a] ← cPipe[0][b];
IF LoadStage1Bc THEN cPipe[1][b] ← cPipe[1][a];
IF LoadStage2Ac THEN cPipe[2][a] ← (SELECT TRUE FROM
BubbleStage2A1BA => noStore,
NormalStage2A1BA => cPipe[1][b],
ENDCASE => ERROR);
IF PhB THEN cPipe[2][b] ← (SELECT TRUE FROM
AbortStage2B2AB => noStore,
NormalStage2B2AB => cPipe[2][a],
ENDCASE => ERROR);
IF LoadStage3Ac THEN cPipe[3][a] ← (SELECT TRUE FROM
AbortStage3A2BA => noStore,
NormalStage3A2BA => cPipe[2][b],
ENDCASE => ERROR);
IF PhB THEN cPipe[3][b] ← (SELECT TRUE FROM
dpFaultedAB => DragonRoseExtras.PRtoByte[euJunk],
NOT dpFaultedAB => cPipe[3][a],
ENDCASE => ERROR);
CReg0BA ← cPipe[0][b];
XBus ← BitOps.ICID[cPipe[3][b], XBus, 32, Dragon.cRegKBusPos, 8];
drive[CRegAddr] ← IF PhB THEN drive ELSE ignore;
CRegAddr ← LOOPHOLE[cPipe[3][b]];
ARegIsC2BA ← (AReg1BA = cPipe[2][a]); -- static logic
ARegIsC3BA ← (AReg1BA = cPipe[3][a]);
BRegIsC2BA ← (BReg1BA = cPipe[2][a]);
BRegIsC3BA ← (BReg1BA = cPipe[3][a]);
ENDCELLTYPE;
CELLTYPE "ABCFormation"
PORTS[
XBus    = INT[32],
OpBA    < INT[8],
AlphaBA   < INT[8],
BetaBA   < INT[8],
LAB    < INT[8],
SAB    < INT[8],
AReg0BA   > INT[8], -- passed just to the logger
BReg0BA   > INT[8], -- passed just to the logger
CReg0BA   > INT[8], -- passed just to the logger
ASourceLtBA < EnumType["IFUPLAInstrDecode.ABCSourceLt"],
ASourceRtBA < EnumType["IFUPLAInstrDecode.ABCSourceRt"],
ASourceOffBA < EnumType["IFUPLAInstrDecode.PlusOffset"],
BSourceLtBA  < EnumType["IFUPLAInstrDecode.ABCSourceLt"],
BSourceRtBA  < EnumType["IFUPLAInstrDecode.ABCSourceRt"],
BSourceOffBA < EnumType["IFUPLAInstrDecode.PlusOffset"],
CSourceLtBA < EnumType["IFUPLAInstrDecode.ABCSourceLt"],
CSourceRtBA < EnumType["IFUPLAInstrDecode.ABCSourceRt"],
CSourceOffBA < EnumType["IFUPLAInstrDecode.MinusOffset"],
CRegIsField3B = BOOL, -- tri-state, driven during PhB by ControlPipe
EUAluLeftSrc1B  = EnumType["Dragon.ALULeftSources"], -- tri-state, driven during PhB by IFUInterlock
EUAluRightSrc1B = EnumType["Dragon.ALURightSources"],
EUStore2ASrc1B  = EnumType["Dragon.Store2ASources"],
ARegIsC2BA  > BOOL,
ARegIsC3BA  > BOOL,
BRegIsC2BA  > BOOL,
BRegIsC3BA  > BOOL,
LoadStage1Ac  < BOOL, -- Pipe Controls
LoadStage1Bc  < BOOL,
LoadStage2Ac  < BOOL,
BubbleStage2A1BA  < BOOL,
NormalStage2A1BA  < BOOL,
AbortStage2B2AB  < BOOL,
NormalStage2B2AB  < BOOL,
LoadStage3Ac  < BOOL,
AbortStage3A2BA  < BOOL,
NormalStage3A2BA  < BOOL,
DPFaultB    < EnumType["Dragon.PBusFaults"],
PhA    < BOOL,
PhB     < BOOL
]
Expand
AReg1BA: INT[8];
BReg1BA: INT[8];
ARegAddr: INT[8]; -- Bit 0 to 7
BRegAddr: INT[8];
CRegAddr: INT[8];
XRest: INT[7];
This must correspond to Dragon.aRegKBusPos, Dragon.bRegKBusPos, and Dragon.cRegKBusPos...
EQUIVALENCE XBus, ARegAddr cat BRegAddr cat CRegAddr cat CRegIsField3B cat EUAluLeftSrc1B cat EUAluRightSrc1B cat EUStore2ASrc1B;
aFormation: AFormation[];
bFormation: BFormation[];
cFormation: CFormation[]
ENDCELLTYPE