DIRECTORY
Basics,
Dragon,
DragOpsCross,
IFUPLA,
PLAOps;

IFUPLAInstrDecode1: CEDAR PROGRAM
IMPORTS IFUPLA, PLAOps EXPORTS IFUPLA =
BEGIN OPEN IFUPLA, PO: PLAOps;

GenInstrDecodePLA1:  PUBLIC PROC = {

sdd:		PO.BoolExpr	_ BE[m:[beta: 200B],	d:[beta: 200B]];
opt:		PO.BoolExpr	_ BE[m:[beta: 040B],	d:[beta: 040B]];
sd:			PO.BoolExpr	_ BE[m:[beta: 100B],	d:[beta: 100B]];
aux:		PO.BoolExpr	_ BE[m:[beta: 020B],	d:[beta: 020B]];

instr, delay, trap, exception:		PO.BoolExpr;	-- Temporaries

m: InstrDecodeOut;

exception _ BE[m:[stateException: TRUE],	d:[stateException: TRUE]];
current _ PO.And[exception, BE[m:[state: prioritySig], d:[state: highPriority]]];
Set[s:current, m:[state: exceptionSig], d:[state: reseting],	out: [
doMacroJump: FALSE,
dontGetNextMacro: TRUE,
pcNext: pcBus, pcBusSrc: trapGen,
lSource: [ zero, one ],
sSource: [ zero, zero ] ]];
Set[s:current, m:[state: exceptionSig], d:[state: reset],		out: [
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
pcNext: pcBus, pcBusSrc: trapGen,
lSource: [ zero, one ],
sSource: [ zero, zero ] ]];
m _ [
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
pcNext: pcBus, pcBusSrc: trapGen,
lSource: [ l3, zero ],
sSource: [ s3, zero ],
restoreTrap3: TRUE];
Set[s:current, m:[state: exceptionSig], d:[state: euCC],	out: m];
Set[s:current, m:[state: exceptionSig], d:[state: epFault],	out: m];
Set[s:current, m:[state: exceptionSig], d:[state: cJump],	out: [
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
pcNext: pcBus, pcBusSrc: pipe3,
lSource: [ l3, zero ],
sSource: [ s3, zero ],
restoreTrap3: TRUE ]];

current _ PO.And[exception, PO.Not[BE[m:[state: prioritySig], d:[state: highPriority]]]];
Set[s:current, m:[stateDelay: TRUE],		d:[stateDelay: TRUE], out: Delayed];

Set[s:current, m:[stateDelay: TRUE],	d:[stateDelay: FALSE], out:[
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
pcNext: pcBus, pcBusSrc: trapGen,
iStackPostEffect: push,
trappingControl: disable ] ];



current _ BE[m:[stateException: TRUE],	d:[stateException: FALSE]];
Set[s:current, m:[stateDelay: TRUE],		d:[stateDelay: TRUE], out: Delayed];

current _ PO.And[current, BE[m:[stateDelay: TRUE],	d:[stateDelay: FALSE]]];
Set[s:current, m:[instReady: TRUE], d:[instReady: FALSE], out: Delayed];
current _ PO.And[current, BE[m:[instReady: TRUE],		d:[instReady: TRUE]]];

delay _ PO.Or[
BE[m:[pushPending: TRUE],	d:[pushPending: TRUE]],
BE[m:[popPending: TRUE],		d:[popPending: TRUE]]];
trap _ PO.And[
PO.Not[delay],
BE[m:[iStkEmpty: TRUE],		d:[iStkEmpty: TRUE]]];
Set[s: PO.And[current, delay],				m:[op: instrIsSig], d:[op: dRET],	out: Delayed];
Set[s: PO.And[current, delay],				m:[op: instrIsSig], d:[op: dRETT],	out: Delayed];
Set[s: PO.And[current, delay],				m:[op: instrIsSig], d:[op: dRETN],	out: Delayed];
m _ [
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
pcNext: pcBus, pcBusSrc: trapGen, -- Underflow is the default
sSource: [ l, alpha ],
trappingControl:	disable ];
Set[s: PO.And[current, trap],						m:[op: instrIsSig], d:[op: dRET],	out: m];
m.sSource _ [ s, zero ];
Set[s: PO.And[current, trap],						m:[op: instrIsSig], d:[op: dRETT],	out: m];
Set[s: PO.And[current, trap],						m:[op: instrIsSig], d:[op: dRETN],	out: m];
Set[s: PO.And[current, PO.Not[PO.Or[delay, trap]]],	m:[op: instrIsSig], d:[op: dRET],	out: [
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
pcNext: pcBus, pcBusSrc: stack,
lSource: [ l3, zero ],
sSource: [ l, alpha ],
iStackPostEffect: pop ]];
Set[s: PO.And[current, PO.Not[PO.Or[delay, trap]]],	m:[op: instrIsSig], d:[op: dRETT],	out: [
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
pcNext: pcBus, pcBusSrc: stack,
lSource: [ l3, zero ],
iStackPostEffect: pop,
trappingControl: enable ]];
Set[s: PO.And[current, PO.Not[PO.Or[delay, trap]]],	m:[op: instrIsSig], d:[op: dRETN],	out: [
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
pcNext: pcBus, pcBusSrc: stack,
lSource: [ l3, zero ],
iStackPostEffect: pop ]];
Set[s: PO.And[current, delay],						m:[op: instrIsSig], d:[op: dLIFUR], out: Delayed];
Set[s: PO.And[current, PO.Not[delay]],				m:[op: instrIsSig], d:[op: dLIFUR], out:[
bReg: [zero, alpha],
xASource: bReg,
cReg: [ s, one ],
deltaSc: push ]];

delay _ PO.And[
BE[m:[popPending: TRUE],			d:[popPending: TRUE]],
BE[m:[iStkEmpty: TRUE],			d:[iStkEmpty: FALSE]]];
trap _ PO.And[
PO.Not[delay], 
BE[m:[iStkEmpty: TRUE],			d:[iStkEmpty: TRUE]],
BE[m:[pushPending: TRUE],		d:[pushPending: FALSE]] ];
Set[s: PO.And[current, delay],		m:[op: instrIsSig], d:[op: dEP],	out: Delayed];
Set[s: PO.And[current, trap],		m:[op: instrIsSig], d:[op: dEP],	out: [
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
pcNext: pcBus, pcBusSrc: trapGen,
lSource: [ s, alpha ],
pclsPipe: seqPCnewLS,
iStackPostEffect: push,  -- this push differentiates this trap from the following
trappingControl: disable ]];
Set[s: PO.And[current, PO.Not[PO.Or[delay, trap]]],	m:[op: instrIsSig], d:[op: dEP],	out:
[lSource: [ s, alpha]]];

Set[s:current, m:[op: instrIsSig], d:[op: dDIS],	out:[deltaSa: pop]];
Set[s:current, m:[op: instrIsSig], d:[op: dAS],		out:[sSource: [s, alpha]]];
Set[s:current, m:[op: instrIsSig], d:[op: dAL],		out:[lSource: [l, alpha]]];
Set[s:current, m:[op: instrIsSig], d:[op: dASL],	out:[sSource: [l, alpha]]];

m _ [
aReg: abStackTop,
xASource: beta,
deltaSa: pop,
aluOp: VSub,
condEffect: macroJump,
condSel: EZ,
doMacroJump: FALSE,
dontGetNextMacro: FALSE,
pclsPipe: offSetPCnewLS, pcOffSetSrc: alphaS];
Set[s:current, m:[op: instrIsSig],	d:[op: dJEBB],	out:m];
m.condSel _ NE;
Set[s:current, m:[op: instrIsSig],	d:[op: dJNEBB],	out:m];

m _ [
aReg: abStackTop,
xASource: beta,
deltaSa: pop,
aluOp: VSub,
condEffect: macroJump,
condSel: EZ,
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
pcNext: pcBus, pcBusSrc: offSetPC, pcOffSetSrc: alphaS,
pclsPipe: seqPCnewLS];
Set[s:current, m:[op: instrIsSig],	d:[op: dJNEBBJ],	out:m];
m.condSel _ NE;
Set[s:current, m:[op: instrIsSig],	d:[op: dJEBBJ],	out:m];

instr _ PO.And[current, BE[m:[op: instrBot4NotSig], d:[op: dRJEB]]];	-- RJ*B and RJ*BJ
Set[s:current, m:[op: instrBot3NotSig],	d:[op: dRJEB],	out:[	-- RJ*B
aluOp: VSub,
condSel: op57,	--  Low 3 bits distinguish between 2 * 8 Jumps
condEffect: macroJump,
doMacroJump: FALSE,
dontGetNextMacro: FALSE,
pclsPipe: offSetPCnewLS, pcOffSetSrc: alphaS] ];
Set[s:current, m:[op: instrBot3NotSig],	d:[op: dRJEBJ],	out:[	-- RJ*BJ
aluOp: VSub,
condSel: op57,
condEffect: macroJump,
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
pcNext: pcBus, pcBusSrc: offSetPC, pcOffSetSrc: alphaS,
pclsPipe: seqPCnewLS] ];
Set[s: PO.And[		sd,	instr],	out:[aReg:[ s, minus1 ]]];
Set[s: PO.And[PO.Not[sd],	instr],	out:[aReg:[ s, zero ]]];
Set[s: PO.And[ PO.Not[opt],			aux,	instr],				out:[bReg:[ aBase,	beta47 ]]];
Set[s: PO.And[ PO.Not[opt],	PO.Not[aux],	instr],				out:[bReg:[ l,			beta47 ]]];
Set[s: PO.And[opt,	instr],	m:[beta: 010B], d:[beta: 000B],	out:[bReg:[ cBase,	beta47 ]]];
Set[s: PO.And[opt,	instr],	m:[beta: 004B], d:[beta: 000B],	out:[bReg:[ cBase,	beta47 ]]];
Set[s: PO.And[opt,	instr],	m:[beta: 015B], d:[beta: 014B],	out:[bReg:[ s,		zero ]]];
Set[s: PO.And[opt,	instr],	m:[beta: 015B], d:[beta: 015B],	out:[bReg:[ s,		minus1 ]]];
Set[s: PO.And[sdd,	instr], 										out:[deltaSa: pop]];
Set[s: PO.And[opt,	instr], m:[beta:	016B],	d:[beta:	016B],	out:[deltaSb: pop]];

Set[s:current, m:[op: instrIsSig],	d:[op: dJ1],	out:DefaultMicro]; -- Just too mark as ~Xops
Set[s:current, m:[op: instrIsSig],	d:[op: dJ2],	out:DefaultMicro]; -- Just too mark as ~Xops
Set[s:current, m:[op: instrIsSig],	d:[op: dJ3],	out:DefaultMicro]; -- Just too mark as ~Xops
Set[s:current, m:[op: instrIsSig],	d:[op: dJ5],	out:DefaultMicro]; -- Just too mark as ~Xops

Set[s:current, m:[op: instrIsSig],	d:[op: dJB], out:[
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
pcNext: pcBus, pcBusSrc: offSetPC, pcOffSetSrc: alphaS ]];

Set[s:current, m:[op: instrIsSig],	d:[op: dJDB], out:[
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
pcNext: pcBus, pcBusSrc: offSetPC, pcOffSetSrc: betaAlphaS ]];

Set[s:current, m:[op: instrIsSig],	d:[op: dDJ], out:[
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
pcNext: pcBus, pcBusSrc: delGamBetAlp ]];

instr _ PO.And[current, BE[m:[op: instrIsSig], d:[op: dSJ]]];
Set[s:instr, m:[state: byteIsSig],	d:[state: 0], out:[ -- ifuXBus _ [S]
dontGetNextMacro: TRUE,
pcNext: pcBus,
bReg: abStackTop,
cReg: ifuXBus ]];
Set[s:instr, m:[state: byteIsSig],	d:[state: 1], out:NoOpMicro];	-- to allow Xa to latch Result3
Set[s:instr, m:[state: byteIsSig],	d:[state: 2], out:NoOpMicro];	-- to allow Xa to latch Result3
Set[s:instr, m:[state: byteIsSig],	d:[state: 3], out:NoOpMicro];	-- to allow Xa to latch Result3
Set[s:instr, m:[state: byteIsSig],	d:[state: 4], out:[ -- S _ S-1
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
pcNext: pcBus, pcBusSrc: offSetPC, pcOffSetSrc: xA,
deltaSa: pop ]];

Set[s:current, m:[op: instrIsSig], d:[op: dLFC], out:[
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
pcNext: pcBus, pcBusSrc: offSetPC, pcOffSetSrc: betaAlphaS,
pclsPipe: seqPCnewLS,
iStackPostEffect: push ]];

Set[s:current, m:[op: instrIsSig], d:[op: dDFC], out:[
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
pcNext: pcBus, pcBusSrc: delGamBetAlp,
pclsPipe: seqPCnewLS,
iStackPostEffect: push ]];

instr _ PO.And[current, BE[m:[op: instrIsSig], d:[op: dSFC]]];
Set[s:instr, m:[state: byteIsSig],	d:[state: 0], out:[ -- ifuXBus _ [S]
dontGetNextMacro: TRUE,
pcNext: pcBus,
bReg: abStackTop,
cReg: ifuXBus ]];
Set[s:instr, m:[state: byteIsSig],	d:[state: 1], out:NoOpMicro];	-- to allow Xa to latch Result3
Set[s:instr, m:[state: byteIsSig],	d:[state: 2], out:NoOpMicro];	-- to allow Xa to latch Result3
Set[s:instr, m:[state: byteIsSig],	d:[state: 3], out:NoOpMicro];	-- to allow Xa to latch Result3
Set[s:instr, m:[state: byteIsSig],	d:[state: 4], out:[ -- S _ S-1
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
pcNext: pcBus, pcBusSrc: xA,
deltaSa: pop,
pclsPipe: seqPCnewLS,
iStackPostEffect: push ]];

instr _ PO.And[current, BE[m:[op: instrIsSig], d:[op: dSFCI]]];
Set[s:instr, m:[state: byteIsSig],	d:[state: 0], out:[ -- ifuXBus _ [S]^
dontGetNextMacro: TRUE,
pcNext: pcBus,
bReg: abStackTop,
cReg: ifuXBus,
euPBusCmd: Fetch ]];
Set[s:instr, m:[state: byteIsSig],	d:[state: 1], out:NoOpMicro];	-- to allow Xa to latch Result3
Set[s:instr, m:[state: byteIsSig],	d:[state: 2], out:NoOpMicro];	-- to allow Xa to latch Result3
Set[s:instr, m:[state: byteIsSig],	d:[state: 3], out:NoOpMicro];	-- to allow Xa to latch Result3
Set[s:instr, m:[state: byteIsSig],	d:[state: 4], out:[ -- S _ S-1
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
pcNext: pcBus, pcBusSrc: xA,
pclsPipe: seqPCnewLS,
iStackPostEffect: push ]];

GenInstrDecodePLA2[]; -- Arbitrary break
}; -- of GenInstrDecodePLA1

END.


ÄIFUPLAInstrDecode1.mesa
Copyright c 1984 by Xerox Corporation.  All rights reserved.
Last edited by TWilliams, August 27, 1984 4:58:00 pm PDT
Last edited by Curry, November 24, 1984 1:58:08 pm PST

Used in RR and RJB instructions
Do High Priority Exceptions
Delayed Low Priority Exceptions
Do Low Priority Exceptions
Not An Exception

Instruction not ready
Check for Delays and IStack Underflow traps in dRET, dRETT, dRETN, dLIFUR
Temporary BE's used by dRET, dRETT, dRETN, dLIFUR
Check for Delay and IStack Underflow trap in EP
Look for the case of a Call - EP sequence broken by a Reschedule which returns with an empty IStack.  EP (L_S+alpha) => that the stack is expected to contain some local values which (if IStack is empty) have been swapped out.
Temporary BE's used by EP:
Do the rest of the S and L modifiers here
dRJ*B and dRJ*BJ  - Bit 4 distinguishes between them
Main Body
AReg depends only on sd
BReg
Stack
deltaS: 0, -- shouldn't SFCI pop S?
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