IFUPLAMainControl.mesa
Copyright c 1984 by Xerox Corporation. All rights reserved.
Last edited by Curry, January 11, 1985 3:51:41 pm PST
DIRECTORY
Commander,
Dragon,
DragOpsCross,
IFUPLA,
IO,
PLAOps;
IFUPLAMainControl: CEDAR PROGRAM
IMPORTS Commander, IO, PLAOps EXPORTS IFUPLA =
BEGIN OPEN IFUPLA, PO: PLAOps;
trapEffectNotSig:  TrappingControl  ← FIRST [TrappingControl];
trapEffectIsSig:  TrappingControl  ← LAST [TrappingControl];
condEffectNotSig: CondEffect   ← FIRST [CondEffect];
condEffectIsSig:  CondEffect   ← LAST [CondEffect];
pBusFaultNotSig: Dragon.PBusFaults ← FIRST [Dragon.PBusFaults];
pBusFaultIsSig:  Dragon.PBusFaults ← LAST [Dragon.PBusFaults];
GenMainControlPLA: PUBLIC PROC = {
cur, done, temp, interlock, iStkOverflow:  PO.BoolExpr;
noBypass, read1, read2, ac2, bc2, passRt:  PO.BoolExpr;
done  ← PO.Or[
   BE[m:[dontGetNextMacro: TRUE], d:[dontGetNextMacro: FALSE ]],
   BE[m:[doMacroJump:  TRUE], d:[doMacroJump:  TRUE ]] ];
noBypass ← BE[m:[noBypassing: TRUE],  d:[noBypassing: TRUE]];
read1  ← BE[m:[pCmndLev1Rd: TRUE],  d:[pCmndLev1Rd: TRUE]];
read2  ← BE[m:[pCmndLev2Rd: TRUE],  d:[pCmndLev2Rd: TRUE]];
ac2  ← BE[m:[aRegIsC2: TRUE],    d:[aRegIsC2: TRUE]];
bc2  ← BE[m:[bRegIsC2: TRUE],    d:[bRegIsC2: TRUE]];
passRt  ← PO.And[
   BE[m:[notPassRtIfAZero: TRUE], d:[notPassRtIfAZero: FALSE]],
   BE[m:[aRegIsZero:  TRUE],  d:[aRegIsZero:  TRUE]] ];
interlock ← PO.Or[
PO.And[read2, ac2],
PO.And[read2, bc2, PO.Not[passRt], BE[m:[kIsRtOp: TRUE], d:[kIsRtOp: FALSE]] ],
PO.And[
BE[m:[aluOpFOP:  TRUE], d:[aluOpFOP: TRUE]],
BE[m:[cRegIsField:  TRUE], d:[cRegIsField: TRUE]] ] ];
Reset
Set[m:[reseting: TRUE], d:[reseting: TRUE], out:[
stateException: TRUE,
stateExceptCode: reseting,
trapPC:   TrapPC[ResetTrap], -- really not necessary here
pipeKill1:   TRUE,
pipeKill23:   TRUE ] ];
cur ← BE[m:[reseting: TRUE], d:[reseting: FALSE]];
Set[s:cur, m:[wereReseting: TRUE], d:[wereReseting: TRUE], out:[
stateException: TRUE,
stateExceptCode: reset,
trapPC:   TrapPC[ResetTrap],
pipeKill1:   TRUE,
pipeKill23:   TRUE ] ];
cur ← PO.And[cur, BE[m:[wereReseting: TRUE], d:[wereReseting: FALSE]]];
Fault
FOR pf: Dragon.PBusFaults IN Dragon.PBusFaults DO-- If not#None THEN fault
IF pf=None THEN LOOP;
Set[s:cur, m:[pBusFault3: pBusFaultIsSig], d:[pBusFault3: pf], out:[
stateException: TRUE,
stateExceptCode: epFault,
trapPC:   TrapPC[EUPbusTrap0],
trapOrPFault: TRUE, 
pipeKill1:   TRUE,
pipeKill23:   TRUE ] ];
ENDLOOP;
cur ← PO.And[cur, BE[m:[pBusFault3: pBusFaultIsSig], d:[pBusFault3: None]]];
Reject
Set[s:cur, m:[pBusReject3: TRUE], d:[pBusReject3: TRUE], out:[
stateLast:    TRUE,
delayNextInstr:   TRUE,
pipeCycle0:    TRUE,
pipeCycle123:   TRUE ] ];
cur ← PO.And[cur, BE[m:[pBusReject3: TRUE], d:[pBusReject3: FALSE]]];
Condition
temp ← PO.And[cur, BE[m:[aluCondResult2: TRUE], d:[aluCondResult2: TRUE]]];
Set[s:temp, m:[condEffect2: condEffectIsSig], d:[condEffect2: macroTrap], out:[
stateException: TRUE,
stateExceptCode: euCC,
trapPC:   TrapPC[ALUCondEZ],
trapOrCond:   TRUE,
pipeKill1:   TRUE,
pipeKill23:   TRUE ] ];
Set[s:temp, m:[condEffect2: condEffectIsSig], d:[condEffect2: macroJump], out:[
stateException: TRUE,
stateExceptCode: cJump,
pipeKill1:   TRUE,
pipeKill23:   TRUE ] ];
Set[s:temp, m:[condEffect2: condEffectIsSig], d:[condEffect2: microJump], out:[
stateMicroBranch: TRUE,
pipeKill1:    TRUE,
pipeKill23:    TRUE ] ];
cur ← PO.And[cur, BE[m:[aluCondResult2: TRUE], d:[aluCondResult2: FALSE]]];
Pipe Interlock
Set[s: PO.And[cur, interlock], out:[
stateLast:   TRUE,
delayNextInstr: TRUE,
pipeCycle0:   TRUE,
pipeKill1:   TRUE]];
cur ← PO.And[cur,    PO.Not[interlock]];
Instruction Fetch Fault (and instruction not ready)
Set[s:cur, m:[iFetchFault: TRUE], d:[iFetchFault: TRUE], out:[
stateException: TRUE,
stateExceptCode: iFtchFault,
trapPC:   TrapPC[IFUPageFaultTrap] ]];
cur ← PO.And[cur, BE[m:[iFetchFault: TRUE], d:[iFetchFault: FALSE]]];
Instruction Delayed
Set[s:cur, m:[instrDelayed: TRUE], d:[instrDelayed: TRUE], out:[
stateLast: TRUE,
trapPC: DefaultTrapPC ]];
cur ← PO.And[cur, BE[m:[instrDelayed: TRUE], d:[instrDelayed: FALSE]]];
Instruction not done
Set[s:PO.And[cur, PO.Not[done]], out:[
stateLastPlusOne: TRUE,
trapPC:    DefaultTrapPC ]];
cur ← PO.And[cur, done];
Low priority traps inhibited
Set[s:cur, m:[inhibTraps: TRUE], d:[inhibTraps: TRUE], out:[
stateZero: TRUE,
trapPC: DefaultTrapPC ]];
cur ← PO.And[cur, BE[m:[inhibTraps: TRUE], d:[inhibTraps: FALSE]]];
Reschedule Waiting
Set[s:cur, m:[rschlWaiting: TRUE], d:[rschlWaiting: TRUE], out:[
stateException: TRUE,
stateExceptCode: rschlWait,
trapPC:   TrapPC[RescheduleTrap] ]];
cur ← PO.And[cur, BE[m:[rschlWaiting: TRUE], d:[rschlWaiting: FALSE]]];
IFU stack overflow
iStkOverflow ←
PO.And[
BE[m:[iStkOverflow: TRUE],  d:[iStkOverflow: TRUE]],
PO.Or[
BE[m:[pushPending: TRUE], d:[pushPending: TRUE]],
BE[m:[popPending: TRUE], d:[popPending: FALSE]] ] ];
Set[s: PO.And[cur, iStkOverflow], out:[
stateException: TRUE,
stateExceptCode: iStkOFlow,
trapPC:   TrapPC[IFUStackOverflowTrap] ] ];
cur ← PO.And[cur, PO.Not[iStkOverflow]];
EU stack overflow
Set[s:cur, m:[eStkOFlow: TRUE], d:[eStkOFlow: TRUE], out:[
stateException: TRUE,
stateExceptCode: eStkOFlow,
trapPC:   TrapPC[EUStackOverflowTrap] ] ];
cur ← PO.And[cur, BE[m:[eStkOFlow: TRUE], d:[eStkOFlow: FALSE]]];
New unexceptional instruction
Set[s:cur, out:[
stateZero: TRUE,
trapPC: DefaultTrapPC ] ];
Bypassing
noBypass should not need to be dependent on interlock
Set[s:noBypass, out:[aluLt: aBus, aluRt: bBus, st2A: bBus, st3AIsCbus: FALSE]];
cur ← PO.Not[noBypass];
Set[s:cur,     m:[aRegIsC2: TRUE],  d:[aRegIsC2: TRUE],  out:[aluLt: rBus]];
cur ← PO.And[cur, BE[m:[aRegIsC2: TRUE],  d:[aRegIsC2: FALSE]]];
Set[s:cur,     m:[aRegIsC3: TRUE],  d:[aRegIsC3: TRUE],  out:[aluLt: cBus]];
Set[s:cur,     m:[aRegIsC3: TRUE],  d:[aRegIsC3: FALSE], out:[aluLt: aBus]];
cur ← PO.Not[noBypass];
Set[s:cur,      m:[kIsRtOp: TRUE], d:[kIsRtOp: TRUE],  out:[aluRt: kBus]];
cur ← PO.And[cur,  BE[m:[kIsRtOp: TRUE], d:[kIsRtOp: FALSE]]];
Set[s:PO.And[cur, bc2, PO.Not[read2]],          out:[aluRt: rBus]];
cur ← PO.And[cur, PO.Not[PO.And[bc2, PO.Not[read2]]]];
Set[s:cur,     m:[bRegIsC3: TRUE], d:[bRegIsC3: TRUE],  out:[aluRt: cBus]];
Set[s:cur,     m:[bRegIsC3: TRUE], d:[bRegIsC3: FALSE], out:[aluRt: bBus]];
cur ← PO.Not[noBypass];
Set[s:cur,      m:[kIsRtOp: TRUE], d:[kIsRtOp: FALSE],  out:[st2A: bBus]];
cur ← PO.And[cur,  BE[m:[kIsRtOp: TRUE], d:[kIsRtOp: TRUE]]];
Set[s:PO.And[cur, bc2, PO.Not[read2]],          out:[st2A: rBus]];
cur ← PO.And[cur, PO.Not[PO.And[bc2, PO.Not[read2]]]];
Set[s:cur,     m:[bRegIsC3: TRUE], d:[bRegIsC3: TRUE],  out:[st2A: cBus]];
Set[s:cur,     m:[bRegIsC3: TRUE], d:[bRegIsC3: FALSE], out:[st2A: bBus]];
Set[s:PO.And[ PO.Not[noBypass], bc2, passRt ],      out:[res3AIsCbus: TRUE]];
Set[s:PO.And[ PO.Not[noBypass], bc2   ],      out:[st3AIsCbus:  TRUE]];
Set[s:PO.And[ PO.Not[noBypass], read1  ],      out:[res3BIsRdData: TRUE]];
};
DefaultTrapPC: Dragon.HexByte = TrapPC[StackUnderflowTrap];
TrapPC: PROC[trap: DragOpsCross.TrapIndex]
RETURNS[trapPC: Dragon.HexByte] =
{trapPC ← LOOPHOLE[trap, Dragon.HexByte]};
BE: PROC [m, d: MainControlIn] RETURNS[PO.BoolExpr] = {
mRef:  REF MainControlIn ← NARROW[MainControlPLA.mask];
dRef:  REF MainControlIn ← NARROW[MainControlPLA.data];
mRef^ ← m; dRef^ ← d; RETURN[PO.GetBEForDataMask[MainControlPLA]]};
Set: PROC [s: PO.BoolExpr ← NIL, m, d: MainControlIn ← [ ], out: MainControlOut] = {
res: REF MainControlOut ← NARROW[MainControlPLA.out];
out.pipeNotStep1  ← out.pipeCycle123 OR out.pipeKill1;
out.pipeNotStep23 ← out.pipeCycle123 OR out.pipeKill23;
IF s=NIL
THEN s ←       BE[m,d]
ELSE s ←   PO.And[s, BE[m,d] ];
res^ ← out; PO.SetOutForBE[MainControlPLA, s]};
MainControlProc: PUBLIC PROC[argRec: MainControlIn] RETURNS[resRec: MainControlOut] = {
arg: REF MainControlIn  ← NARROW[MainControlPLA.data];
res: REF MainControlOut ← NARROW[MainControlPLA.out];
arg^ ← argRec; PO.GetOutForData[MainControlPLA]; resRec ← res^};
MainControlPLA:  PUBLIC PO.PLA;
GenMainControl: Commander.CommandProc = {
filename: IO.ROPEPO.DefaultCMDLine[cmd.commandLine, defaultFile];
MainControlPLA ← PO.NewPLA[inName: "IFUPLA.MainControlIn", outName: "IFUPLA.MainControlOut"];
GenMainControlPLA[];
PO.WritePLAFile[filename, cmd.out, MainControlPLA] };
ReadMainControl: Commander.CommandProc = {
MainControlPLA ← PO.ReadPLAFile[PO.DefaultCMDLine[cmd.commandLine, defaultFile], cmd.out] };
WriteMainControl: Commander.CommandProc = {PO.WritePLAFile
[PO.DefaultCMDLine[cmd.commandLine, defaultFile], cmd.out, MainControlPLA] };
doc:   IO.ROPE = "Expects the name of the pla file";
defaultFile: IO.ROPE = "MainControl.pla";
Commander.Register[key:"GenMainControl",  proc: GenMainControl,  doc: doc];
Commander.Register[key:"ReadMainControl",  proc: ReadMainControl,  doc: doc];
Commander.Register[key:"WriteMainControl", proc: WriteMainControl, doc: doc];
END.