IFUPLAInstrDecode3:
CEDAR
PROGRAM
IMPORTS IFUPLA, PLAOps EXPORTS IFUPLA =
BEGIN OPEN IFUPLA, PO: PLAOps;
GenInstrDecodePLA3: PUBLIC PROC = {
sglBiAlu: PO.BoolExpr ← BE[m:[alpha:351B], d:[alpha:100B]];
sglUnAlu: PO.BoolExpr ← PO.Or[ BE[m:[alpha:351B], d:[alpha:110B]],
BE[m:[alpha:371B], d:[alpha:160B]],
BE[m:[alpha:375B], d:[alpha:170B]]];
dblUnAlu: PO.BoolExpr ← PO.Or[ BE[m:[alpha:351B], d:[alpha:111B]],
BE[m:[alpha:371B], d:[alpha:161B]]];
dblBiAlu: PO.BoolExpr ← BE[m:[alpha:351B], d:[alpha:101B]];
sglBiCom: PO.BoolExpr ← BE[m:[alpha:371B], d:[alpha:140B]];
dblBiCom: PO.BoolExpr ← BE[m:[alpha:371B], d:[alpha:141B]];
sglUnCom: PO.BoolExpr ← BE[m:[alpha:371B], d:[alpha:150B]];
dblUnCom: PO.BoolExpr ← BE[m:[alpha:371B], d:[alpha:151B]];
sglUnCvt: PO.BoolExpr ← PO.Or[ BE[m:[alpha:373B], d:[alpha:173B]],
BE[m:[alpha:375B], d:[alpha:174B]]];
dblUnCvt: PO.BoolExpr ← BE[m:[alpha:373B], d:[alpha:171B]];
sglBiMult: PO.BoolExpr ← BE[m:[alpha:301B], d:[alpha:200B]];
dblBiMult: PO.BoolExpr ← BE[m:[alpha:301B], d:[alpha:201B]];
setMode: PO.BoolExpr ← BE[m:[alpha:300B], d:[alpha:300B]];
instr: PO.BoolExpr;
state: PO.BoolExpr;
m: InstrDecodeOut;
GenInstrDecodePLA3a:
PROC = {
instr ← PO.And[current, BE[m:[op: instrIsSig], d:[op: dFP]]];
state ← PO.And[instr, BE[m:[state: byteIsSig], d:[state: 0]]];
m ← [
dontGetNextMacro: TRUE,
pcNext: pcBus,
euPBusCmd: StoreFP];
m.xASource ← fpLdMode; Set[s: PO.And[setMode, state], out:m];
m.bReg ← [s, zero];
m.xASource ← fpLdAMsw; Set[s: PO.And[sglUnCom, state], out:m];
m.xASource ← fpLdAMsw; Set[s: PO.And[sglUnAlu, state], out:m];
m.xASource ← fpLdAMsw; Set[s: PO.And[sglUnCvt, state], out:m];
m.xASource ← fpLdALsw; Set[s: PO.And[dblUnCom, state], out:m];
m.xASource ← fpLdALsw; Set[s: PO.And[dblUnAlu, state], out:m];
m.xASource ← fpLdALsw; Set[s: PO.And[dblUnCvt, state], out:m];
m.xASource ← fpLdBMsw; Set[s: PO.And[sglBiCom, state], out:m];
m.xASource ← fpLdBMsw; Set[s: PO.And[sglBiAlu, state], out:m];
m.xASource ← fpLdBMsw; Set[s: PO.And[sglBiMult, state], out:m];
m.xASource ← fpLdBLsw; Set[s: PO.And[dblBiCom, state], out:m];
m.xASource ← fpLdBLsw; Set[s: PO.And[dblBiAlu, state], out:m];
m.xASource ← fpLdBLsw; Set[s: PO.And[dblBiMult, state], out:m];
state ← PO.And[instr, BE[m:[state: byteIsSig], d:[state: 1]]];
m ← [dontGetNextMacro: FALSE]; Set[s: PO.And[setMode, state], out:m];
m ← NoOpMicro; Set[s: PO.And[sglUnCom, state], out:m];
m ← NoOpMicro; Set[s: PO.And[sglUnAlu, state], out:m];
m ← NoOpMicro; Set[s: PO.And[sglUnCvt, state], out:m];
m ← [
dontGetNextMacro: TRUE,
pcNext: pcBus,
bReg: [s, minus1],
euPBusCmd: StoreFP];
m.xASource ← fpLdAMsw; Set[s: PO.And[dblUnCom, state], out:m];
m.xASource ← fpLdAMsw; Set[s: PO.And[dblUnAlu, state], out:m];
m.xASource ← fpLdAMsw; Set[s: PO.And[dblUnCvt, state], out:m];
m.xASource ← fpLdAMsw; Set[s: PO.And[sglBiCom, state], out:m];
m.xASource ← fpLdAMsw; Set[s: PO.And[sglBiAlu, state], out:m];
m.xASource ← fpLdAMsw; Set[s: PO.And[sglBiMult, state], out:m];
m.xASource ← fpLdBMsw; Set[s: PO.And[dblBiCom, state], out:m];
m.xASource ← fpLdBMsw; Set[s: PO.And[dblBiAlu, state], out:m];
m.xASource ← fpLdBMsw; Set[s: PO.And[dblBiMult, state], out:m];
state ← PO.And[instr, BE[m:[state: byteIsSig], d:[state: 2]]];
m ← NoOpMicro; Set[s: PO.And[sglUnCom, state], out:m];
m ← NoOpMicro; Set[s: PO.And[sglUnAlu, state], out:m];
m ← NoOpMicro; Set[s: PO.And[sglUnCvt, state], out:m];
m ← NoOpMicro; Set[s: PO.And[dblUnCom, state], out:m];
m ← NoOpMicro; Set[s: PO.And[dblUnAlu, state], out:m];
m ← NoOpMicro; Set[s: PO.And[dblUnCvt, state], out:m];
m ← NoOpMicro; Set[s: PO.And[sglBiCom, state], out:m];
m ← NoOpMicro; Set[s: PO.And[sglBiAlu, state], out:m];
m ← NoOpMicro; Set[s: PO.And[sglBiMult, state], out:m];
m ← [
dontGetNextMacro: TRUE,
pcNext: pcBus,
bReg: [ s, minus2 ],
euPBusCmd: StoreFP ];
m.xASource ← fpLdALsw; Set[s: PO.And[dblBiCom, state], out:m];
m.xASource ← fpLdALsw; Set[s: PO.And[dblBiAlu, state], out:m];
m.xASource ← fpLdALsw; Set[s: PO.And[dblBiMult, state], out:m];
state ← PO.And[instr, BE[m:[state: byteIsSig], d:[state: 3]]];
m ← NoOpMicro; Set[s: PO.And[sglUnCom, state], out:m];
m ← NoOpMicro; Set[s: PO.And[sglUnAlu, state], out:m];
m ← NoOpMicro; Set[s: PO.And[sglUnCvt, state], out:m];
m ← NoOpMicro; Set[s: PO.And[dblUnCom, state], out:m];
m ← NoOpMicro; Set[s: PO.And[dblUnAlu, state], out:m];
m ← NoOpMicro; Set[s: PO.And[dblUnCvt, state], out:m];
m ← NoOpMicro; Set[s: PO.And[sglBiCom, state], out:m];
m ← NoOpMicro; Set[s: PO.And[sglBiAlu, state], out:m];
m ← NoOpMicro; Set[s: PO.And[sglBiMult, state], out:m];
m ← [
dontGetNextMacro: TRUE,
pcNext: pcBus,
bReg: [ s, minus3 ],
euPBusCmd: StoreFP ];
m.xASource ← fpLdAMsw; Set[s: PO.And[dblBiCom, state], out:m];
m.xASource ← fpLdAMsw; Set[s: PO.And[dblBiAlu, state], out:m];
m.xASource ← fpLdAMsw; Set[s: PO.And[dblBiMult, state], out:m] };
GenInstrDecodePLA3b:
PROC = {
state ← PO.And[instr, BE[m:[state: byteIsSig], d:[state: 4]]];
Set[s:
PO.And[sglUnCom, state], out:[
dontGetNextMacro: FALSE,
deltaSa: pop,
xASource: fpUnldMsw,
euPBusCmd: FetchFPAlu ]];
Set[s:
PO.And[sglUnAlu, state], out:[
dontGetNextMacro: FALSE,
cReg: [ s, zero ],
xASource: fpUnldMsw,
euPBusCmd: FetchFPAlu ]];
Set[s:
PO.And[sglUnCvt, state], out:[
dontGetNextMacro: TRUE,
pcNext: pcBus,
cReg: [ s, zero ],
xASource: fpUnldMsw,
euPBusCmd: FetchFPAlu ]];
m ← NoOpMicro; Set[s: PO.And[dblUnCom, state], out:m];
m ← NoOpMicro; Set[s: PO.And[dblUnAlu, state], out:m];
m ← NoOpMicro; Set[s: PO.And[dblUnCvt, state], out:m];
m ← NoOpMicro; Set[s: PO.And[sglBiCom, state], out:m];
m ← NoOpMicro; Set[s: PO.And[sglBiAlu, state], out:m];
m ← NoOpMicro; Set[s: PO.And[sglBiMult, state], out:m];
m ← NoOpMicro; Set[s: PO.And[dblBiCom, state], out:m];
m ← NoOpMicro; Set[s: PO.And[dblBiAlu, state], out:m];
m ← NoOpMicro; Set[s: PO.And[dblBiMult, state], out:m];
state ← PO.And[instr, BE[m:[state: byteIsSig], d:[state: 5]]];
Set[s:
PO.And[sglUnCvt, state], out:[
dontGetNextMacro: FALSE,
deltaSc: push,
cReg: [ s, one ],
xASource: fpUnldLsw,
euPBusCmd: FetchFPAlu ]];
m ← [
dontGetNextMacro: FALSE,
deltaSa: pop,
deltaSb: pop,
xASource: fpUnldMsw,
euPBusCmd: FetchFPAlu ];
Set[s: PO.And[dblUnCom, state], out:m];
Set[s: PO.And[sglBiCom, state], out:m];
Set[s:
PO.And[dblUnAlu, state], out:[
dontGetNextMacro: TRUE,
pcNext: pcBus,
cReg: [ s, minus1 ],
xASource: fpUnldMsw,
euPBusCmd: FetchFPAlu ]];
m ← [
dontGetNextMacro: FALSE,
deltaSa: pop,
cReg: [ s, minus1 ],
xASource: fpUnldMsw,
euPBusCmd: FetchFPAlu ];
Set[s: PO.And[dblUnCvt, state], out:m];
Set[s: PO.And[sglBiAlu, state], out:m];
Set[s:
PO.And[sglBiMult, state], out:[
dontGetNextMacro: FALSE,
deltaSa: pop,
cReg: [ s, minus1 ],
xASource: fpUnldMsw,
euPBusCmd: FetchFPMult ]];
m ← NoOpMicro; Set[s: PO.And[dblBiCom, state], out:m];
m ← NoOpMicro; Set[s: PO.And[dblBiAlu, state], out:m];
m ← NoOpMicro; Set[s: PO.And[dblBiMult, state], out:m];
state ← PO.And[instr, BE[m:[state: byteIsSig], d:[state: 6]]];
Set[s:
PO.And[dblUnAlu, state], out:[
dontGetNextMacro: FALSE,
cReg: [ s, zero ],
xASource: fpUnldLsw,
euPBusCmd: FetchFPAlu ]];
m ← NoOpMicro; Set[s: PO.And[dblBiCom, state], out:m];
m ← NoOpMicro; Set[s: PO.And[dblBiAlu, state], out:m];
m ← NoOpMicro; Set[s: PO.And[dblBiMult, state], out:m];
state ← PO.And[instr, BE[m:[state: byteIsSig], d:[state: 7]]];
Set[s:
PO.And[dblBiCom, state], out:[
dontGetNextMacro: TRUE,
pcNext: pcBus,
deltaSa: pop,
deltaSb: pop, -- Two more left for next cycle
xASource: fpUnldMsw,
euPBusCmd: FetchFPAlu ]];
Set[s:
PO.And[dblBiAlu, state], out:[
dontGetNextMacro: TRUE,
pcNext: pcBus,
cReg: [ s, minus3 ],
xASource: fpUnldMsw,
euPBusCmd: FetchFPAlu ]];
m ← NoOpMicro; Set[s: PO.And[dblBiMult, state], out:m];
state ← PO.And[instr, BE[m:[state: byteIsSig], d:[state: 8]]];
Set[s:
PO.And[dblBiCom, state], out:[
dontGetNextMacro: FALSE,
deltaSa: pop,
deltaSb: pop, -- Last two
xASource: fpUnldMsw,
euPBusCmd: FetchFPAlu ]];
Set[s:
PO.And[dblBiAlu, state], out:[
dontGetNextMacro: FALSE,
deltaSa: pop,
deltaSb: pop,
cReg: [ s, minus2 ],
xASource: fpUnldLsw,
euPBusCmd: FetchFPAlu ]];
Set[s:
PO.And[dblBiMult, state], out:[
dontGetNextMacro: FALSE,
deltaSa: pop,
deltaSb: pop,
cReg: [ s, minus2 ],
xASource: fpUnldLsw,
euPBusCmd: FetchFPAlu ]];
state ← PO.And[instr, BE[m:[state: byteIsSig], d:[state: 9]]];
Set[s:
PO.And[dblBiMult, state], out:[
dontGetNextMacro: FALSE,
deltaSa: pop,
deltaSb: pop,
cReg: [ s, minus2 ],
xASource: fpUnldLsw,
euPBusCmd: FetchFPMult ]]};
GenInstrDecodePLA3a[];
GenInstrDecodePLA3b[];
GenInstrDecodePLA4[] };
END.