
<<IFUPLAInstrDecode2.mesa>>
<<Copyright © 1984 by Xerox Corporation.  All rights reserved.>>
<<Last edited by TWilliams, August 27, 1984 4:58:00 pm PDT>>
<<Last edited by Curry, November 24, 1984 2:02:39 pm PST>>
<<>>
DIRECTORY
DragOpsCross,
IFUPLA,
PLAOps;

IFUPLAInstrDecode2: CEDAR PROGRAM
IMPORTS IFUPLA, PLAOps EXPORTS IFUPLA =
BEGIN OPEN IFUPLA, PO: PLAOps;

<<Temporary>>
instr: PO.BoolExpr;


GenInstrDecodePLA2:  PUBLIC PROC = {


Set[s:current, m:[op: instrIsSig], d:[op: dIN], out:[
aReg: abStackTop,
xASource: alpha,
cReg: cStackTop,
aluOp: VAdd,
euPBusCmd: IOFetch ]];

Set[s:current, m:[op: instrIsSig], d:[op: dRB], out:[
aReg: abStackTop,
xASource: alpha,
cReg: cStackTop,
aluOp: VAdd,
euPBusCmd: Fetch ]];

Set[s:current, m:[op: instrIsSig], d:[op: dRSB], out:[
aReg: abStackTop,
xASource: alpha,
cReg: [ s, one ],
deltaSc: push,
aluOp: VAdd,
euPBusCmd: Fetch ]];

Set[s:current, m:[op: instrBot4NotSig], d:[op: dLRI0], out:[
aReg: [ l, op47 ],
xASource: alpha,
cReg: [ s, one ],
deltaSc: push,
aluOp: VAdd,
euPBusCmd: Fetch ]];
<<>>
Set[s:current, m:[op: instrIsSig], d:[op: dLGF], out:[    -- Save me for lisp
aReg: euGF,
xASource: betaAlpha,
cReg: [ s, one ],
deltaSc: push,
aluOp: VAdd,
euPBusCmd: Fetch ]];

Set[s:current, m:[op: instrIsSig], d:[op: dRRI], out:[
aReg: [ l, beta47],
xASource: alpha,
cReg: [ l, beta03 ],
aluOp: VAdd,
euPBusCmd: Fetch ]];

Set[s:current, m:[op: instrIsSig], d:[op: dRAI], out:[
aReg: [ aBase, beta47],
xASource: alpha,
cReg: [ l, beta03 ],
aluOp: VAdd,
euPBusCmd: Fetch ]];

<<dRRX is with the RR instructions>>

instr _ PO.And[current, BE[m:[op: instrIsSig], d:[op: dCST]]];
Set[s:instr, m:[state: byteIsSig],    d:[state: 0], out:[
dontGetNextMacro: TRUE,
pcNext: pcBus,
aReg: [ s, minus2 ],
xASource: alpha,
cReg: [ s, one ],
aluOp: VAdd,
euPBusCmd: FetchHold ]];
<<This cycle will invariably be Delayed (automatically) by the pipe since cycle 0 was a fetch into S+1>>
Set[s:instr, m:[state: byteIsSig],    d:[state: 1], out:[
dontGetNextMacro: TRUE,
pcNext: pcBus,
aReg: [ s, one ],
bReg: abStackTop,
aluOp: VSub,
condSel: EZ,
condEffect: microJump ]];    -- IF [S+1] = [S] THEN microJump
Set[s:instr, m:[state: byteIsSig],    d:[state: 2], out:NoOpMicro]; -- Allow ALU result to get back
Set[s:instr, m:[state: byteIsSig],    d:[state: 3], out:NoOpMicro]; -- Allow ALU result to get back
Set[s:instr, m:[state: byteIsSig],    d:[state: 4], out:[    -- [] _ ([S-2]+alpha)^, release hold, S _ S+1
aReg: [ s, minus2 ],
xASource: alpha,
deltaSc: push,
aluOp: VAdd,
euPBusCmd: Fetch ]];
<<Remember that when doing microjumps, you can't get next macro until the condition has been tested since the opcode must be the 
same (cycles 2 and 3 above are necessary).>>
<<([S-2]+alpha)^ _ [S-1], release hold, S _ S+1>>
Set[s:instr, m:[state: byteIsSig],    d:[state: microBranch], out:[
aReg: [ s, minus2 ],
bReg: [  s, minus1 ],
xASource: alpha,
deltaSc: push,
aluOp: VAdd,
euPBusCmd: Store ]];

Set[s:current, m:[op: instrIsSig], d:[op: dOUT], out:[
aReg: abStackTop,
bReg: [ s, minus1 ],
xASource: alpha,
deltaSa: pop,
deltaSb: pop,
aluOp: VAdd,
euPBusCmd: IOStore ]];

Set[s:current, m:[op: instrIsSig], d:[op: dWB], out:[
aReg: abStackTop,
bReg: [ s, minus1 ],
xASource: alpha,
deltaSa: pop,
deltaSb: pop,
aluOp: VAdd,
euPBusCmd: Store ]];

Set[s:current, m:[op: instrIsSig], d:[op: dWSB], out:[
aReg: [ s, minus1 ],
bReg: abStackTop,
xASource: alpha,
deltaSa: pop,
deltaSb: pop,
aluOp: VAdd,
euPBusCmd: Store ]];

Set[s:current, m:[op: instrIsSig], d:[op: dPSB], out:[
aReg: [ s, minus1 ],
bReg: abStackTop,
xASource: alpha,
deltaSa: pop,
aluOp: VAdd,
euPBusCmd: Store ]];

Set[s:current, m:[op: instrBot4NotSig], d:[op: dSRI0], out:[
aReg: [ l, op47 ],
bReg: abStackTop,
xASource: alpha,
deltaSb: pop,
aluOp: VAdd,
euPBusCmd: Store ]];

Set[s:current, m:[op: instrIsSig], d:[op: dWRI], out:[
aReg: [ l, beta47],
bReg: [ l, beta03 ],
xASource: alpha,
aluOp: VAdd,
euPBusCmd: Store ]];

Set[s:current, m:[op: instrIsSig], d:[op: dWAI], out:[
aReg: [ aBase, beta47],
bReg: [ l, beta03 ],
xASource: alpha,
aluOp: VAdd,
euPBusCmd: Store ]];

Set[s:current, m:[op: instrIsSig], d:[op: dFSDB], out:[
xASource: betaAlpha,
cReg: euField ]];

Set[s:current, m:[op: instrIsSig], d:[op: dLIB], out:[
xASource: alpha,
cReg: [ s, one ],
deltaSc: push ]];

Set[s:current, m:[op: instrIsSig], d:[op: dLIDB], out:[
xASource: betaAlpha,
cReg: [ s, one ],
deltaSc: push ]];

Set[s:current, m:[op: instrIsSig], d:[op: dLIQB], out:[
xASource: delGamBetAlp,
cReg: [ s, one ],
deltaSc: push ]];

Set[s:current, m:[op: instrBot3NotSig], d:[op: dLC0], out:[
bReg: [ cBase, op47 ],
cReg: [ s, one ],
deltaSc: push ]];

Set[s:current, m:[op: instrBot4NotSig], d:[op: dLR0], out:[
bReg: [ l, op47 ],
cReg: [ s, one ],
deltaSc: push ]];

Set[s:current, m:[op: instrBot4NotSig], d:[op: dSR0], out:[
bReg: [ s, zero ],
cReg: [ l, op47 ],
deltaSb: pop ]];

Set[s:current, m:[op: instrIsSig], d:[op: dDUP], out:[
bReg: abStackTop,
cReg: [ s, one ],
deltaSc: push ]];

Set[s:current, m:[op: instrIsSig], d:[op: dEXDIS], out:[
bReg: abStackTop,
cReg: [ s, minus1 ],
deltaSa: pop ]];

instr _ PO.And[current, BE[m:[op: instrIsSig], d:[op: dEXCH]]];
Set[s:instr, m:[state: byteIsSig],    d:[state: 0], out:[
dontGetNextMacro: TRUE,
pcNext: pcBus,
bReg: abStackTop,
cReg: [ s, minus1 ] ] ];
Set[s:instr, m:[state: byteIsSig],    d:[state: 1], out:[
dontBypass: TRUE,
bReg: [ s, minus1 ],
cReg: cStackTop ]];

Set[s:current, m:[op: instrIsSig], d:[op: dSEUR], out:[
bReg: abStackTop,
cReg: [ zero, alpha ],
deltaSb: pop ] ];

instr _ PO.And[current, BE[m:[op: instrIsSig], d:[op: dSIFUR]]];
Set[s:instr, m:[state: byteIsSig],    d:[state: 0], out:[
dontGetNextMacro: TRUE,
pcNext: pcBus,
bReg: abStackTop,
cReg: [ zero, alpha ] ] ];
Set[s:instr, m:[state: byteIsSig],    d:[state: 1], out:NoOpMicro];    -- allow ALU result to Result3
Set[s:instr, m:[state: byteIsSig],    d:[state: 2], out:NoOpMicro];    -- allow ALU result to Result3
<<EU driving ifu XBus during A with IFU internal dest specified by level 3 cAddr>>
Set[s:instr, m:[state: byteIsSig],    d:[state: 3], out:[
dontGetNextMacro: FALSE,
deltaSa: pop ]];    -- allow ALU result to Result3

Set[s:current, m:[op: instrIsSig], d:[op: dLEUR], out:[
bReg: [ zero, alpha ],
cReg: [ s, one ],
deltaSc: push ] ];

Set[s:current, m:[op: instrIsSig], d:[op: dADDB], out:[
aReg: abStackTop,
xASource: alpha,
cReg: cStackTop,
aluOp: SAdd,
condSel: OvFl ]];

Set[s:current, m:[op: instrIsSig], d:[op: dADDDB], out:[
aReg: abStackTop,
xASource: betaAlpha,
cReg: cStackTop,
aluOp: SAdd,
condSel: OvFl ]];

Set[s:current, m:[op: instrIsSig], d:[op: dSUBB], out:[
aReg: abStackTop,
xASource: alpha,
cReg: cStackTop,
aluOp: SSub,
condSel: OvFl ]];

Set[s:current, m:[op: instrIsSig], d:[op: dSHL], out:[
aReg: abStackTop,
bReg: [ cBase, zero ],
xASource: betaAlpha,
cReg: cStackTop,
aluOp: FOPK ]];

Set[s:current, m:[op: instrIsSig], d:[op: dSHR], out:[
aReg: abStackTop,
bReg: [ s, zero ],
xASource: betaAlpha,
cReg: cStackTop,
aluOp: FOPK ]];

Set[s:current, m:[op: instrIsSig], d:[op: dADD], out:[
aReg: [ s, minus1 ],
bReg: abStackTop,
cReg: [ s, minus1 ],
deltaSa: pop,
aluOp: SAdd,
condSel: OvFl,
condEffect: macroTrap ]];

Set[s:current, m:[op: instrIsSig], d:[op: dSUB], out:[
aReg: [ s, minus1 ],
bReg: [  s, zero ],
cReg: [ s, minus1 ],
deltaSa: pop,
aluOp: SSub,
condSel: OvFl,
condEffect: macroTrap ]];

Set[s:current, m:[op: instrIsSig], d:[op: dBNDCK], out:[
aReg: [ s, minus1 ],
bReg: [  s, zero ],
deltaSa: pop,
aluOp: VSub,    -- This does not need to be BndChk since cReg is not used
condSel: BC,
condEffect: macroTrap ]];

instr _ PO.And[current, BE[m:[op: instrIsSig], d:[op: dUMUL]]];
Set[s: instr, m:[state: byteIsSig],    d:[state: 0], out:[
dontGetNextMacro: TRUE,
pcNext: pcBus,
aReg: [  s, zero ],        -- Lt _ S=Multiplicand
bReg: [  s, minus1 ],    -- MQ _ Rt _ Multiplier
cReg: [  s, minus1 ],    -- Product.msw
aluOp: MulLdU,
condSel: EZ,                -- IF aluout=Lt=Multiplicand is zero then quit
condEffect: microJump]]; -- cycle _ 32 if zero
FOR cycle: INT IN [1..17] DO
Set[s: instr, m:[state: byteIsSig], d:[state: cycle], out: [
dontGetNextMacro: TRUE,
pcNext: pcBus,
aReg: [  s, minus1 ],    -- Product.msw
bReg: [  s, zero ],        -- Multiplicand
cReg: [  s, minus1 ],    -- Product.msw
aluOp: MulStep ]] ENDLOOP;
Set[s: instr, m:[state: byteIsSig], d:[state: 17], out:[
dontGetNextMacro: TRUE,
pcNext: pcBus,
aReg: [  s, minus1 ],    -- Product.msw
bReg: [  s, zero ],        -- Multiplicand
cReg: [  s, minus1 ],    -- Product.msw
aluOp: MulAdj ]];
Set[s: instr, m:[state: byteIsSig], d:[state: 18], out:[
dontGetNextMacro: FALSE,
cReg: [  s, zero ],        -- Product.lsw _ MQ
aluOp: RdMQ ]];
Set[s: instr, m:[state: byteIsSig], d:[state: microBranch], out:[
aReg: constantZero,        -- Product.msw
bReg: constantZero,        -- Multiplicand
cReg: [  s, minus1 ],    -- Product.msw _ 0
aluOp: Or ]];

instr _ PO.And[current, BE[m:[op: instrIsSig], d:[op: dUDIV]]];
Set[s: instr, m:[state: byteIsSig], d:[state: 0], out:[
dontGetNextMacro: TRUE,
pcNext: pcBus,
aReg: [  s, minus2 ],    -- Dividend MSW
bReg: [  s, minus1 ],    -- Dividend LSW
cReg: [  s, one ],
aluOp: DivLdDbl]];
Set[s: instr, m:[state: byteIsSig], d:[state: 1], out:[
dontGetNextMacro: TRUE,
pcNext: pcBus,
aReg:        [  s, one ],        -- Dividend.msw (temp location)
bReg:        [  s, zero ],        -- Divisor
cReg:        [  s, one ],
aluOp:    DivLdU ]];        -- Dividend.msw (temp location)
Set[s: instr, m:[state: byteIsSig], d:[state: 2], out:[
dontGetNextMacro: TRUE,
pcNext: pcBus,
aReg:        [  s, one ],        -- Dividend.msw (temp location)
bReg:        [  s, zero ],        -- Divisor
cReg:        [  s, minus1 ],    -- Remainder destination
aluOp:        DivCkU,
condSel:        DivOvFl,
condEffect:    macroTrap ]];
FOR cycle: INT IN [3..33] DO
Set[s: instr, m:[state: byteIsSig], d:[state: cycle], out:[
dontGetNextMacro: TRUE,
pcNext: pcBus,
aReg:        [  s, minus1 ],    -- Remainder source
bReg:        [  s, zero ],        -- Divisor
cReg:        [  s, minus1 ],    -- Remainder destination
aluOp:    DivStep ]];
ENDLOOP;
Set[s: instr, m:[state: byteIsSig], d:[state: 34], out:[
dontGetNextMacro: TRUE,
pcNext: pcBus,
aReg:        [  s, minus1 ],    -- Remainder source
bReg:        [  s, zero ],        -- Divisor
cReg:        [  s, minus1 ],    -- Remainder destination
aluOp:    DivAdjM ]];
Set[s: instr, m:[state: byteIsSig], d:[state: 35], out:[
dontGetNextMacro: TRUE,
pcNext: pcBus,
aReg:        [  s, minus1 ],    -- Remainder source
bReg:        [  s, zero ],        -- Divisor
cReg:        [  s, minus1 ],    -- Remainder destination
aluOp:    DivAdj ]];
Set[s: instr, m:[state: byteIsSig], d:[state: 36], out:[
dontGetNextMacro: TRUE,
pcNext: pcBus,
cReg:        [  s, minus2 ],    -- Quotient destination
aluOp:    RdMQ ]];
Set[s: instr, m:[state: byteIsSig], d:[state: 37], out:[
dontGetNextMacro: FALSE,
aReg:        [  s, minus2 ],    -- Quotient source
bReg:        constantZero,        -- Zero
cReg:        [  s, minus2 ],    -- Quotient destination
deltaSa:    pop,
aluOp:    SAdd ]];

GenInstrDecodePLA3[]; -- Arbitrary break
};  -- of GenInstrDecodePLA2


END.