IFUPLA:
CEDAR
DEFINITIONS =
BEGIN
MainControlProc: PROC[args: MainControlIn] RETURNS[result: MainControlOut];
InstrDecodeProc: PROC[args: InstrDecodeIn] RETURNS[result: InstrDecodeOut];
FetchControlProc: PROC[args: FetchControlIn] RETURNS[result: FetchControlOut];
FetchPreDecodeProc: PROC[args: FetchPreDecodeIn] RETURNS[result: FetchPreDecodeOut];
MainControlIn:
TYPE =
RECORD [
-- default must be zero for use initializing sigificance arg
reseting: BOOL ← FALSE,
wereReseting: BOOL ← FALSE,
epFaulted: BOOL ← FALSE,
fpFaulted: BOOL ← FALSE,
rejected: BOOL ← FALSE,
aluCondResult2: BOOL ← FALSE,
condEffect2: CondEffect ← LOOPHOLE[0],
noBypassing: BOOL ← FALSE,
pCmndLev1Rd: BOOL ← FALSE,
pCmndLev2Rd: BOOL ← FALSE,
notPassRtIfAZero: BOOL ← FALSE,
aluOpFOP: BOOL ← FALSE,
kIsRtOp: BOOL ← FALSE,
cRegIsField: BOOL ← FALSE,
aRegIsZero: BOOL ← FALSE,
aRegIsC2: BOOL ← FALSE,
aRegIsC3: BOOL ← FALSE,
bRegIsC2: BOOL ← FALSE,
bRegIsC3: BOOL ← FALSE,
instrDone: BOOL ← FALSE,
instrDelayed: BOOL ← FALSE,
getNextMacro: BOOL ← FALSE,
macroJump: BOOL ← FALSE,
ipFaulted: BOOL ← FALSE,
trapsEnbled: BOOL ← FALSE,
rschlWaiting: BOOL ← FALSE,
iStkOverflow: BOOL ← FALSE,
pushPending: BOOL ← FALSE,
popPending: BOOL ← FALSE,
eStkOverFlow: BOOL ← FALSE ];
MainControlOut:
TYPE =
RECORD [
microBranch: BOOL ← FALSE,
exception: BOOL ← FALSE,
exceptionCode: ExceptionCode ← 0, -- new state is either this exception code or cycle #
delayNextInstr: BOOL ← FALSE,
pipeAdv0: BOOL ← FALSE,
pipeAdv1: BOOL ← FALSE, -- not (pipeCycle123 or pipeKill1)
pipeAdv2: BOOL ← FALSE, -- not (pipeCycle123 or pipeKill2)
pipeAdv3: BOOL ← FALSE, -- not (pipeCycle123 or pipeCCTrap3 or pipeFault3
pipeCycle123: BOOL ← FALSE,
pipeKill1: BOOL ← FALSE,
pipeKill2: BOOL ← FALSE,
pipeCCTrap3: BOOL ← FALSE,
pipeFault3: BOOL ← FALSE,
aluLt: Dragon.ALULeftSources ← aBus,
aluRt: Dragon.ALURightSources ← bBus,
st2A: Dragon.Store2ASources ← bBus,
st3AIsCbus: BOOL ← FALSE,
res3AIsCbus: BOOL ← FALSE,
res3BIsRdData: BOOL ← FALSE
];
InstrDecodeIn:
TYPE =
RECORD [
-- default must be zero for use initializing sigificance arg
cycle: Dragon.HexByte ← 0,
exception: BOOL ← FALSE,
delayNextInstr: BOOL ← FALSE,
instReady: BOOL ← FALSE,
op: DragOpsCross.Inst ← LOOPHOLE[0],
alpha: Dragon.HexByte ← 0,
beta: Dragon.HexByte ← 0,
iStkEmpty: BOOL ← FALSE,
pushPending: BOOL ← FALSE,
popPending: BOOL ← FALSE,
userMode: BOOL ← FALSE ];
InstrDecodeOut:
TYPE =
RECORD [
aReg: ABReg ← constantZero,
bReg: ABReg ← constantZero,
microJump: BOOL ← FALSE,
macroJump: BOOL ← FALSE,
dontGetNextMacro: BOOL ← FALSE,
instrDelayed: BOOL ← FALSE,
pcBusSrc: PCBusSrc ← pc,
pcNext: PCNext ← pcBus,
pclsPipeSrc: PCLSPipeSrc ← old,
cReg: CReg ← inhibitStore,
lSource: LSource ← [ l, zero ],
sSource: SSource ← [ s, deltaS ],
popSa: BOOL ← FALSE,
popSb: BOOL ← FALSE,
pushSc: BOOL ← FALSE,
xASource: XaSource ← none,
kIsRtOp: BOOL ← FALSE,
aluOp: Dragon.ALUOps ← Or,
notPassRtIfAZero: BOOL ← FALSE,
aluOpFOP: BOOL ← FALSE,
condSel: Dragon.CondSelects ← False,
condEffect: CondEffect ← macroTrap,
noBypassing: BOOL ← FALSE, -- TRUE for EXCH
push: BOOL ← FALSE,
pop: BOOL ← FALSE,
euPCmnd: Dragon.PBusCommands ← NoOp,
fpCSLdAlu: BOOL ← FALSE,
fpCSLdMult: BOOL ← FALSE,
fpCSUnldAlu: BOOL ← FALSE,
fpCSUnldMult: BOOL ← FALSE,
fpCheckStatue: BOOL ← FALSE,
changeTrapsEnbledBA: BOOL ← FALSE,
changeUserModeBA: BOOL ← FALSE,
changeFPAluArgBA: BOOL ← FALSE,
changeFPMultArgBA: BOOL ← FALSE,
newTrapsEnbledBA: BOOL ← FALSE,
newUserModeBA: BOOL ← FALSE,
newFPAluArgBA: FPArgType ← clear,
newFPMultArgBA: FPArgType ← clear
];
DefaultMicro: InstrDecodeOut = [];
BlankMicro: InstrDecodeOut = [];
NoOpMicro: InstrDecodeOut =
[dontGetNextMacro: TRUE, pcBusSrc: pc, pcNext: pcBus];
Delayed: InstrDecodeOut =
[dontGetNextMacro: TRUE, pcBusSrc: pc, pcNext: pcBus, instrDelayed: TRUE];
Fetch
ControlIn:
TYPE =
RECORD [
-- default must be zero for use initializing sigificance arg
jump: BOOL ← FALSE,
getNext: BOOL ← FALSE,
hold: BOOL ← FALSE,
reject: BOOL ← FALSE,
jumping: BOOL ← FALSE,
jumpInProgress: BOOL ← FALSE,
jumpPending: BOOL ← FALSE,
fetching: BOOL ← FALSE,
roomFor1: BOOL ← FALSE,
roomFor2: BOOL ← FALSE,
faulted: BOOL ← FALSE,
fault: Dragon.PBusFaults ← None,
opLength: [0..7] ← LOOPHOLE[0],
offSet: [0..3] ← LOOPHOLE[0]
];
FetchControlOut:
TYPE =
RECORD [
-- default must be zero
jumpInProgress: BOOL ← FALSE,
jumpPending: BOOL ← FALSE,
newFetch: BOOL ← FALSE,
fetching: BOOL ← FALSE,
faulted: BOOL ← FALSE,
incrPrefetch: BOOL ← FALSE,
wt: WtIndexCtl ← [ ],
rd: RdIndexCtl ← [ ]
];
Fetch
PreDecodeIn:
TYPE =
RECORD [
-- default must be zero
preOp: DragOpsCross.Inst ← LOOPHOLE[0],
atLeast1: BOOL ← FALSE,
atLeast2: BOOL ← FALSE,
atLeast3: BOOL ← FALSE,
atLeast5: BOOL ← FALSE
];
FetchPreDecodeOut:
TYPE =
RECORD [
-- default must be zero
instReady: BOOL ← FALSE,
opLength: [0..7] ← 0,
pcBranchOffSet: PCBranchOffSet ← [ ]
];
WtIndexCtl:
TYPE =
RECORD[
set0: BOOL ← FALSE,
inc0: BOOL ← FALSE,
inc1: BOOL ← FALSE ];
RdIndexCtl:
TYPE =
RECORD[
set0: BOOL ← FALSE,
set1: BOOL ← FALSE,
set2: BOOL ← FALSE,
set3: BOOL ← FALSE,
inc0: BOOL ← FALSE,
inc1: BOOL ← FALSE,
inc2: BOOL ← FALSE,
inc3: BOOL ← FALSE,
inc5: BOOL ← FALSE ];
PCBranchOffSet:
TYPE =
RECORD[ -- should probably just decode opcode directly
alphaBeta: BOOL ← FALSE,
beta: BOOL ← FALSE,
alpha: BOOL ← FALSE,
abgd: BOOL ← FALSE ];
fixedMicroBranch: Dragon.HexByte = 64;
ExceptionCode:
TYPE = Dragon.HexByte;
prioritySig :ExceptionCode = 10B; -- 1xxx test used to identify these in PLA-B
exceptionSig :ExceptionCode = 07B; -- 1xxx test used to identify these in PLA-B
highPriority :ExceptionCode = 10B; -- 1xxx test used to identify these in PLA-B
High priority (not delayed by an interlock)
reseting :ExceptionCode = 17B;
reset :ExceptionCode = 16B;
epFault :ExceptionCode = 13B;
fpFault :ExceptionCode = 12B;
euCC :ExceptionCode = 11B;
cJump :ExceptionCode = 10B;
Low priority (happen at or below the priority of delayNextInstr generated in phA)
modeFault :ExceptionCode = 05B; --
iFtchFault :ExceptionCode = 04B; --
rschlWait :ExceptionCode = 02B;
iStkOFlow :ExceptionCode = 01B;
eStkOFlow :ExceptionCode = 00B;
CondEffect: TYPE = MACHINE DEPENDENT {macroTrap(0),macroJump,microJump,res(3)};
IStackPostEffect: TYPE = MACHINE DEPENDENT {none(0), push, pop, res(3)};
TrappingControl: TYPE = MACHINE DEPENDENT {noChange(0), enable, disable, res(3)};
FPArgType: TYPE = MACHINE DEPENDENT {clear, single, integer, double};
PCBusSrc:
TYPE =
MACHINE
DEPENDENT
{pc(0), offSetPC, stack, delGamBetAlp, xA, pipe3, trapGen, xopGen};
PCNext: TYPE = MACHINE DEPENDENT {seqPC(0), pcBus(1)};
PCLSPipeSrc:
TYPE =
MACHINE
DEPENDENT
{holdLastEntry(0), old(1), seqPCnewLS(2), offSetPCnewLS(3)};
XaSource:
TYPE =
MACHINE
DEPENDENT {
none(0),
alpha(8), beta(9), betaAlpha(10), delGamBetAlp(11),
bReg(12), -- This just means Lev1Dr nop
reserve15,
fpUnldMsw(16), fpLdBSgl(17), fpLdBMsw(18), fpLdBLsw(19),
fpUnldLsw(20), fpLdASgl(21), fpLdAMsw(22), fpLdALsw(23)};
This arrangement allows the constant generator to operate off the low 4 bits. Bit 3 doubles as the level1XBusDr control. Bit 4 is the level2XBusDr control. The euSwap BOOL must be specified separately. The constants below can be used in PLA's using XaSource as an input type.
constSig: XaSource = reserve15; -- low 4 bits
xALev1Dr: XaSource = alpha;
xALev2Dr: XaSource = fpUnldMsw; -- 16
ABReg: TYPE = RECORD [ lt: ABSourceLt, rt: ABSourceRt ]; -- 7 bits
ABSourceLt: TYPE = MACHINE DEPENDENT {cBase(0), aBase, s, l, iRef, zero};
ABSourceRt:
TYPE =
MACHINE
DEPENDENT {
zero(0), one(1), two(2), three(3),
minus4(4), minus3(5), minus2(6), minus1(7),
op47(8), alpha(9), alpha03(10), alpha47(11),
deltaS(12), beta(13), beta03(14), beta47(15)};
CReg: TYPE = RECORD [ lt: CSourceLt, rt: CSourceRt ]; -- 7 bits
CSourceLt: TYPE = MACHINE DEPENDENT {aBase(0), cBase, l, s, zero, iRef};
CSourceRt:
TYPE =
MACHINE
DEPENDENT {
-- addr bit 1 invrtd from ABSourceRt
minus4(0), minus3(1), minus2(2), minus1(3),
zero(4), one(5), two(6), three(7),
deltaS(8), beta(9), beta03(10), beta47(11),
op47(12), alpha(13), alpha03(14), alpha47(15)};
LSource: TYPE = RECORD [ lt: LSourceLt, rt: LSourceRt ]; -- 4 bits
LSourceLt: TYPE = MACHINE DEPENDENT {l(0), s, zero, l3};
LSourceRt: TYPE = MACHINE DEPENDENT { zero(0), alpha, stack, one};
SSource: TYPE = RECORD [ lt: SSourceLt, rt: SSourceRt ]; -- 4 bits
SSourceLt: TYPE = MACHINE DEPENDENT {s(0), l, zero, s3};
SSourceRt: TYPE = MACHINE DEPENDENT { deltaS(0), alpha, zero, one};
These must agree with DragOpsCross.ProcessorRegister
abStackTop: ABReg = [ s , zero ];
cStackTop: CReg = [ s , zero ];
constantZero: ABReg = [ cBase , zero ];
euField: CReg = [ aBase , minus1 ];
inhibitStore: CReg = [ aBase , minus4 ];
euGF: ABReg = [ aBase , zero ];
ifuXBus: CReg = [ iRef , minus4 ];
byteIsSig: Dragon.HexByte = 377B;
byteNotSig: Dragon.HexByte = 000B;
byteBot7NotSig: Dragon.HexByte = 200B;
byteBot6NotSig: Dragon.HexByte = 300B;
instrIsSig: DragOpsCross.Inst = LOOPHOLE[377B];
instrBot1NotSig: DragOpsCross.Inst = LOOPHOLE[376B];
instrBot3NotSig: DragOpsCross.Inst = LOOPHOLE[370B];
instrBot4NotSig: DragOpsCross.Inst = LOOPHOLE[360B];
instrBot5NotSig: DragOpsCross.Inst = LOOPHOLE[340B];
instrBot6NotSig: DragOpsCross.Inst = LOOPHOLE[300B];
Used by InstrDecode
current: PLAOps.BoolExpr;
GenInstrDecodePLA1: PROC;
GenInstrDecodePLA2: PROC;
GenInstrDecodePLA3: PROC;
GenInstrDecodePLA4: PROC;
BE: PROC [m, d: InstrDecodeIn] RETURNS[PLAOps.BoolExpr];
Set: PROC [s: PLAOps.BoolExpr ← NIL, m, d: InstrDecodeIn ← [ ], out: InstrDecodeOut];
ControlPipeRec:
TYPE =
RECORD [ -- ~35 bits - This is an aid to the ControlPipe Rose sim
drXa2Lev: BOOL ← FALSE,
drXa3Lev: BOOL ← FALSE,
push: BOOL ← FALSE,
pop: BOOL ← FALSE,
epCmnd: Dragon.PBusCommands ← NoOp,
fpCSUnAlu: BOOL ← FALSE,
fpCSUnMult: BOOL ← FALSE,
fpCheckStatus: BOOL ← FALSE,
fpCSLdAlu: BOOL ← FALSE,
fpCSLdMult: BOOL ← FALSE,
aluLeftSrc: Dragon.ALULeftSources ← aBus,
aluRightSrc: Dragon.ALURightSources ← bBus,
store2ASrc: Dragon.Store2ASources ← bBus,
aluOp: Dragon.ALUOps ← Or,
condSel: Dragon.CondSelects ← False,
st3AisCBus: BOOL ← FALSE,
res3AisCBus: BOOL ← FALSE,
condEffect: CondEffect ← macroTrap,
checkParity: BOOL ← FALSE,
writeToPBus: BOOL ← FALSE,
res3BisPBus: BOOL ← FALSE ];
IFUStatusRec:
TYPE =
MACHINE
DEPENDENT
RECORD [
rescheduleSet (0: 0.. 0): BOOL ← FALSE,
reschedule (0: 1.. 1): BOOL ← FALSE,
reschedulePad (0: 2.. 3): [0..4) ← 0,
trapsEnabledSet (0: 4.. 4): BOOL ← FALSE,
trapsEnabled (0: 5.. 5): BOOL ← FALSE,
trapsEnabledPad (0: 6.. 7): [0..4) ← 0,
userModeSet (0: 8.. 8): BOOL ← FALSE,
userMode (0: 9.. 9): BOOL ← FALSE,
userModePad (0:10..11): [0..4) ← 0,
fpArgAluSet (0:12..12): BOOL ← FALSE,
fpArgAlu (0:13..14): FPArgType ← clear,
fpArgAluPad (0:15..15): BOOL ← FALSE,
fpArgMultSet (0:16..16): BOOL ← FALSE,
fpArgMult (0:17..18): FPArgType ← clear,
fpArgMulPad (0:19..31): [0..8192) ← 0 ];
END.